DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited within the IDS document (dated August 21, 2024) have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites “wherein the thickness of the core insulating layer is 800 µm or more” (emphasis added). This limitation renders the claim indefinite, as this is an open-ended range and the exact metes and bounds of the claim cannot be ascertained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 8, and 10-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 2025/0385145 A1, hereinafter referred to as ‘Chen’).
As to claim 1, Chen teaches a passive component embedded substrate comprising:
a core substrate (20) including a core insulating layer that includes a cavity (S1, S2);
a passive component (21, 22, see also paragraphs 0032-0033);
a thickness supplementary layer (26) attached to a first surface of the passive component; and
an encapsulant (24) that fills the cavity and is on the passive component,
wherein the thickness supplementary layer and at least a portion of the passive component is within the cavity. See also figures 2A-G.
As to claim 5, Chen teaches the thickness supplementary layer (26) comprises an adhesive film. See paragraphs 0032-0034.
As to claim 8, Chen teaches the encapsulant (24) is on at least one from among two surfaces of the core substrate (20) that face away from each other. See figure 2C.
As to claim 10, Chen teaches a thickness of the passive component (21, 22) is thinner than a thickness of the core insulating layer. See figure 2C.
As to claim 11, Chen teaches a wiring structure on a surface of the core substrate. See figures 2F and 2G.
As to claim 12, Chen teaches a passive component embedded substrate comprising:
a core substrate (20) comprising:
a core insulating layer that includes a cavity (S1, S2);
a first core wiring layer (201) and a second core wiring layer (201) respectively on two surfaces of the core insulating layer that face away from each other; and
a through via (201, 202) that penetrates the core insulating layer such as to electrically connect the first core wiring layer and the second core wiring layer;
a passive component (21, 22) comprising an electrode (210/211, 220/221) on a first surface of the passive component;
a thickness supplementary layer (26) attached to a second surface of the passive component, that is opposite to the first surface;
an encapsulant (24) on the passive component;
a first wiring structure (23) on the first surface of the passive component and electrically connected to each of the core substrate and the passive component; and
a second wiring structure (23) on the second surface of the passive component and electrically connected to the core substrate,
wherein the thickness supplementary layer and at least a portion of the passive component is within the cavity. See figures 2A-2G.
As to claim 13, Chen teaches the through via comprises an insulating material (203) and a conductive material (201) surrounding the insulating material.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ham et al. (US 2022/0301975 A1, hereinafter referred to as ‘Ham’).
As to claim 1, Ham teaches a passive component embedded substrate comprising:
a core substrate (101) including a core insulating layer that includes a cavity (C2);
a passive component (300, see also paragraph 0073);
a thickness supplementary layer (300T) attached to a first surface of the passive component; and
an encapsulant (112) that fills the cavity and is on the passive component,
wherein the thickness supplementary layer and at least a portion of the passive component is within the cavity. See e.g. figure 5.
As to claim 4, Ham teaches a side surface of the thickness supplementary layer (300T) is coplanar with a side surface of the passive component (300). See figure 5.
As to claim 5, Ham teaches the thickness supplementary layer (300T) comprises an adhesive film. See paragraph 0074.
Claims 1, 3-5, 8, 10-12, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kyozuka et al. (US 2014/0070396 A1, hereinafter referred to as ‘Kyozuka’).
As to claim 1, Kyozuka teaches a passive component embedded substrate comprising:
a core substrate (10) including a core insulating layer that includes a cavity (10X);
a passive component (30, see also paragraph 0185);
a thickness supplementary layer (31) attached to a first surface of the passive component; and
an encapsulant (40) that fills the cavity and is on the passive component,
wherein the thickness supplementary layer and at least a portion of the passive component is within the cavity. See e.g. figure 7.
As to claim 3, Kyozuka teaches a first surface of the thickness supplementary layer (31), that is opposite to a second surface of the thickness supplementary layer that is attached to the passive component (30), is coplanar with (shown in figure 7) a surface of the core insulating layer (10).
As to claim 4, Kyozuka teaches a side surface of the thickness supplementary layer (31) is coplanar with a side surface of the passive component (30). See figure 7.
As to claim 5, Kyozuka teaches the thickness supplementary layer (31) comprises an adhesive film. See paragraphs 0039-0040.
As to claim 8, Kyozuka teaches the encapsulant (40) is on at least one from among two surfaces of the core substrate (10) that face away from each other. See figure 7.
As to claim 10, Kyozuka teaches a thickness of the passive component (30) is thinner than a thickness of the core insulating layer (10). See figure 7.
As to claim 11, Kyozuka teaches a wiring structure (23,24) on a surface of the core substrate. See figure 7.
As to claim 12, Kyozuka teaches a passive component embedded substrate comprising:
a core substrate (10) comprising:
a core insulating layer that includes a cavity (10X);
a first core wiring layer (23) and a second core wiring layer (24) respectively on two surfaces of the core insulating layer that face away from each other; and
a through via (11) that penetrates the core insulating layer such as to electrically connect the first core wiring layer and the second core wiring layer;
a passive component (30) comprising an electrode (30P) on a first surface of the passive component;
a thickness supplementary layer (31) attached to a second surface of the passive component, that is opposite to the first surface;
an encapsulant (40, 21) on the passive component;
a first wiring structure (51) on the first surface of the passive component and electrically connected to each of the core substrate and the passive component; and
a second wiring structure (91) on the second surface of the passive component and electrically connected to the core substrate,
wherein the thickness supplementary layer and at least a portion of the passive component is within the cavity. See figure 7.
As to claim 14, Kyozuka teaches the encapsulant (40, 21) is on the two surfaces of the core substrate that face away from each other, and
the passive component embedded substrate further comprises:
a first via (51A) penetrating the encapsulant such as to electrically connect the first wiring structure (51) to the electrode of the passive component;
a second via (51A) penetrating the encapsulant such as to electrically connect the first wiring structure to the first core wiring layer; and
a third via (91A) penetrating the encapsulant such as to electrically connect the second wiring structure to the second core wiring layer. See also annotated figure 7 below.
As to claim 15, Kyozuka teaches the third via (91A) is tapered in a direction opposite to a direction in which the first via and the second via are tapered. See also annotated figure 7 below.
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As to claim 16, Kyozuka teaches a first protective layer (60) on the first wiring structure; and a second protective layer (92) on the second wiring structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kyozuka as applied to claim 1 above, and further in view of Sprague et al. (US 3,149,399, hereinafter referred to as ‘Sprague’).
As to claim 9, Kyozuka teaches the passive component embedded substrate, as noted above in the rejection of claim 1. Kyozuka also teaches the chip (30) to be a silicon chip (see paragraphs 0037-0038).
Kyozuka also teaches that chip (30) can be a passive device, specifically a chip resistor or a chip capacitor (in paragraph 0185). However, Kyozuka does not explicitly teach that the passive device examples from paragraph 0185 are also silicon, as noted by Kyozuka in paragraphs 0037-0038.
Sprague teaches that capacitors can indeed be made of silicon (see title and columns 1 and 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kyozuka with a silicon capacitor as taught by Sprague, since it is notoriously well known to those of ordinary skill in the art to use silicon in semiconductor devices (including capacitors) as well as using silicon for its thermal matching properties in comparison to the other materials used in the semiconductor package (e.g. core substrate and encapsulants).
Allowable Subject Matter
Claims 17, 19, and 20 are allowable.
The following is an examiner’s statement of reasons for allowability.
The prior art of record does not teach or suggest the disclosed invention regarding a semiconductor package comprising:
a passive component embedded substrate; and
a semiconductor chip on the passive component embedded substrate and electrically connected to the passive component embedded substrate,
wherein a thickness of the passive component is 600 µm to 780 µm,
wherein a thickness of the core insulating layer is thicker than the thickness of the passive component, and
wherein the semiconductor chip is electrically connected to the passive component by the first wiring structure, as recited within independent claim 17.
Claims 19 and 20 depend from claim 17.
Claims 2, 6, and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000.
/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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