Prosecution Insights
Last updated: October 23, 2026
Application No. 18/811,736

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §DOUBLEPATENT
Filed
Aug 21, 2024
Priority
Apr 01, 2019 — CN 201910256992.7 +3 more
Examiner
PRENTY, MARK V
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
676 granted / 740 resolved
+31.4% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
8 currently pending
Career history
746
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
29.3%
-10.7% vs TC avg
§102
39.4%
-0.6% vs TC avg
§112
21.3%
-18.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 740 resolved cases

Office Action

§DOUBLEPATENT
This Office Action is in response to the papers filed on August 21, 2024. Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, respectively, of Lin (parent United States Patent 12,100,750) together with Jones (United States Patent 4,675,7161). As to independent claim 1, Lin’s claim 1 recites a semiconductor device, comprising: a gate isolation structure on a shallow trench isolation (STI); a first epitaxial layer on one side of the gate isolation structure; a second epitaxial layer on another side of the gate isolation structure; and a contact etch stop layer (CESL) on the gate isolation structure. The difference between this application’s claim 1 and Lin’s claim 1 is the former further recites a spacer around the gate isolation structure. Jones teaches forming sidewall spacers on a semiconductor device’s gates to improve step coverage (see the entire patent, including the Abstract and Fig. 9’s sidewall spacers 34). It would have been obvious to one skilled in the art to form sidewall spacers around Lin’s claim 1 gate isolation structure to improve step coverage as taught by Jones. As to dependent claim 2, Lin’s dependent claim 2 further recites: first fin-shaped structures directly under the first epitaxial layer; and second fin-shaped structures directly under the second epitaxial layer, wherein the STI surrounds the first fin-shaped structures and the second fin-shaped structures. As to dependent claim 3, Lin’s dependent claim 3 further recites wherein a top surface of the gate isolation structure is even with a top surface of the first epitaxial layer. As to dependent claim 4, Lin’s dependent claim 4 further recites the contact etch stop layer (CESL) on the gate isolation structure, the STI, part of the first epitaxial layer, and part of the second epitaxial layer. As to dependent claim 5, Lin’s dependent claim 5 further recites: an interlayer dielectric (ILD) layer on the CESL; a first contact plug on one side of the ILD layer and directly on the first epitaxial layer; and a second contact plug on another side of the ILD layer and directly on the second epitaxial layer. Registered practitioners can telephone the examiner at (571) 272-1843. Any voicemail message left for the examiner should include the registration number of the registered practitioner calling. The examiner’s supervisor is Wael Fahmy, whose telephone number is (571) 272-1705. /MARK V PRENTY/Primary Examiner, Art Unit 2814 1 The Jones patent’s BRIEF DESCRIPTION OF THE DRAWINGS (column 1, line 62, through column 2, line 6) and DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT (column 2, line 7, through column 6, line 20) are incorrect. The examiner respectfully submits, however, that the Jones patent’s spacer teaching is still readily understood from the rest of the patent, including the title, abstract, Fig. 9, SUMMARY OF THE INVENTION (column 1, lines 40-53), and claims (column 6, lines 20-44).
Read full office action

Prosecution Timeline

Aug 21, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772816
SELF-ALIGNED BACKSIDE CONTACT IN NANOSHEET WITHOUT BDI
4y 1m to grant Granted Oct 20, 2026
Patent 12772730
ORGANIC LIGHT EMITTING DEVICE
3y 0m to grant Granted Oct 20, 2026
Patent 12751019
SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME
3y 8m to grant Granted Sep 29, 2026
Patent 12733410
Hydrogen and Hydrocarbon Plasma Treatment of Phase Change Memory Material
3y 11m to grant Granted Sep 08, 2026
Patent 12733412
METAL FERROELECTRIC INSULATOR METAL STACK IN RRAM
3y 5m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
94%
With Interview (+2.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 740 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month