DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 4-6, 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 27, 29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 27 recites “a bit-line or bit-line pair of a memory section” twice, line 2 and line 12. It is not clear if they are being referred as a same bit line or two different bit lines.
Claim 29 recites “the logic computing circuits”, without sufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7, 11, 13, 19-22, 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (Patent 5732018), hereinafter as Choi.
Regarding claim 1, Choi teaches a memory device, comprising: a memory array, divided into a plurality of memory sections, each memory section comprising a plurality of memory cells (Fig 4); a plurality of data transfer circuits (Fig 4, circuit 16 and 17), each data transfer circuit being disposed between two memory sections;
wherein a data movement occurring from all or a selected set of bit-lines or bit-line pairs between any two adjacent memory sections of the memory array is performed, data signals of all or the selected set of bit-lines or bit-line pairs of two adjacent memory sections are sensed, latched, buffered (Fig 6a, sensing, latching/buffering) and repeated during the data movement by a data transfer circuit disposed between two adjacent memory sections, and the data movement is sequentially performed between two memory sections to facilitate the transfer of data signals to any memory section of the memory array without the need for global or trans-multiple-section data lines (Fig. 4, col 6 line 46-58, it is obvious to a person with ordinary skill in the art that data stored in cells attached to a BL need to be moved sequentially, e.g. Gohain 20240220126).
Regarding claim 2, Choi teaches each data transfer circuit comprises a plurality of first-type data transfer circuits, and each first-type data transfer circuits comprises: a first-type sensing buffer circuit comprising a bit-line sense amplifier (BLSA), coupled to a bit-line or bit-line pair of a memory section and a bit-line or a bit-line pair of an adjacent memory section (Fig 6a); wherein data signals on the bit-line or bit-line pair in the memory section are sensed, latched, and buffered by the first-type sensing buffer circuit, the latched data signals are driven and transferred to the bit-line or bit-line pair in the adjacent memory section by the first-type sensing buffer circuit, and the data signals are sequentially transferred across subsequent memory sections through
Regarding claim 7, Choi teaches each data transfer circuit comprises a plurality of fourth-type data transfer circuits, and each fourth-type data transfer circuit comprises: a second-type sensing buffer circuit, comprising: a BLSA, coupled to a bit-line or bit-line pair of a memory section and a bit-line or a bit-line pair of an adjacent memory section; and a data interface, other than the bit-line or bit-line pair, coupled to the BLSA; wherein data signals on the bit-line or bit-line pair in the memory section are sensed, latched, and buffered by the BLSA, the latched data signals are driven and transferred to the bit-line or bit-line pair in the adjacent memory section or the data interface (Fig 6a, 55), other than bit-lines or bit-line pairs in memory sections, by the BLSA, and the data signals are sequentially transferred across subsequent memory sections through other data transfer circuits which are coupled to two adjacent memory sections (Fig 4, duplication of essential working parts (number of data transfer circuits) is not patentable feature, St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
Regarding claim 11, Choi teaches an interface transfer circuit, wherein the interface transfer circuit comprises a plurality of first-type interface transfer circuit, and each first-type interface transfer circuit comprises: a third-type sensing buffer circuit, comprising a BLSA, and coupled to a bit-line or bit-line pair of a memory section; wherein data signals on the bit-line or bit-line pair in the memory section are sensed, latched, and buffered by the BLSA (Fig 6a).
Regarding claim 13, Choi teaches an interface transfer circuit, wherein the interface transfer circuit comprises a plurality of third-type interface transfer circuit, and each third-type interface transfer circuit comprises: a fourth-type sensing buffer circuit, comprising: a BLSA, coupled to a bit-line or bit-line pair of one of the pluralities of memory sections; and a data interface, coupled to the BLSA; wherein data signals on the bit-line or bit-line pair in the memory section are sensed, latched, and buffered by the BLSA, the latched data signals are driven and transferred to the data interface by the BLSA (Fig 6a).
Regarding claim 19, Choi teaches an operation method for data movement within memory sections and through external interfaces of a memory device, each memory device comprising a memory array divided into a plurality of memory sections, each memory section comprising a plurality of memory cells (Fig 4), the operation method comprising:
performing a data movement occurring from all or a selected set of bit-lines or bit-line pairs between any two adjacent memory sections of the memory array; sensing, latching, buffering, and repeating data signals of all or the selected set of bit-lines or bit-line pairs of one of two adjacent memory sections during the data movement to the adjacent memory section by a data transfer circuit disposed between two adjacent memory sections; and sequentially performing the data movement between two memory sections to facilitate the transfer of data signals to the adjacent memory section, and then, to any memory section of the memory array without the need for global or trans-multiple-section data lines (col 6 line 46-58 and Fig 6a, also it is obvious to a person with ordinary skill in the art that data stored in cells attached to a BL need to be moved sequentially).
Regarding claim 20, Choi teaches connecting a bit-line or bit-line pair of a memory section to a bit-line or a bit-line pair of an adjacent memory section by a data transfer circuit; sensing, latching, and buffering the data signals on the bit-line or bit-line pair of the memory section by the data transfer circuit; transferring the data signals to the bit-line or bit-line pair in the adjacent memory section or a data interface through the data transfer circuit; and sequentially transferring the data signals across subsequent memory sections through other data transfer circuits which are coupled to two adjacent memory sections (Fig 6a).
Regarding claim 21, the examiner takes note that it is well known in a field that a word line from a target section or any signal-pass-by section, wherein the word line is activated during the trans-section data movement to capture the data on the bit-lines or bit-line pairs of the section and store it in the memory cells of the section coupled to the activated word line.
Regarding claim 22, Choi teaches selecting a set of bit-lines or bit-line pairs of a memory section from a first number of bit-lines or bit-line pairs of the memory section, and connecting the selected set of bit-lines or bit-line pairs of the memory section to the data transfer circuit; sensing, latching, and buffering the data signals on the selected set of bit-lines or bit-line pairs of the memory section; and transferring the data signals to the selected set of bit-lines or bit-line pairs in the adjacent memory section or a data interface, other than the bit-line or bit-line pair, through the data transfer circuit or transferring data signals directly or multiplexed from an external device or other data output ports of this memory device to the data transfer circuit from the data interface, other than the bit-line or bit-line pair (col 6, line 46-58).
Regarding claim 30, Choi teaches all or part of variant types of data transfer circuits, coupled to the bit-line or bit-line pairs in the memory section, interface transfer circuits, and data interfaces among the multiple-section memory array, are configured to be operated in serial or parallel (Fig 6a-b).
Claim(s) 3, 8-10, 12, 14-18, 23-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi, in view of Kolar et al. (Patent 12057159), hereinafter as Kolar.
Regarding claim 3, Choi teaches a plurality of second-type data transfer circuits, and each second-type data transfer circuit comprises: a first-type sensing buffer circuit, comprising a BLSA; wherein the data signals on the selected set of bit-lines or bit-line pairs in the memory section are sensed, latched and buffered by the first-type sensing buffer circuit, the latched data signals are driven and transferred to the selected set of bit-lines or bit-line pairs in the adjacent memory section by the first-type sensing buffer circuit, and the data signals are sequentially transferred across subsequent memory sections through other data transfer circuits which are coupled to two adjacent memory sections (col 6 line 46-58);
But not expressly multiplexer for the transfer circuits,
Kolar teaches a first multiplexer, coupled to a first number of bit-lines or bit-line pairs of a memory section and the first-type sensing buffer circuit, and configured to select a set of bit-lines or bit-line pairs of the memory section from the first number of bit-lines or bit-line pairs of the memory section, and connect the selected set of bit-lines or bit-line pairs of the memory section to the first-type sensing buffer circuit; and a second multiplexer, coupled to a second number of bit-lines or bit-line pairs of an adjacent memory section and the first-type sensing buffer circuit, and configured to select a set of bit-lines or bit-line pairs of the adjacent memory section from the second number of bit-lines or bit-line pairs of the adjacent memory section, and connect the selected set of bit-lines or bit-line pairs of the adjacent memory section to the first-type sensing buffer circuit (Fig 1).
Since Kolar and Choi are both from the same field of semiconductor memory device, the purpose disclosed by Kolar would have been recognized in the pertinent art of Choi.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use a multiplexer as in Kolar into the device of Choi for the purpose of reducing number of sense amplifiers in the memory device.
Regarding claim 8, the examiner takes note that it is well known in the field that a computing logic circuit, directly or selectively/multiplexed coupled to the data interface; wherein the data signals are directly or selectively/multiplexed driven and transferred to the computing logic circuit by the data interface.
Regarding claim 9, Choi teaches a BLSA; coupled to a bit-line or bit-line pair of a memory section; and a data interface, other than bit-lines or bit-line pairs in memory sections, coupled to the BLSA; wherein the data signals on the selected set of bit-lines or bit-line pairs in the memory section are sensed, latched and buffered by the BLSA through connection operations of the first multiplexer, the latched data signals are driven and transferred to the selected set of bit-lines or bit-line pairs in the adjacent memory section or the data interface by the BLSA, and the data signals are sequentially transferred across subsequent memory sections through other data transfer circuits which are coupled to two adjacent memory sections (Fig 6a-b, and col 4).
Kolar teaches 1st and 2nd multiplexers for circuit between memory blocks (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Regarding claim 12, Choi teaches an interface transfer circuit, wherein the interface transfer circuit comprises a plurality of second-type interface transfer circuit, and each second-type interface transfer circuit comprises: a third-type sensing buffer circuit, comprising a BLSA; wherein the data signals on the selected set of bit-lines or bit-line pairs in the memory section are sensed, latched, and buffered by the third-type sensing buffer circuit through connection operations of the multiplexer (Fig 6a);
Kolar teaches a multiplexer, coupled to a first number of bit-lines or bit-line pairs of a memory section and the BLSA, and configured to select a set of bit-lines or bit-line pairs of the memory section from the first number of bit-lines or bit-line pairs of the memory section, and connect the selected set of bit-lines or bit-line pairs of the memory section to the BLSA (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Regarding claim 10/14/16/18, argument used in rejection of claim 8 applies.
Regarding claim 15, Choi teaches an interface transfer circuit, wherein the interface transfer circuit comprises a plurality of fourth-type interface transfer circuits, and each fourth-type interface transfer circuit comprises: a fourth-type sensing buffer circuit, comprising: a BLSA; and a data interface, coupled to the BLSA; wherein the data signals on the selected set of bit-lines or bit-line pairs in the memory section are sensed, latched, and buffered by the BLSA through connection operations of the multiplexer, the latched data signals are driven and transferred to the data interface by the BLSA (Fig 6a),
Kolar teaches a multiplexer, coupled to a first number of bit-lines or bit-line pairs of a memory section and the BLSA, and configured to select a set of bit-lines or bit-line pairs of the memory section from the first number of bit-lines or bit-line pairs of the memory section, and connect the selected set of bit-lines or bit-line pairs of the memory section to the BLSA (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Regarding claim 17, Choi teaches an interface transfer circuit, wherein the interface transfer circuit comprises a plurality of fifth-type interface transfer circuit, and each fifth-type interface transfer circuit comprises: a plurality of first-type sensing buffer circuits, comprising: a plurality of BLSAs, and each BLSA is coupled to a bit-line or bit-line pair of a memory section; a multiplexer, coupled to the plurality of BLSAs, and configured to select a set of BLSAs from the plurality of BLSAs; and a data interface, coupled to the multiplexer; wherein the multiplexer is configured to connect the selected set of BLSAs to the data interface, and the data signals on bit-lines or bit-line pairs coupled to the selected set of BLSAs in the memory section are sensed, latched, and buffered by the selected set of BLSAs, the latched data signals are driven and transferred to the data interface by the selected set of BLSAs through connection operations of the multiplexer (Fig 6a, column selector 52t is a multiplexer to output circuit 55).
Kolar teaches multiplexers (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Regarding claim 23, Choi teaches selecting a set of first BLSAs from a plurality of first BLSAs of a first first-type sensing buffer circuit of the data transfer circuit coupled to bit-lines or bit-line pairs of a memory section, and connecting the selected set of first BLSAs to a second multiplexer by a first multiplexer; selecting a set of second BLSAs from a plurality of second BLSAs of a second first-type sensing buffer circuit of the data transfer circuit coupled to bit-lines or bit-line pairs of an adjacent memory section, and connecting to the selected set of second BLSAs by the second multiplexer; sensing, latching, and buffering the data signals on bit-lines or bit-line pairs coupled to the selected set of first BLSAs in the memory section by the selected set of first BLSAs; transferring the data signals to the selected set of second BLSAs or a data interface by the selected set of first BLSAs through connection operations of the first multiplexer and the second multiplexer; transferring the data signals to bit-lines or bit-line pairs coupled to the selected set of second BLSAs in the adjacent memory section; and sequentially transferring the data signals across subsequent memory sections through other data transfer circuits which are coupled to two adjacent memory sections (Fig 6a-b and col 6).
Kolar teaches multiplexers (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Regarding claim 24, Choi teaches connecting a bit-line or bit-line pair of a memory section to a data interface or a computing logic circuit by an interface transfer circuit; sensing, latching, and buffering the data signals on the bit-line or bit-line pair of the memory section by the interface transfer circuit; and transferring data signals directly or multiplexed from an external device or other data output ports of the memory device to the data transfer circuit from the data interface, then to the bit-line or bit-line pair; or transferring the data signals on the bit-line or bit-line pair of the memory section to the data interface or the computing logic circuit by the interface transfer circuit (col 4, and the argument used in rejection of claim 8 applies) .
Regarding claim 25, Choi teaches selecting a set of bit-lines or bit-line pairs of a memory section from a first number of bit-lines or bit-line pairs of the memory section by a multiplexer of an interface transfer circuit; connecting the selected set of bit-lines or bit-line pairs of the memory section to a data interface or a computing logic circuit by the multiplexer; sensing, latching, and buffering the data signals on the selected set of bit-lines or bit-line pairs of the memory section by the interface transfer circuit; and transferring data signals directly or multiplexed from an external device or other data output ports of the memory device to the data transfer circuit from the data interface, then to the selected bit-lines or bit-line pairs; or transferring the data signals on the selected bit-lines or bit-line pairs of the memory section to the data interface or the computing logic circuit through the interface transfer circuit (Fig 4, Fig 6a, col 4).
Kolar teaches multiplexers (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Regarding claim 26, Choi teaches selecting a set of BLSAs from a plurality of BLSAs of a first-type sensing buffer circuit of an interface transfer circuit coupled to bit-lines or bit-line pairs of a memory section; sensing, latching, and buffering the data signals on bit-lines or bit-line pairs coupled to the selected set of BLSAs in the memory section by the selected set of BLSAs of first-type sensing buffer circuit; and transferring data signals directly or multiplexed from an external device or other data output ports of the memory device to the data transfer circuit from the data interface, then to the selected bit-lines or bit-line pairs; or transferring the data signals to the data interface or the computing logic circuit by the selected set of BLSAs (Fig 4, 6a, and col 4).
Kolar teaches connecting multiplexers (Fig 1).
The reason for combining the references used in rejection of claim 3 applies.
Conclusion
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/MIN HUANG/ Primary Examiner, Art Unit 2827