DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant has amended independent claim 1 and persuasively argued that the amended limitation is the same limitation of cancelled and previously objected to claim 6. Regarding independent claims 7 & 11, there are neither amendments made or arguments provided. Because independent claims 7 & 11 have not been amended and no arguments have been made addressing the 103 rejections, Examiner maintains the previous 103 rejections to independent claims 7 & 11 and all subsequent dependent claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jamaludin et al (Jamaludin, Wan Shahmisufi Wan, et al. "Cost-effective microcontroller-based hardware-in-the-loop test equipment for testing vehicle instrument panel." 2017 IEEE 4th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA). IEEE, 2017.) in view of Weiss et al (Weiss, Kevin, et al. "PHiLIP on the HiL: Automated multi-platform OS testing with external reference devices." ACM Transactions on Embedded Computing Systems (TECS) 20.5s (2021): 1-26.).
Regarding Independent claim 7, Jamaludin teaches:
A method of testing hardware devices using an integrated Hardware-In-the-Loop (HIL) system, the method comprising:
receiving, by a microcontroller unit of the integrated HIL system (See Examiner amended Fig. 2 below wherein a microcontroller is mapped and indicated. See Section II.), test parameters required for testing a Device Under Test (DUT) (See Fig. 2 Element DUT. See Section II.) through a front panel of the integrated HIL system (See Examiner amended Fig. 2 below wherein the input is shown and highlighted.);
decoding, by the microcontroller unit (See Examiner amended Fig. 2 below wherein there is a data path depicted from the PC through the HiL to the DUT with data transitions and transformations. See Section II.), the test parameters for determining a test functionality to be performed on the DUT (See Examiner amended Fig. 2 below. See Title, Abstract and body of paper wherein it discloses a test setup to determine the functionality of an instrument panel.);
performing, by the microcontroller unit, the test functionality on the DUT (See Examiner amended Fig. 2 below. See Title, Abstract and body of paper wherein it discloses a test setup to determine the functionality of an instrument panel.) and generate a test outcome corresponding to the test functionality (See Examiner amended Fig. 2 below. See Table 2.); and
output, by the microcontroller unit (See Examiner amended Fig. 2 below. See Table 2.), the test outcome on a display interface of the front panel (See Examiner amended Fig. 2 below. See title, Abstract and body of the paper. See PC display in figure 2. See Section II & V. See Table 2.).
PNG
media_image1.png
726
1306
media_image1.png
Greyscale
PNG
media_image2.png
220
338
media_image2.png
Greyscale
Jamaludin does not explicitly teach:
using one of a plurality of hardware abstraction layers, comprised in an automated test application interface of the microcontroller unit.
Weiss teaches:
using one of a plurality of hardware abstraction layers, comprised in an automated test application interface of the microcontroller unit (Title; Abstract; Introduction page 91:2 Step 1; Table 3 & elsewhere.).
PNG
media_image3.png
152
580
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Weiss to the teachings of Jamaludin such that one would use one of a plurality of hardware abstraction layers, comprised in an automated test application interface of the microcontroller unit because developers “of IoT systems can easily access various hardware features and specific functions when relying on the hardware abstraction layer (HAL) and APIs of an OS for embedded devices. See Section 2.1 paragraph 1 lines 1-2 on page 91:4 of Weiss.
Regarding claim 8, Jamaludin & Weiss teach all elements of claim 7, upon which this claim depends.
Jamaludin teaches configuring a plurality of test modules in the microcontroller unit, wherein the plurality of test modules includes at least one of a DUT-specific evaluation board (See Examiner amended Fig. 2 below Element signal conditioning circuit.), an ethernet module, a Controller Area Network (CAN) module, an Analog-to-Digital Converter (ADC) module, a Digital-to-Analog Converter (DAC) module, a Pulse Width Modulation (PWM) module, a resistor bank module, Local Interconnect Network (LIN) module, a relay module and a digital I/O module in the, wherein the plurality of hardware abstraction layers of the automated test application interface is configured to correspond to the plurality of test modules.
Regarding claim 9, Jamaludin & Weiss teach all elements of claim 8, upon which this claim depends.
Jamaludin does not explicitly teach the plurality of hardware abstraction layers communicates with corresponding plurality of test modules through an abstract interface configured in the automated test application interface.
Weiss teaches the plurality of hardware abstraction layers communicates with corresponding plurality of test modules through an abstract interface configured in the automated test application interface (Section 2.1 paragraph 1; Section 3.1 paragraph 1; & Table 3.).
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Weiss to the teachings of Jamaludin such that the plurality of hardware abstraction layers communicates with corresponding plurality of test modules through an abstract interface configured in the automated test application interface because developers “of IoT systems can easily access various hardware features and specific functions when relying on the hardware abstraction layer (HAL) and APIs of an OS for embedded devices. See Section 2.1 paragraph 1 lines 1-2 on page 91:4 of Weiss.
Regarding claim 10, Jamaludin & Weiss teach all elements of claim 7, upon which this claim depends.
Jamaludin does not explicitly teach the test outcome comprises a plurality of log files generated while performing the test functionality and an indication of completion of testing of the DUT.
Weiss teaches the test outcome comprises a plurality of log files generated while performing the test functionality and an indication of completion of testing of the DUT (Section 4.1 step 8 of list on page 91:6 & Section 6.2 paragraph 1 second to last line.).
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Weiss to the teachings of Jamaludin such that the test outcome comprises a plurality of log files generated while performing the test functionality and an indication of completion of testing of the DUT because this is how most systems work. A program runs and directs measurements and outputs of sensors to be logged into files for analysis either later or in real time.
Regarding Independent claim 11, Jamaludin teaches:
A non-transitory computer-readable medium storing computer-executable instructions for testing hardware devices using an integrated Hardware-In-the-Loop (HIL) system, comprising:
receiving test parameters required for testing a Device Under Test (DUT) through a front panel of the integrated HIL system (See Examiner amended Fig. 2 below wherein an Input is depicted and highlighted.);
decoding the test parameters for determining a test functionality to be performed on the DUT (See Examiner amended Fig. 2 below wherein there is a data path depicted from the PC through the HiL to the DUT with data transitions and transformations. See Section II.);
performing the test functionality on the DUT (See Examiner amended Fig. 2 below. See Title, Abstract and body of paper wherein it discloses a test setup to determine the functionality of an instrument panel.) and generate a test outcome corresponding to the test functionality (See Examiner amended Fig. 2 below. See Table 2 and Sections II & V.); and
outputting the test outcome on a display interface of the front panel (See Examiner amended Fig. 2 below. See title, Abstract and body of the paper. See PC display in figure 2. See Section II & V. See Table 2.).
PNG
media_image1.png
726
1306
media_image1.png
Greyscale
PNG
media_image2.png
220
338
media_image2.png
Greyscale
Jamaludin does not explicitly teach:
using one of a plurality of hardware abstraction layers, comprised in an automated test application interface of the microcontroller unit.
Weiss teaches:
using one of a plurality of hardware abstraction layers, comprised in an automated test application interface of the microcontroller unit (Title; Abstract; Introduction page 91:2 Step 1; Table 3 & elsewhere.).
PNG
media_image3.png
152
580
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Weiss to the teachings of Jamaludin such that one would use one of a plurality of hardware abstraction layers, comprised in an automated test application interface of the microcontroller unit because developers “of IoT systems can easily access various hardware features and specific functions when relying on the hardware abstraction layer (HAL) and APIs of an OS for embedded devices. See Section 2.1 paragraph 1 lines 1-2 on page 91:4 of Weiss.
Regarding claim 12, Jamaludin & Weiss teach all elements of claim 11, upon which this claim depends.
Jamaludin teaches the computer-executable instructions are further configured for configuring a plurality of test modules in the microcontroller unit, wherein the plurality of test modules includes at least one of a DUT-specific evaluation board (See Examiner amended Fig. 2 below Element signal conditioning circuit.), an ethernet module, a Controller Area Network (CAN) module, an Analog-to-Digital Converter (ADC) module, a Digital-to-Analog Converter (DAC) module, a Pulse Width Modulation (PWM) module, a resistor bank module, Local Interconnect Network (LIN) module, a relay module and a digital I/O module in the, wherein the plurality of hardware abstraction layers of the automated test application interface is configured to correspond to the plurality of test modules.
Regarding claim 13, Jamaludin & Weiss teach all elements of claim 12, upon which this claim depends.
Jamaludin does not explicitly teach the plurality of hardware abstraction layers communicates with corresponding plurality of test modules through an abstract interface configured in the automated test application interface.
Weiss teaches the plurality of hardware abstraction layers communicates with corresponding plurality of test modules through an abstract interface configured in the automated test application interface (Section 2.1 paragraph 1; Section 3.1 paragraph 1; & Table 3.).
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Weiss to the teachings of Jamaludin such that the plurality of hardware abstraction layers communicates with corresponding plurality of test modules through an abstract interface configured in the automated test application interface because developers “of IoT systems can easily access various hardware features and specific functions when relying on the hardware abstraction layer (HAL) and APIs of an OS for embedded devices. See Section 2.1 paragraph 1 lines 1-2 on page 91:4 of Weiss.
Regarding claim 14, Jamaludin & Weiss teach all elements of claim 11, upon which this claim depends.
Jamaludin teaches the test outcome comprises a plurality of log files generated while performing the test functionality and an indication of completion of testing of the DUT.
Weiss teaches the test outcome comprises a plurality of log files generated while performing the test functionality and an indication of completion of testing of the DUT (Section 4.1 step 8 of list on page 91:6 & Section 6.2 paragraph 1 second to last line.).
It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Weiss to the teachings of Jamaludin such that the test outcome comprises a plurality of log files generated while performing the test functionality and an indication of completion of testing of the DUT because this is how most systems work. A program runs and directs measurements and outputs of sensors to be logged into files for analysis either later or in real time.
Allowable Subject Matter
Claims 1-5 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art does not anticipate alone or combine in an obvious manner to teach the invention claimed by Applicant.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached on 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858
Prosecution Insights