DETAILED ACTION
This correspondence is in response to the communications received 08/22/2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/22/2024 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 12-14, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 requires “the connection terminal in a central portion of the first semiconductor device in the first direction by the redistribution layer”. This limitation renders claim 2 indefinite as it is unclear the relationship between the central terminal, the central portion of the first semiconductor device, and the redistribution layer. For the purposes of examination, the limitation will be interpretated as “the connection terminal being in a central portion of the first semiconductor device in the first direction and by the redistribution layer, the redistribution layer extending in the first direction”.
Claim 12 recites the limitation “the decoupling capacitor”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the decoupling capacitor will be interpretated as “the at least one decoupling capacitor”.
Claim 13 recites the limitation “the decoupling capacitor”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the decoupling capacitor will be interpretated as “the at least one decoupling capacitor”.
Claim 14 recites the limitation “the decoupling capacitor”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the decoupling capacitor will be interpretated as “the at least one decoupling capacitor”.
Claim 16 requires “a wiring layer of the package substrate”. It is unclear this element is the same as the “wiring layer of the package substrate” required by claim 15. Claim 16 is therefore indefinite. For the purposes of examination, “a wiring layer of the package substrate” of claim 16 will be interpretated as “[[a]] the wiring layer of the package substrate”.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor package (1000), comprising:
a package substrate (100);
an interposer (200) on the package substrate (see Fig. 1B) and comprising a body layer (201) and a redistribution layer (an upper redistribution layer 210, a lower redistribution layer 220", [0034]);
a semiconductor-bridge (500) in the interposer and comprising a decoupling capacitor (520);
a first semiconductor device (300) on a central portion of a top surface of the interposer (see Fig. 1B); and
a second semiconductor device (400) on an outer portion of the top surface of the interposer and adjacent to the first semiconductor device (see Fig. 1B), wherein the decoupling capacitor is connected to the first semiconductor device by the redistribution layer (see Fig. 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-9, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ling et al. (US 20240071936 A1, filed 08/26/2022) in view of Jain et al. (US 11,133,256 B2, published 09/28/2021) in view of Cheah et al. (US 11,521,932 B2, published 12/06/2022).
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Regarding claim 1, Fig. 1 of Ling discloses a semiconductor package (“package structure 1”, [0013]), comprising:
a package substrate (“wiring substrate 10”, [0013]);
an interposer (“interposer substrate 12”, [0013]) on the package substrate (as seen in Fig. 1, 12 is on 10) and comprising a body layer (“substrate 120”, [0015]) and a redistribution layer (together “first redistribution circuit structure 125 and a second redistribution circuit structure 126”, [0015], form a split redistribution layer);
a semiconductor-bridge (“bridge device 121”, [0015], Ling does not disclose 121 as a semiconductor-bridge, however a secondary reference will be used to teach this limitation below) in the interposer (as seen in Fig. 1, 121 is in 12) and comprising a decoupling capacitor (Ling does not disclose 121 as comprising a decoupling capacitor, however a secondary reference will be used to teach this limitation below);
a first semiconductor device (“system-on-chip die 140”, [0030]) on a central portion of a top surface of the interposer (as seen in Fig. 1, 140 is on a central portion of 12); and
a second semiconductor device (“memory cubes 142”, [0030]) on an outer portion of the top surface of the interposer and adjacent to the first semiconductor device (as seen in Fig. 1, 142 is on an outer portion of the top surface of 12 and adjacent to 140).
Ling fails to disclose “a semiconductor-bridge … comprising a decoupling capacitor;
wherein the decoupling capacitor is connected to the first semiconductor device by the redistribution layer”.
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However, in a similar field of endeavor, Fig. 1 of Jain teaches a semiconductor-bridge (“The bridge 110 may be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (e.g., silicon or germanium)”, col. 4, lines 47-49) comprising a decoupling capacitor (“The bridge 110 may include one or more integral devices 112 … An integral device 112 may be a resistor or a capacitor”, col. 4, lines 54-60, where 110 of Jain is equivalent to 121 of Ling. While Jain does not disclose that 112 is a decoupling capacitor, a secondary reference will be used to teach this limitation below);
wherein the decoupling capacitor is connected to the first semiconductor device by the redistribution layer (“The bridge 110 may also include conductive pathways 115 through the insulating material that couple the integral devices 112 to the dies 114”, col. 5, lines 26-29, where 114 of Jain is equivalent to 140 and 142 of Ling, further as seen in Fig. 1 of Ling, all connections from 121 to 140 and 142 pass through 126, thus after combination of Ling and Jain, 112 of Jain will be connected to 140 of Ling via 126 of Ling).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a semiconductor-bridge comprising a decoupling capacitor;
wherein the decoupling capacitor is connected to the first semiconductor device by the redistribution layer” as taught by Jain in the system of Ling for the purpose of providing a material for the bridge and providing additional functionality to the bridge device.
Ling in combination with Jain fails to disclose “a semiconductor-bridge … comprising a decoupling capacitor”.
However, in a similar field of endeavor, Figs. 1A-1K of Cheah teaches a semiconductor-bridge … comprising a decoupling capacitor (“Where the passive device 112 is a decoupling capacitor 112, improved power integrity is enabled by shortened loop inductance between the capacitor 112 and the IC die that it is servicing, which facilitates uninterrupted current flow that is useful to direct-current (DC) load-line performance and consequently the computing performance of the IC die and any computing system of which it is a part”, col. 5, lines 12-18, thus 112 of Jain can be a decoupling capacitor).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a semiconductor-bridge … comprising a decoupling capacitor” as taught by Cheah in the system of Ling in combination with Jain for the purpose of facilitating computing performance of the package device.
Regarding claim 2, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 1, Fig. 1 of Ling further discloses wherein the second semiconductor device is adjacent to a side surface of the first semiconductor device in a first direction (as seen in Fig. 1, 142 is adjacent to a side surface of 140 in a horizontal direction),
the semiconductor-bridge overlaps with
at least a portion of the first semiconductor device (as seen in Fig. 1, 121 overlaps with at least a portion of 140), and
at least a portion of the second semiconductor device (as seen in Fig. 1, 121 overlaps with at least a portion of 142), and
the decoupling capacitor is connected to a connection terminal (as seen in Fig. 1, all connections between 121 and 140 or 142 are through “conductive terminals 128”, [0025], thus after combination with Jain, 112 of Jain will be connected to 128 of Ling), the connection terminal in a central portion of the first semiconductor device in the first direction (as seen in Fig. 1, a portion of 128 is in a central portion of 140 in the horizontal direction) by the redistribution layer (as seen in Fig. 1, 128 is by 126), the redistribution layer extending in the first direction (as seen in Fig. 1, 125 and 126 extend in the horizontal direction).
Regarding claim 3, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 1, Fig. 1 of Ling further discloses wherein the redistribution layer comprises an upper redistribution layer (as seen in Fig. 1, 126 is an upper redistribution layer) and a lower redistribution layer (as seen in Fig. 1, 125 is a lower redistribution layer), the upper redistribution layer being on a top surface of the body layer (as seen in Fig. 1, 126 is on a top surface of 120) and the lower redistribution layer being on a bottom surface of the body layer (as seen in Fig. 1, 125 is on a bottom surface of 120),
the semiconductor-bridge is in the body layer (as seen in Fig. 1, 121 is in 120), and
the decoupling capacitor is connected to the first semiconductor device by the upper redistribution layer (as seen in Fig. 1, 121 is connected to 140 via 126, thus after combination with Jain and Cheah, 112 of Jain will be connected to 140 of Ling via 126 of Ling).
Regarding claim 6, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 1.
Ling in combination with Jain and Cheah do not specifically disclose “wherein the first semiconductor device includes a logic chip, and the second semiconductor device includes at least one of a memory chip or a memory package”.
However, in a similar field of endeavor, Ling teaches wherein the first semiconductor device includes a logic chip, and the second semiconductor device includes at least one of a memory chip or a memory package (“the plurality of semiconductor dies 14 include logic dies, system-on-chip (SoC) dies, high bandwidth memory (HBM) cubes each having stacked memory dies or other suitable semiconductor dies”, [0029], thus 140 and 142, which together form 14, can respectively be a logic die and an HBM die).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first semiconductor device includes a logic chip, and the second semiconductor device includes at least one of a memory chip or a memory package” as taught by Ling in the system of Ling in combination with Jain and Cheah for the purpose of tailoring the device functionality for a given application.
Regarding claim 7, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 6, Ling further discloses wherein the second semiconductor device includes a high bandwidth memory (HBM) package (as discussed previously, 142 can be an HBM die).
Regarding claim 8, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 1, Fig. 1 of Jain further discloses wherein the semiconductor-bridge includes a silicon (Si)-bridge (as discussed previously, 110 of Jain, equivalent to 121 of Ling may be silicon).
Fig. 1 of Ling further discloses the first semiconductor device is connected to the second semiconductor device by internal wiring of the semiconductor-bridge (as seen in Fig. 1, 140 is connected to 142 by internal wiring of 121, further “The bridge device 121 is configured for electrical connection (see the dash lines) between adjacent semiconductor dies 14 and/or between the semiconductor dies 14 and the wiring substrate 10”, [0019]).
Regarding claim 9, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 1, Fig. 1 of Jain further discloses wherein the interposer does not comprise a separate capacitor therein (Jain states “integrated passive device 124 may include resistors, capacitors, inductors or combination thereof, but not limited thereto”, [0022], therefore while a separate capacitor may be included in 12, resistors or inductors may instead be used).
Claim 15 has been interpretated in two ways to better facilitate mapping of the dependent claims. Each dependent claim will identify which interpretation of claim 15 is being relied upon.
Interpretation One:
Regarding interpretation one of claim 15, Fig. 1 of Ling discloses a semiconductor package (“package structure 1”, [0013]), comprising:
a package substrate (“interposer substrate 12”, [0013]);
a silicon (Si)-bridge (“bridge device 121”, [0015], Ling does not disclose 121 as a Si-bridge, however a secondary reference will be used to teach this limitation below) in or on the package substrate (as seen in Fig. 1, 121 is in 12) and comprising a decoupling capacitor (Ling does not disclose a decoupling capacitor, however a secondary reference will be used to teach this limitation below);
a logic chip (“system-on-chip die 140”, [0030], Ling does not specifically disclose that 140 is a logic chip, however a secondary reference will be used to teach this limitation below) on a central portion of the package substrate (as seen in Fig. 1, 140 is on a central portion of 12); and
a high bandwidth memory (HBM) package (“memory cubes 142”, [0030], Ling does not specifically disclose that 142 is a HBM, however, a secondary reference will be used to teach this limitation below) on an outer portion of the package substrate and adjacent to the logic chip in a first direction (as seen in Fig. 1, 142 is on an outer portion of 12 and adjacent to 142 in the horizontal direction).
Ling fails to disclose “a silicon (Si)-bridge … comprising a decoupling capacitor;
a logic chip; and
a high bandwidth memory (HBM) package,
wherein the decoupling capacitor is connected to the logic chip by a wiring layer of the package substrate or by a redistribution layer on the package substrate.”
However, in a similar field of endeavor, Fig. 1 of Jain teaches a silicon (Si)-bridge (“The bridge 110 may be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (e.g., silicon or germanium)”, col. 4, lines 47-49, thus 110 may be a Si-Bridge) … comprising a decoupling capacitor (“The bridge 110 may include one or more integral devices 112 … An integral device 112 may be a resistor or a capacitor”, col. 4, lines 54-60, where 110 of Jain is equivalent to 121 of Ling. While Jain does not disclose that 112 is a decoupling capacitor, a secondary reference will be used to teach this limitation below),
wherein the decoupling capacitor is connected to the logic chip by a wiring layer of the package substrate or by a redistribution layer on the package substrate (“The bridge 110 may also include conductive pathways 115 through the insulating material that couple the integral devices 112 to the dies 114”, col. 5, lines 26-29, where 114 of Jain is equivalent to 140 and 142 of Ling, further as seen in Fig. 1 of Ling, all connections from 121 to 140 and 142 pass through “second redistribution circuit structure 126”, [0015], thus after combination of Ling and Jain, 112 of Jain will be connected to 140 of Ling via 126 of Ling, as a redistribution structure, 126 functions as a wiring layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a silicon (Si)-bridge … comprising a decoupling capacitor;
wherein the decoupling capacitor is connected to the logic chip by a wiring layer of the package substrate or by a redistribution layer on the package substrate” as taught by Jain in the system of Ling for the purpose of providing a material for the bridge and providing additional functionality to the bridge device.
Ling in combination with Jain fails to disclose “a silicon (Si)-bridge … comprising a decoupling capacitor;
a logic chip; and
a high bandwidth memory (HBM) package”.
However, in a similar field of endeavor, Figs. 1A-1K of Cheah teaches a Si-bridge … comprising a decoupling capacitor (“Where the passive device 112 is a decoupling capacitor 112, improved power integrity is enabled by shortened loop inductance between the capacitor 112 and the IC die that it is servicing, which facilitates uninterrupted current flow that is useful to direct-current (DC) load-line performance and consequently the computing performance of the IC die and any computing system of which it is a part”, col. 5, lines 12-18, thus 112 of Jain can be a decoupling capacitor).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a Si-bridge … comprising a decoupling capacitor” as taught by Cheah in the system of Ling in combination with Jain for the purpose of facilitating computing performance of the package device.
Ling in combination with Jain and Cheah do not specifically disclose “a logic chip; and
a high bandwidth memory (HBM) package”.
However, in a similar field of endeavor, Ling teaches a logic chip; and
a high bandwidth memory (HBM) package (“the plurality of semiconductor dies 14 include logic dies, system-on-chip (SoC) dies, high bandwidth memory (HBM) cubes each having stacked memory dies or other suitable semiconductor dies”, [0029], thus 140 and 142, which together form 14, can respectively be a logic die and an HBM die)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a logic chip; and
a high bandwidth memory (HBM) package” as taught by Ling in the system of Ling in combination with Jain and Cheah for the purpose of tailoring the device functionality for a given application.
Interpretation Two:
Regarding interpretation two of claim 15, Fig. 1 of Ling discloses a semiconductor package (“package structure 1”, [0013]), comprising:
a package substrate (“wiring substrate 10”, [0013]);
a silicon (Si)-bridge (“bridge device 121”, [0015], Ling does not disclose 121 as a Si-bridge, however a secondary reference will be used to teach this limitation below) in or on the package substrate (as seen in Fig. 1, 121 is on 10) and comprising a decoupling capacitor (Ling does not disclose a decoupling capacitor, however a secondary reference will be used to teach this limitation below);
a logic chip (“system-on-chip die 140”, [0030], Ling does not specifically disclose that 140 is a logic chip, however a secondary reference will be used to teach this limitation below) on a central portion of the package substrate (as seen in Fig. 1, 140 is on a central portion of 10); and
a high bandwidth memory (HBM) package (“memory cubes 142”, [0030], Ling does not specifically disclose that 142 is a HBM, however, a secondary reference will be used to teach this limitation below) on an outer portion of the package substrate and adjacent to the logic chip in a first direction (as seen in Fig. 1, 142 is on an outer portion of 10 and adjacent to 142 in the horizontal direction).
Ling fails to disclose “a silicon (Si)-bridge … comprising a decoupling capacitor;
a logic chip; and
a high bandwidth memory (HBM) package,
wherein the decoupling capacitor is connected to the logic chip by a wiring layer of the package substrate or by a redistribution layer on the package substrate.”
However, in a similar field of endeavor, Fig. 1 of Jain teaches a silicon (Si)-bridge (“The bridge 110 may be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (e.g., silicon or germanium)”, col. 4, lines 47-49, thus 110 may be a Si-Bridge) … comprising a decoupling capacitor (“The bridge 110 may include one or more integral devices 112 … An integral device 112 may be a resistor or a capacitor”, col. 4, lines 54-60, where 110 of Jain is equivalent to 121 of Ling. While Jain does not disclose that 112 is a decoupling capacitor, a secondary reference will be used to teach this limitation below),
wherein the decoupling capacitor is connected to the logic chip by a wiring layer of the package substrate or by a redistribution layer on the package substrate (“The bridge 110 may also include conductive pathways 115 through the insulating material that couple the integral devices 112 to the dies 114”, col. 5, lines 26-29, where 114 of Jain is equivalent to 140 and 142 of Ling, further as seen in Fig. 1 of Ling, all connections from 121 to 140 and 142 pass through “second redistribution circuit structure 126”, [0015], thus after combination of Ling and Jain, 112 of Jain will be connected to 140 of Ling via 126 of Ling).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a silicon (Si)-bridge … comprising a decoupling capacitor;
wherein the decoupling capacitor is connected to the logic chip by a wiring layer of the package substrate or by a redistribution layer on the package substrate” as taught by Jain in the system of Ling for the purpose of providing a material for the bridge and providing additional functionality to the bridge device.
Ling in combination with Jain fails to disclose “a silicon (Si)-bridge … comprising a decoupling capacitor;
a logic chip; and
a high bandwidth memory (HBM) package”.
However, in a similar field of endeavor, Figs. 1A-1K of Cheah teaches a Si-bridge … comprising a decoupling capacitor (“Where the passive device 112 is a decoupling capacitor 112, improved power integrity is enabled by shortened loop inductance between the capacitor 112 and the IC die that it is servicing, which facilitates uninterrupted current flow that is useful to direct-current (DC) load-line performance and consequently the computing performance of the IC die and any computing system of which it is a part”, col. 5, lines 12-18, thus 112 of Jain can be a decoupling capacitor).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a Si-bridge … comprising a decoupling capacitor” as taught by Cheah in the system of Ling in combination with Jain for the purpose of facilitating computing performance of the package device.
Ling in combination with Jain and Cheah do not specifically disclose “a logic chip; and
a high bandwidth memory (HBM) package”.
However, in a similar field of endeavor, Ling teaches a logic chip; and
a high bandwidth memory (HBM) package (“the plurality of semiconductor dies 14 include logic dies, system-on-chip (SoC) dies, high bandwidth memory (HBM) cubes each having stacked memory dies or other suitable semiconductor dies”, [0029], thus 140 and 142, which together form 14, can respectively be a logic die and an HBM die)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a logic chip; and
a high bandwidth memory (HBM) package” as taught by Ling in the system of Ling in combination with Jain and Cheah for the purpose of tailoring the device functionality for a given application.
Regarding claim 16, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of interpretation one of claim 15, Fig. 1 of Ling further discloses wherein the Si-bridge is in the package substrate and at least partially overlaps with a portion of the logic chip and with a portion of the HBM package (as seen in Fig. 1, 121 is in 12 and at least partially overlaps with a portion of 140 and 1 portion of 142), and
the decoupling capacitor is connected to a connection terminal by a wiring layer of the package substrate (as seen in Fig. 1, all connections between 121 and 140 or 142 are through “conductive terminals 128”, [0025], and 126, thus after combination with Jain, 112 of Jain will be connected to 128 of Ling by 126 of Ling), the connection terminal positioned in a central portion of the logic chip in the first direction (as seen in Fig. 1, a portion of 128 is in a central portion of 140 in the horizontal direction) and the wiring layer extending in the first direction (as seen in Fig. 1, 126 extends in the horizontal direction).
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ling et al. (US 20240071936 A1, filed 08/26/2022) in view of Mueller et al. (US 20250251446 A1, filled 04/08/2022) in view of Jain et al. (US 11,133,256 B2, published 09/28/2021) in view of Cheah et al. (US 11,521,932 B2, published 12/06/2022).
Regarding claim 10, Fig. 1 of Ling discloses a semiconductor package (“package structure 1”, [0013]), comprising:
a package substrate (“wiring substrate 10”, [0013]);
a panel level package (PLP) interposer (“interposer substrate 12”, [0013], Ling does not disclose that 12 is a PLP interposer, however a secondary reference will be used to teach this limitation below) on the package substrate (as seen in Fig. 1, 12 is on 10) and comprising a body layer (“substrate 120”, [0015]) and a redistribution layer (together “first redistribution circuit structure 125 and a second redistribution circuit structure 126”, [0015], form a split redistribution layer);
a silicon (Si)-bridge (“bridge device 121”, [0015], Ling does not disclose 121 as a Si-bridge, however a secondary reference will be used to teach this limitation below) in the PLP interposer (as seen in Fig. 1, 121 is in 12) and comprising at least one decoupling capacitor (Ling does not disclose a decoupling capacitor, however a secondary reference will be used to teach this limitation below);
a logic chip (“system-on-chip die 140”, [0030], Ling does not specifically disclose that 140 is a logic chip, however a secondary reference will be used to teach this limitation below) on a central portion of a top surface of the PLP interposer (as seen in Fig. 1, 140 is on a central portion of a top surface of 12); and
at least two high bandwidth memory (HBM) packages (“memory cubes 142”, [0030], and as seen in Fig. 1, there are two instances of 142. Ling does not specifically disclose that 142 is a HBM, however, a secondary reference will be used to teach this limitation below) on an outer portion of the top surface of the PLP interposer and adjacent to sides of the logic chip in a first direction (as seen in Fig. 1, 142 is on an outer portion of the top surface of 12 and adjacent to 142 in the horizontal direction),
Ling fails to disclose “a panel level package (PLP) interposer;
a silicon (Si)-bridge … comprising at least one decoupling capacitor;
a logic chip; and
at least two high bandwidth memory (HBM) packages
wherein the at least one decoupling capacitor is connected to the logic chip by the redistribution layer and a connection terminal, the redistribution layer extending in the first direction, and the connection terminal being in a central portion of the logic chip in the first direction.”
However, in a similar field of endeavor, Mueller teaches a panel level package (PLP) interposer (“2.5D integrated circuits” (2.5D ICs) and “3D integrated circuits” (3D ICs) combine multiple dies in a single integrated package. Here, two or more dies are placed on a packaging substrate, e.g. on a silicon interposer or a panel-level-packaging substrate. In 2.5D ICs, the dies are placed on the packaging substrate side-by-side, whereas in 3D ICs at least some of the dies are placed on top of each other. The assembly can be packaged as a single component, which reduced costs and size as compared to a conventional 2D circuit board assembly”, [0025], thus 12 of Ling can be substituted with a panel-level-packaging substrate).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a panel level package (PLP) interposer” as taught by Mueller in the system of Ling for the purpose of reducing interposer cost and size.
Ling in combination with Mueller fails to disclose “a silicon (Si)-bridge … comprising at least one decoupling capacitor;
a logic chip; and
at least two high bandwidth memory (HBM) packages
wherein the at least one decoupling capacitor is connected to the logic chip by the redistribution layer and a connection terminal, the redistribution layer extending in the first direction, and the connection terminal being in a central portion of the logic chip in the first direction.”
However, in a similar field of endeavor, Fig. 1 of Jain teaches a silicon (Si)-bridge (“The bridge 110 may be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (e.g., silicon or germanium)”, col. 4, lines 47-49, thus 110 may be a Si-Bridge) … comprising at least one decoupling capacitor (“The bridge 110 may include one or more integral devices 112 … An integral device 112 may be a resistor or a capacitor”, col. 4, lines 54-60, where 110 of Jain is equivalent to 121 of Ling. While Jain does not disclose that 112 is a decoupling capacitor, a secondary reference will be used to teach this limitation below),
wherein the at least one decoupling capacitor is connected to the logic chip by the redistribution layer and a connection terminal, the redistribution layer extending in the first direction, and the connection terminal being in a central portion of the logic chip in the first direction (“The bridge 110 may also include conductive pathways 115 through the insulating material that couple the integral devices 112 to the dies 114”, col. 5, lines 26-29, where 114 of Jain is equivalent to 140 and 142 of Ling, further as seen in Fig. 1 of Ling, all connections from 121 to 140 and 142 pass through “conductive terminals 128”, [0025], and 126, thus after combination of Ling and Jain, 112 of Jain will be connected to 140 of Ling via 126 and 128 of Ling).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a silicon (Si)-bridge … comprising at least one decoupling capacitor;
wherein the at least one decoupling capacitor is connected to the logic chip by the redistribution layer and a connection terminal, the redistribution layer extending in the first direction, and the connection terminal being in a central portion of the logic chip in the first direction” as taught by Jain in the system of Ling in combination with Mueller for the purpose of providing a material for the bridge and providing additional functionality to the bridge device.
Ling in combination with Mueller and Jain fails to disclose “a silicon (Si)-bridge … comprising at least one decoupling capacitor;
a logic chip; and
at least two high bandwidth memory (HBM) packages”.
However, in a similar field of endeavor, Figs. 1A-1K of Cheah teaches a Si-bridge … comprising at least one decoupling capacitor (“Where the passive device 112 is a decoupling capacitor 112, improved power integrity is enabled by shortened loop inductance between the capacitor 112 and the IC die that it is servicing, which facilitates uninterrupted current flow that is useful to direct-current (DC) load-line performance and consequently the computing performance of the IC die and any computing system of which it is a part”, col. 5, lines 12-18, thus 112 of Jain can be decoupling capacitors).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a Si-bridge … comprising at least one decoupling capacitor” as taught by Cheah in the system of Ling in combination with Mueller and Jain for the purpose of facilitating computing performance of the package device.
Ling in combination with Mueller, Jain, and Cheah fails to disclose “a logic chip; and
at least two high bandwidth memory (HBM) packages.”
However, in a similar field of endeavor, Ling teaches a logic chip; and
at least two high bandwidth memory (HBM) packages (“the plurality of semiconductor dies 14 include logic dies, system-on-chip (SoC) dies, high bandwidth memory (HBM) cubes each having stacked memory dies or other suitable semiconductor dies”, [0029], thus 140 and 142, which together form 14, can respectively be a logic die and two HBM dies)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a logic chip; and
at least two high bandwidth memory (HBM) packages” as taught by Ling in the system of Ling in combination with Mueller, Jain, and Cheah for the purpose of tailoring the device functionality for a given application.
Regarding claim 13, Fig. 1 of Ling in combination with Mueller, Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of claim 10, Fig. 1 of Ling further discloses wherein the redistribution layer comprises an upper redistribution layer (as seen in Fig. 1, 126 is an upper redistribution layer) and a lower redistribution layer (as seen in Fig. 1, 125 is a lower redistribution layer), the upper redistribution layer on a top surface of the body layer (as seen in Fig. 1, 126 is on a top surface of 120) and the lower redistribution layer on a bottom surface of the body layer (as seen in Fig. 1, 125 is on a bottom surface of 120),
the Si-bridge is in the body layer (as seen in Fig. 1, 121 is in 120), and
the decoupling capacitor is connected to the logic chip by the upper redistribution layer (as seen in Fig. 1, 121 is connected to 140 via 126, thus after combination with Jain and Cheah, 112 of Jain will be connected to 140 of Ling via 126 of Ling).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ling et al. (US 20240071936 A1, filed 08/26/2022) in view of Jain et al. (US 11,133,256 B2, published 09/28/2021) in view of Cheah et al. (US 11,521,932 B2, published 12/06/2022) in view of Mueller et al. (US 20250251446 A1, filled 04/08/2022).
Regarding claim 17, Fig. 1 of Ling in combination with Fig. 1 of Jain and Figs. 1A-1K of Cheah discloses the semiconductor package of interpretation two of claim 15, Fig. 1 of Ling further discloses further comprising a panel level package (PLP) interposer (“interposer substrate 12”, [0013], Ling does not disclose that 12 is a PLP interposer, however a secondary reference will be used to teach this limitation below) on the package substrate (as seen in Fig. 1, 12 is on 10) and comprising a body layer (“substrate 120”, [0015]) and a redistribution layer (together “first redistribution circuit structure 125 and a second redistribution circuit structure 126”, [0015], form a split redistribution layer),
wherein the logic chip and the HBM package are on a top surface of the PLP interposer (as seen in Fig. 1, 140 and 142 are on a top surface of 12),
the Si-bridge is in the PLP interposer (as seen in Fig. 1, 121 is in 12), and
the decoupling capacitor is connected to the logic chip by the redistribution layer (as seen in Fig. 1, all connections between 121 and 140 or 142 are through 126, thus after combination with Jain, 112 of Jain will be connected to 140 of Ling by 126 of Ling).
Ling in combination with Jain and Cheah fails to disclose “a panel level package (PLP) interposer”.
However, in a similar field of endeavor, Mueller teaches a panel level package (PLP) interposer (“2.5D integrated circuits” (2.5D ICs) and “3D integrated circuits” (3D ICs) combine multiple dies in a single integrated package. Here, two or more dies are placed on a packaging substrate, e.g. on a silicon interposer or a panel-level-packaging substrate. In 2.5D ICs, the dies are placed on the packaging substrate side-by-side, whereas in 3D ICs at least some of the dies are placed on top of each other. The assembly can be packaged as a single component, which reduced costs and size as compared to a conventional 2D circuit board assembly”, [0025], thus 12 of Ling can be substituted with a panel-level-packaging substrate).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a panel level package (PLP) interposer” as taught by Mueller in the system of Ling in combination with Jain and Cheah for the purpose of reducing interposer cost and size.
Regarding claim 18, Fig. 1 of Ling in combination with Fig. 1 of Jain, Figs. 1A-1K of Cheah, and Mueller disclose the semiconductor package of claim 17, Fig. 1 of Ling further discloses wherein the Si-bridge at least partially overlaps with a portion of the logic chip and with a portion of the HBM package (as seen in Fig. 1, 121 at least partially overlaps with a portion of 140 and with a portion of 142), and
the decoupling capacitor is connected to a connection terminal by the redistribution layer (as seen in Fig. 1, all connections between 121 and 140 or 142 are through “conductive terminals 128”, [0025], and 126, thus after combination with Jain, 112 of Jain will be connected to 128 of Ling by 126 of Ling), the connection terminal in a central portion of the logic chip in the first direction (as seen in Fig. 1, a portion of 128 is in a central portion of 140 in the horizontal direction) and the redistribution layer extending in the first direction (as seen in Fig. 1, 126 extends in the horizontal direction).
Allowable Subject Matter
Claims 4, 5, 11, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor package as recited in the claims of the instant application.
Regarding claim 4, the prior art of Ling et al. (US 20240071936 A1) in view of Jain et al. (US 11,133,256 B2) in view of Cheah et al. (US 11,521,932 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the connection arrangement of the decoupling capacitor, the first semiconductor device and the Cu post e.g. “the decoupling capacitor is connected to the first semiconductor device by the upper redistribution layer, the Cu post”.
Claim 5 is allowable by virtue of its dependence on claim 4.
Regarding claim 11, the prior art of Ling et al. (US 20240071936 A1) in view of Mueller et al. (US 20250251446 A1) in view of Jain et al. (US 11,133,256 B2) in view of Cheah et al. (US 11,521,932 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the connection pathway between the decoupling capacitors and the logic chip e.g. “the decoupling capacitor of the first Si-bridge is connected to the logic chip by a first redistribution line of the redistribution layer, the first redistribution line extending in the first direction from a position corresponding to the first Si-bridge to a position corresponding to a central portion of the logic chip, and
the decoupling capacitor of the second Si-bridge is connected to the logic chip by a second redistribution line of the redistribution layer, the second redistribution line extending in the first direction from a position corresponding to the second Si-bridge to a position corresponding to a central portion of the logic chip”.
Regarding claim 19, the prior art of Ling et al. (US 20240071936 A1) in view of Jain et al. (US 11,133,256 B2) in view of Cheah et al. (US 11,521,932 B2) in view of Mueller et al. (US 20250251446 A1) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the connection pathway between the decoupling capacitors and the logic chip e.g. “wherein a path connecting the decoupling capacitor to the logic chip and at least partially defined by the redistribution layer comprises a first path, and further comprises a second path, the second path connected in parallel to the first path and connecting the decoupling capacitor to the logic chip.”
Claim 20 is allowable by virtue of its dependence on claim 19.
Claims 12 and 14 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 12, the prior art of Ling et al. (US 20240071936 A1) in view of Mueller et al. (US 20250251446 A1) in view of Jain et al. (US 11,133,256 B2) in view of Cheah et al. (US 11,521,932 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the connection pathway between the decoupling capacitors and the logic chip e.g. “wherein a path connecting the decoupling capacitor to the logic chip and at least partially defined by the redistribution layer comprises a first path, and further comprises a second path connected in parallel to the first path and connecting the decoupling capacitor to the logic chip.”
Regarding claim 14, the prior art of Ling et al. (US 20240071936 A1) in view of Mueller et al. (US 20250251446 A1) in view of Jain et al. (US 11,133,256 B2) in view of Cheah et al. (US 11,521,932 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the arrangement of the connection between the at least one decoupling capacitor, the logic chip and the Cu post e.g. “the decoupling capacitor is connected to the logic chip by an additional path, the additional path at least partially defined by the upper redistribution layer, the Cu post, the lower redistribution layer, and a wiring layer of the package substrate.”
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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