Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 22, 2024, claim 1 is active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed August 22, 2024 have been considered.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 1 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12094532 [‘532]. This is a statutory double patenting rejection. See table below.
Present Application
Patent ‘532
1: A semiconductor memory device comprising: a first memory string including a first select transistor, a first memory cell and a second memory cell connected in series, each of the first memory cell and the second memory cell being configured to store data by one of a first state, a second state,... n-th state (n is a natural number);a second memory string including a second select transistor, a third memory cell and a fourth memory cell connected in series, each of the third memory cell and the fourth memory being configured to store data by one of the first state, the second state...the n-th state;a first bit line connected to one end of the first memory string; a second bit line connected to one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a first word line connected to gates of the first memory cells and the third memory cell, respectively; a second word line connected to gates of the second memory cell and the fourth memory cell, respectively; a first select line connected to gates of the first select transistor and the second select transistor; a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits; and a second data storage circuit electrically connected to the second bit line and including a plurality of second latch circuits, wherein when data is written to the first memory cell to change a state thereof from the first state to one of the first state, the second state,... the n state depending on a first data
after the first data is inputted to the first latch circuits in a first write operation, second data generated by the first data at the first latch circuits in a second write operation, and data is read from the first memory cell written by
the first write operation, the first data is restored by the read data and the second data, and the second write operation is executed to the first memory cell once again by the restored first data.
1. A semiconductor memory device comprising: a first memory string including a first select transistor, a first memory cell and a second memory cell connected in series, each of the first memory cell and the second memory cell being configured to store data by one of a first state, a second state, . . . n-th state (n is a natural number); a second memory string including a second select transistor, a third memory cell and a fourth memory cell connected in series, each of the third memory cell and the fourth memory being configured to store data by one of the first state, the second state . . . the n-th state; a first bit line connected to one end of the first memory string; a second bit line connected to one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a first word line connected to gates of the first memory cells and the third memory cell, respectively; a second word line connected to gates of the second memory cell and the fourth memory cell, respectively; a first select line connected to gates of the first select transistor and the second select transistor; a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits; and a second data storage circuit electrically connected to the
second bit line and including a plurality of second latch circuits, wherein when data is written to the first memory cell to change a state thereof from the first state to one of the first state, the second state, . . . the n state depending on a first data
after the first data is inputted to the first latch circuits in a first write operation, second data generated by the first data at the first latch
circuits in a second write operation, and data is read from the first memory cell written by
the first write operation, the first data is restored by the read data and the second data, and the second write operation is executed to the first memory cell once again by the restored first data.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 February 5, 2026