Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated May 11, 2026, claim 1-15 are active in
this application.
Claim Objection
The phrase “CLain 13” should be changed to –Claim 13--.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 8-14 of U.S. Patent No. 12094532 [‘532]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘532
1. A semiconductor memory device comprising: a first memory string including a first select transistor, a plurality of first memory cells connected in series and a second select transistor, each of the first memory cells being configured to store data by one of a first state, a second state,... n-th state (n is a natural number); a second memory string including a third select transistor, a plurality of second memory cells connected in series and a fourth select transistor, each of the second memory cells being configured to store data by one of the first state, the second state...the n-th state; a first bit line connected to one end of the first memory string and one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a plurality of word lines laminated in a vertical direction, each of the word lines connected to a gate of a corresponding one of the first memory cells and a gate of a corresponding one of the second memory cells; a first select line connected to a gate of the first select transistor; a second select line connected to a gate of the third select transistor; a third select line connected to a gate of the second select transistor and a gate of the fourth select transistor; and a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits, wherein when data is written to one of the first memory cells to change a state thereof from the first state to one of the first state, the second state,... the n state depending on a first data after the first data is inputted to the first latch circuits in a first write operation, a second data is generated by the first data at the first latch circuits in a second write operation, the first data is restored by data read from the one of the first memory cells, and the second data, and the second write operation is executed to the one of the first memory cells by the restored first data.
1. A semiconductor memory device comprising: a first memory string including a first select transistor, a first memory cell and a second memory cell connected in series, each of the first memory cell and the second memory cell being configured to store data by one of a first state, a second state, . . . n-th state (n is a natural number); a second memory string including a second select transistor, a third memory cell and a fourth memory cell connected in series, each of the third memory cell and the fourth memory being configured to store data by one of the first state, the second state . . . the n-th state; a first bit line connected to one end of the first memory string; a second bit line connected to one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a first word line connected to gates of the first memory cells and the third memory cell, respectively; a second word line connected to gates of the second memory cell and the fourth memory cell, respectively; a first select line connected to gates of the first select transistor and the second select transistor; a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits; and a second data storage circuit electrically connected to the
second bit line and including a plurality of second latch circuits, wherein when data is written to the first memory cell to change a state thereof from the first state to one of the first state, the second state, . . . the n state depending on a first data
after the first data is inputted to the first latch circuits in a first write operation, second data generated by the first data at the first latch
circuits in a second write operation, and data is read from the first memory cell written by
the first write operation, the first data is restored by the read data and the second data, and the second write operation is executed to the first memory cell once again by the restored first data.
Claim 2 (New): The semiconductor memory device according to claim 1, further comprising: a third memory string including a fifth select transistor, a plurality of third memory cells connected in series and a sixth select transistor, each of the third memory cells being configured to store data by one of the first state, the second state...the n-th state; a fourth memory string including a seventh select transistor, a plurality of fourth memory cells connected in series and an eighth select transistor, each of the fourth memory cells being configured to store data by one of the first state, the second state...the n-th state; and a second bit line connected to one end of the third memory string and one end of the fourth memory string; and a second data storage circuit electrically connected to the second bit line and including a plurality of second latch circuits, wherein each of the word lines is also connected to a gate of a corresponding one of the third memory cells and a gate of a corresponding one of the fourth memory cells, the first select line is also connected to a gate of the fifth select transistor, the second select line is also connected to a gate of the seventh select transistor, and the third select gate line is also connected to a gate of the sixth select transistor and a gate of the eighth select transistor.
2. The semiconductor memory device according to claim 1, further comprising: a third memory string including a third select transistor, a fifth memory cell and a sixth memory cell connected in series, each of the fifth memory cell and the sixth memory being configured to store data by one of the first state, the second state, . . . the n-th state; a fourth memory string including a fourth select transistor, a seventh memory cell and an eighth memory cell connected in series, each of the seventh memory cell and the eighth memory being configured to store data by one of the first state, the second state, . . . the n-th state; and a second select line connected to gates of the third select transistor and the fourth select transistor; wherein the first bit line is connected to one end of the third memory string; the second bit line is connected to one end of the fourth memory string; the source line connected to another ends of the third memory string and the fourth memory string; the first word line is connected to gates of the fifth memory cell and the seventh memory cell, respectively; and the second word line connected to gates of the sixth memory cell and the eighth memory cell, respectively.
Claim 3 (New): The semiconductor memory device according to claim 2, wherein when data is written to the one of the first memory cells, another data is simultaneously written to one of the third memory cells to change a state thereof from the first state to one of the first state, the second state,... the n state depending on a third data after the third data is inputted to the second latch circuits in the first write operation, a fourth second data is generated by the third data at the second latch circuits in the second write operation, the third data is restored by data read from the one of the third memory cells, and the fourth data, andthe second write operation is executed also to the one of the third memory cells by the restored third data.
3. The semiconductor memory device according to claim 1, wherein when data is written to the second memory cell and to the fourth memory cell to change each state thereof from the first state to one of the first state, the second state, . . . the n state depending on a third data after the third data is inputted to the first latch circuits and the second latch circuits in a third write operation, fourth data generated by the third data at the first latch circuits and the second latch circuits in a fourth write operation, and data are read from the second memory cell and from the fourth memory cell written by the third write operation, the third data is restored by the read data and the fourth data, and the fourth write operation is executed to the second memory cell and the fourth memory cell once again by the restored third data.
Claim 4 (New): The semiconductor memory device according to claim 1, wherein the second data distinguishes adjacent states among the first state, the second state,...the n state.
4. The semiconductor memory device according to claim 1, wherein the second data distinguishes adjacent state among the first state, the second state . . . the n state.
Claim 5 (New): The semiconductor memory device according to claim 1, wherein after the first write operation, another write operation is executed to another one of the first memory cells which is adjacent to the one of the first memory cells, and then the second write operation is executed to the one of the first memory cells.
5. The semiconductor memory device according to claim 1, wherein after the first write operation, a write operation is executed to the second memory cell, and then the second write operation is executed to the first memory cell.
Claim 6 (New): The semiconductor memory device according to claim 1, wherein the second write operation is executed after the first write operation.
6. The semiconductor memory device according to claim 1, wherein the second write operation is executed after the first write operation.
Claim 7 (New): The semiconductor memory device according to claim 1, wherein the first state is an E state, the second data is an A state, a third state is a B state, and a fourth state is a C state.
8. The semiconductor memory device according to claim 1, wherein the first state is an E state, the second data is an A state, a third state is a B state, and a fourth state is a C state.
Claim 8 (New): The semiconductor memory device according to claim 1, wherein when read voltage levels used for write verify of the one of the first memory cells in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading of data stored in the one of the first memory cells in the second write operation is E (A<E<B).
9. The semiconductor memory device according to claim 1, wherein when read voltage levels used for write verify of the memory cell in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading of data stored in the memory cell in the second write operation is E (A<E<B).
Claim 9 (New): The semiconductor memory device according to claim 1, whereinwhen read voltage levels used for write verify of the one of the first memory cells in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading of data stored in the one of the first memory cells in the second write operation is F (B<F<C).
10. The semiconductor memory device according to claim 1, wherein when read voltage levels used for write verify of the memory cell in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading of data stored in the memory cell in the second write operation is F (B<F<C).
Claim 10 (New): The semiconductor memory device according to claim 1, wherein a part of the first latch circuits temporarily stores bits, writing of at least data of 1 bit is completed during the first write operation, and data to be written in a subsequent write operation is temporarily held in a remaining part of the first latch circuits.
11. The semiconductor memory device according to claim 1, wherein a part of the latch circuits temporarily stores bits, writing of at least data of 1 bit is completed during the first write operation, and data to be written in a subsequent write operation is temporarily held in a remaining part of the latch circuits.
Claim 11 (New): The semiconductor memory device according to claim 1, wherein after an end of the second write operation, the second write operation is further repeatedly executed.
12. The semiconductor memory device according to claim 1, wherein after an end of the second write operation, the second write operation is again repeatedly executed.
Claim 12 (New): The semiconductor memory device according to claim 1, wherein the first write operation and second write operation are executed as one program sequence.
13. The semiconductor memory device according to claim 1, wherein the first write operation and second write operation are executed as one program sequence.
Clain 13 (New): The semiconductor memory device according to claim 1, wherein a control circuit executes a weak erase operation between the first write operation and the second write operation, and the control circuit applies a weak erase voltage to the one of the first memory cells in the weak erase operation, the weak erase voltage has a reverse voltage for a write voltage applied to the one of the first memory cells in the first and second write operations.
14. The semiconductor memory device according to claim 1, wherein a control circuit executes a weak erase operation between the first write operation and the second write operation, and the control circuit applies a weak erase voltage to the first memory cell in the weak erase operation, the weak erase voltage has a reverse voltage for a write voltage applied to the first memory cell in the first and second write operations.
As can be seen from the above table, both, claim 1 of the application and claim 1 of the patent, explicitly rely on (n)-state multi-level cell (MLC/TLC) storage, making the core data-density concept identical. Both, the application and the patent, recitations share the key feature of vertically stacked or linked word lines that tie corresponding cells across memory strings. The use of select lines to manage string operation is common to both recitations. The application outlines a multi-step write operation using latches to write data, generate a second data set, and restore the initial data for accuracy. Claim 1 of the patent outlines a write and restore operation that similarly generates a second dataset, saves it, and restores the initial data if power is lost or a subsequent write occurs. The core logic of using latch-based circuitry to read, restore, and re-execute programming is functionally identical. Claim 1 of the application specifies two memory strings connected in parallel sharing a bit line and common source line. Claim 1 of the patent defines two memory strings sharing a common source line (with dedicated or separate bit lines). The distinction between shared vs. separate bit lines and parallel vs. serial strings is a routine circuit design choice and an obvious architectural variation. Thus, the patent protections have been granted to the earlier filed patent application.
With respect to claim 2, as can be seen from the table above, both, claim 2 of the application and claim 2 of the patent, feature a third and a fourth memory string, each containing a plurality of memory cells and select transistors connected in series. Both specify that the memory cells are designed to store multi-state data (from a first state up to an (n)-th state). In both configurations, the third string connects to a first (or one) bit line, and the fourth string connects to a second bit line. Both link the opposite ends of both the third and fourth memory strings to a single, common source line. In claim 2 of the patent, the first word line connects to the gates of both the fifth and seventh memory cells. In claim 2 of the application, each word line connects directly to a memory cell in the third string and its corresponding memory cell in the fourth string (acting as a shared control for these gates). Claim 2 of the patent links the second select line to the gates of both the third and fourth select transistors. In claim 2 of the application, the second select line explicitly connects to the seventh select transistor (the fourth string's select). Therefore, there are minor sematic differences in how the nodes or select gates are defined, the application and the patent describe structurally overlapping memory arrays. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 3-13 are rejected over claims 1-6 and 8-14 of the patent ‘532.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12094532 [‘532]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘532
Claim 14 (New): A semiconductor memory device comprising: a first bit line; a first word line; a first source line; a first memory cell having one end electrically connected to the first bit line and the other end electrically connected to the first source line and a gate electrically connected to the first word line, the first memory cell being configured to store data by one of a first state, a second state,... n-th state (n is a natural number);wherein to write the first memory cell, a state of the first memory cell is changed from the first state to one of the first state, the second state,... the n state depending on a first data inputted in a first write operation, the first data is restored by data read from the first memory cell, the first memory cell is weakly erased, the first data is restored by data read from the one of the first memory cells, and the second data, and the second write operation is executed to the one of the first memory cells by the restored first data.
1. A semiconductor memory device comprising: a first memory string including a first select transistor, a first memory cell and a second memory cell connected in series, each of the first memory cell and the second memory cell being configured to store data by one of a first state, a second state, . . . n-th state (n is a natural number); a second memory string including a second select transistor, a third memory cell and a fourth memory cell connected in series, each of the third memory cell and the fourth memory being configured to store data by one of the first state, the second state . . . the n-th state; a first bit line connected to one end of the first memory string; a second bit line connected to one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a first word line connected to gates of the first memory cells and the third memory cell, respectively; a second word line connected to gates of the second memory cell and the fourth memory cell, respectively; a first select line connected to gates of the first select transistor and the second select transistor; a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits; and a second data storage circuit electrically connected to the second bit line and including a plurality of second latch circuits, wherein when data is written to the first memory cell to change a state thereof from the first state to one of the first state, the second state, . . . the n state depending on a first data after the first data is inputted to the first latch circuits in a first write operation, second data generated by the first data at the first latch circuits in a second write operation, and data is read from the first memory cell written by the first write operation, the first data is restored by the read data and the second data, and the second write operation is executed to the first memory cell once again by the restored first data.
As can be seen from the above table, Claim 14 of the application teaches a sequence of: initial programming, data read and restore, weak erase and then second write. Claim 1 of patent ‘532 teaches a sequence of: first write, read data, reconstruct first data (restore) and then second write. The steps of generating second data, reading the cell, reconstructing the data, and performing a second write are functionally and structurally identical to “data read and restore” and “second write” operations claimed in Claim 14 of the application. The logic of refining a memory cell’s threshold voltage via a read-reconstruct-rewrite sequence is identical in both claims. Additionally, both claims specify multiple programmable states and the use of data storage circuits (latches). Because multi-level cell (MLC) technology inherently requires latches to hold the incoming data and intermediate reconstructed data during multi-step programming sequences, the circuit architecture in Claim 1 of the patent is the standard, predictable implementation of the methodology claimed in Claim 14 of the application. Further, Claim 14 of the application broadly refers to memory cells linked to bit lines, word lines, and source lines. Claim 1 of the patent claims a highly specific layout (first and second strings with select transistors, alternating word lines, and multiple memory cells). Scaling memory strings, sharing source lines at opposite ends, and connecting cells in series to form NAND/NOR string architectures are conventional design choices. Thus, the patent protections have been granted to the earlier filed patent application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12094532 [‘532]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘532
Claim 15 (New): A method for writing data into a semiconductor memory device, the semiconductor memory device including: a first memory string including a first select transistor, a plurality of first memory cells connected in series and a second select transistor, each of the first memory cells being configured to store data by one of a first state, a second state,...n-th state (n is a natural number);a second memory string including a third select transistor, a plurality of second memory cells connected in series and a fourth select transistor, each of the second memory cells being configured to store data by one of the first state, the second state...the n-th state; a first bit line connected to one end of the first memory string and one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a plurality of word lines laminated in a vertical direction, each of the word lines connected to a gate of a corresponding one of the first memory cells and a gate of a corresponding one of the second memory cells; a first select line connected to a gate of the first select transistor; a second select line connected to a gate of the third select transistor; a third select line connected to a gate of the second select transistor and a gate of the fourth select transistor; and a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits, the method comprising: writing when data to one of the first memory cells to change a state thereof from the first state to one of the first state, the second state,... the n state depending on a first data after the first data is inputted to the first latch circuits; generating a second data by the first data at the first latch circuits; restoring the first data by data read from the one of the first memory cells, and the second data; and further writing the one of the first memory cells by the restored first data.
1. A semiconductor memory device comprising: a first memory string including a first select transistor, a first memory cell and a second memory cell connected in series, each of the first memory cell and the second memory cell being configured to store data by one of a first state, a second state, . . . n-th state (n is a natural number); a second memory string including a second select transistor, a third memory cell and a fourth memory cell connected in series, each of the third memory cell and the fourth memory being configured to store data by one of the first state, the second state . . . the n-th state; a first bit line connected to one end of the first memory string; a second bit line connected to one end of the second memory string; a source line connected to another ends of the first memory string and the second memory string; a first word line connected to gates of the first memory cells and the third memory cell, respectively; a second word line connected to gates of the second memory cell and the fourth memory cell, respectively; a first select line connected to gates of the first select transistor and the second select transistor; a first data storage circuit electrically connected to the first bit line and including a plurality of first latch circuits; and a second data storage circuit electrically connected to the second bit line and including a plurality of second latch circuits, wherein when data is written to the first memory cell to change a state thereof from the first state to one of the first state, the second state, . . . the n state depending on a first data after the first data is inputted to the first latch circuits in a first write operation, second data generated by the first data at the first latch circuits in a second write operation, and data is read from the first memory cell written by the first write operation, the first data is restored by the read data and the second data, and the second write operation is executed to the first memory cell once again by the restored first data.
As can be seen from the above table, both, Claim 15 of the application and Claim 1 of the patent, describe architectures comprising two memory strings (a first and a second string). Both strings contain multiple memory cells connected in series with select transistors. The core architecture of having a first memory string and a second memory string is identical in both phrases. Additionally, both designs utilize a bit line connection to one or both ends of the memory strings, and both involve reading/holding data states (e.g., using "latch circuits"). Further, Claim 1 of the patent uses a "first select line" to connect the gates of both the first and second select transistors, while Claim 15 of the application distinguishes them by having a first select line (top transistor 1), a second select line (top transistor 2), and a shared line (bottom select transistors). Furthermore, both describe the same sequence of operations: (1) writing to memory cells depending on first data via latch circuits, (2) generating second data at the latches, (3) restoring the first data using the read data and the second data, and (4) executing a second write operation with the restored first data. Although there are minor differences in specific word lines and select transistor connections (e.g., top versus bottom select lines), a person having ordinary skill in the art would find it obvious to combine or modify these elements due to their strong structural similarity. Thus, the patent protections have been granted to the earlier filed patent application.
Remarks
Applicant's amendment necessitated the new ground(s) of rejection
presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 10, 2026
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