DETAILED ACTION
This correspondence is in response to the communications received 08/22/2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/22/2024 and 07/24/2025 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
PNG
media_image1.png
878
621
media_image1.png
Greyscale
PNG
media_image2.png
728
690
media_image2.png
Greyscale
PNG
media_image3.png
773
604
media_image3.png
Greyscale
Regarding claim 1, 1. A semiconductor memory device comprising:
a bit line (BL) extending in a first direction (D1) on a substrate (100, see Fig. 1);
an active pattern (AP1 And AP2) on the bit line (see Fig. 2), the active pattern including a first side wall (SS1) and a second side wall (SS2) that are opposite to each other in the first direction (see Fig. 4) and a first surface (S1) and a second surface (S2) that are opposite to each other in a vertical direction (see Fig. 4), the first surface of the active pattern being connected to the bit line (see Fig. 4);
a word line (WL1 and WL2) on the first side wall of the active pattern (see Fig. 4), the word line extending in a second direction (D2, see Fig. 1); and
a data storage pattern (DSP) on the active pattern (see Fig. 2), the data storage pattern connected to the second surface of the active pattern (see Figs. 2 and 4),
wherein the word line includes a first line pattern (WL_M1) including a first conductive material, a second line pattern (WL_M2) including a second conductive material different from the first conductive material, and a third line pattern (WL_M3) including a third conductive material different from the first conductive material (See [0097]), and
the first line pattern is between the second line pattern and the third line pattern (see Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Kim et al. (US 20220139921 A1, published 05/05/2022).
PNG
media_image4.png
643
1055
media_image4.png
Greyscale
PNG
media_image5.png
724
849
media_image5.png
Greyscale
Regarding claim 1, Figs. 1-19 of Xiao disclose a semiconductor memory device (“The following describes the manufacturing method of a semiconductor structure with reference to FIGS. 1 to 19 … The semiconductor structure is described below by using a DRAM as an example, but this embodiment is not limited thereto”, [0039]-[0040], as DRAM is a type of memory, the semiconductor structure is a semiconductor memory device) comprising:
a bit line (“bit line 100”, [0069]) extending in a first direction (“third direction Z”, [0062]) on a substrate (“substrate 10”, [0049], as seen in Fig. 18, 100 extends in the Z direction on 10);
an active pattern (“active pillar 140”, [0082], where 140 includes “first segment 141”, [0086], “second segment 142”, [0086], and “third segment 143”, [0086] and “the silicon pillar 20 is preprocessed to form the active pillar 140”, [0082], thus 140 is formed of silicon) on the bit line (as seen in Fig. 18, 140 is on 100), the active pattern including a first side wall and a second side wall that are opposite to each other in the first direction (as seen in Fig. 18, 140 has a right side wall and a left side wall that are first and second side walls respectively, where the right and left sidewalls are opposite to each other in the Z direction) and a first surface and a second surface that are opposite to each other in a vertical direction (as seen in Fig. 18, 140 has a lower surface and an upper surface that are first and second surfaces respectively, where the lower and upper surfaces are opposite to each other in the vertical direction), the first surface of the active pattern being connected to the bit line (as seen in Fig. 18, the bottom surface of 140 is connected to 100);
a word line (“word line structure 170”, [0095], where 170 includes “first word lines 171”, [0097], “second word line 172”, [0099], “third word line 173”, [0101], and “fourth word line 174”, [0103]) on the first side wall of the active pattern (as seen in Fig. 18, 171/172/173/174 are on the right side wall of 140), the word line extending in a second direction (as seen in Fig. 18, 171/172/173/174 extend in the “second direction Y”, [0053]); and
a data storage pattern on the active pattern (“It should be noted that the bit line may be connected to the drain of the subsequently formed active pillar. In a transistor, a gate is connected to a word line, and a source is connected to a capacitor structure. The voltage signal on the word line is transmitted to the gate, such that the transistor is controlled to turn on or off, and data information stored in the capacitor structure is read through the bit line, or data information is written into the capacitor structure through the bit line for storage”, [0071], thus Xiao discloses a capacitor structure connected to a source of 140 that is used for storage, Xiao does not directly disclose a data storage pattern on the active pattern, therefore a secondary reference will be used to teach this limitation below), the data storage pattern connected to the second surface of the active pattern (as “third segment 143 forms the source”, [0086], this capacitor structure will therefore be on the upper surface of 140),
wherein the word line includes a first line pattern (172 is a first line pattern) including a first conductive material (“A material of the second word line 172 may include, but is not limited to, tungsten or polycrystalline silicon”, [0100], thus 172 may be formed from tungsten), a second line pattern (173 is a second line pattern) including a second conductive material (“The material of the third word line 173 may include, but is not limited to, titanium nitride”, [0102]) different from the first conductive material (tungsten is different from titanium nitride), and a third line pattern (171 is third line pattern) including a third conductive material (“The material of the first word line 171 may include, but is not limited to, titanium nitride”, [0098]) different from the first conductive material (tungsten is different from titanium nitride), and
the first line pattern is between the second line pattern and the third line pattern (as seen in Fig. 19, a portion of 173 is between 172 and 171).
Xiao fails to disclose “a data storage pattern on the active pattern”.
PNG
media_image6.png
656
922
media_image6.png
Greyscale
However, in a similar field of endeavor, Figs. 1-3 of Kim teach a data storage pattern on the active pattern (as seen in Fig. 2A, “capacitor structures CAP”, [0020] are on the top of “semiconductor device 100”, [0020], thus after combination with Xiao, CAP of Kim will be on 140 of Xiao.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a data storage pattern on the active pattern” as taught by Kim in the structure of Xiao for the purpose of providing a specific location for the capacitor structure.
Regarding claim 2, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim disclose the semiconductor memory device of claim 1, Figs. 1-19 of Xiao further disclose wherein the second conductive material is identical to the third conductive material (as discussed above, both 173 and 171 may include titanium nitride).
Regarding claim 3, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim disclose the semiconductor memory device of claim 1, Figs. 1-19 of Xiao further disclose wherein the first line pattern is in contact with the second line pattern and the third line pattern (as seen in Fig. 19, 172 is in contact with 173 and 171).
Regarding claim 4, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim disclose the semiconductor memory device of claim 1, Figs. 1-19 of Xiao further disclose wherein the word line further includes a fourth line pattern (“fourth word line 174”, [0103]) between the first line pattern and the second line pattern (as seen in Fig. 19, 174 is between 172 and a portion of 173), and
the fourth line pattern includes a fourth conductive material (“A material of the fourth word line 174 may include, but is not limited to, tungsten or polycrystalline silicon”, [0103], thus 174 may be formed from polycrystalline silicon) different from the first conductive material and the second conductive material (polycrystalline silicon is different from the tungsten of 172 and the titanium nitride of 173).
Regarding claim 6, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim disclose the semiconductor memory device of claim 1, Figs. 1-19 of Xiao further disclose wherein at least one of the first line pattern, the second line pattern, or the third line pattern includes an internal interface extending in the vertical direction (as seen in Fig. 19, 171 has an internal interface extending in the vertical direction).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Kim et al. (US 20220139921 A1, published 05/05/2022) in view of Tang et al. (US 20240349479 A1, filed 07/14/2023).
Regarding claim 7, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim disclose the semiconductor memory device of claim 1.
Xiao in combination with Kim fails to disclose “further comprising:
a back gate electrode on the second side wall of the active pattern, the back gate electrode extending in the second direction,
wherein the active pattern is between the back gate electrode and the word line.”
PNG
media_image7.png
523
558
media_image7.png
Greyscale
However, in a similar field of endeavor, Figs. 1-8C of Tang teach further comprising:
a back gate electrode (“conductive layer 226 may serve as back gate”, [0062], where “the interference between adjacent word lines may be prevented by applying a reference voltage (e.g., a ground voltage) to the back gates”, [0062], and “the material of the conductive layer 226 includes any suitable conductive material, such as tungsten, copper, aluminum, titanium nitride, tantalum nitride, doped polysilicon, etc”, [0062], thus 226 may be formed of copper) on the second side wall of the active pattern (as seen in Fig. 7B, 226 is on both left and right sidewalls of “semiconductor layer 211”, [0048], where 211 of Tang is equivalent to 140 of Xiao as “The material of the semiconductor layer 211 may comprise silicon”, [0048] similar to 140 of Xiao), the back gate electrode extending in the second direction (after combination with Xiao, 226 will extend in the Y direction of Xiao),
wherein the active pattern is between the back gate electrode and the word line (as seen in Fig. 7B, 211 is between 226 and 227 where “One of the two first gates 227 extends continuously in the second direction D2 and serves as a word line of a DRAM”, [0075]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
a back gate electrode on the second side wall of the active pattern, the back gate electrode extending in the second direction,
wherein the active pattern is between the back gate electrode and the word line” as taught by Tang in the system of Xiao in combination with Kim for the purpose of reducing interference between word lines.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Kim et al. (US 20220139921 A1, published 05/05/2022) in view of Tang et al. (US 20240349479 A1, filed 07/14/2023) in view of Furukawa et al. (US 6,444,405 B1, published 09/03/2002).
Regarding claim 8, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim and Figs. 1-8C of Tang disclose the semiconductor memory device of claim 7.
Xiao in combination with Kim and Tang fails to disclose “wherein the back gate electrode includes a plurality of electrode patterns stacked in the vertical direction”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 34-39 of Furukawa teach wherein the back gate electrode includes a plurality of electrode patterns stacked in the vertical direction (Furukawa states “Copper tends to diffuse into silicon oxide films and cannot firmly adhere to silicon oxide films. Therefore, it is generally necessary to provide a barrier metal film between a copper film and a silicon oxide film, in order to form copper plugs or copper wires in the through holes made in the silicon oxide film. The barrier metal film should be, for example, a titanium nitride film, which inhibits diffusion of copper and firmly adheres to the silicon oxide film”, col. 21, lines 46-53, therefore in order to prevent diffusion of the copper atoms of 226 of Tang into 225 of Tang when “the material of the second gate insulation layer 225 is silicon oxide”, Tang, [0062], 226 of Tang can be surrounded in a titanium nitride barrier layer, by surrounding 226 with a barrier layer, thus the back gate will include a plurality of electrode patterns stacked in the vertical direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the back gate electrode includes a plurality of electrode patterns stacked in the vertical direction” as taught by Furukawa in the system of Xiao in combination with Kim and Tang for the purpose of preventing the migration of copper atoms into neighboring dielectric layers.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Kim et al. (US 20220139921 A1, published 05/05/2022) in view of Tanaka et al. (US 11,183,499 B2, filed 11/23/2021).
Regarding claim 10, Figs. 1-19 of Xiao in combination with Figs. 1-3 of Kim disclose the semiconductor memory device of claim 1, Figs. 1-19 of Xiao further disclose wherein the bit line includes an upper surface and a bottom surface that are opposite to each other in the vertical direction (as seen in Fig. 18, 100 includes an upper surface and a bottom surface that are opposite to each other in the vertical direction),
the upper surface of the bit line looks at the active pattern (as seen in Fig. 18, the upper surface of 110 looks at 140).
Xiao in combination with Kim fails to disclose “further comprising:
a shielding conductive pattern adjacent to the bit line in the second direction, the shielding conductive pattern extending in the first direction,
wherein … the shielding conductive pattern is absent on the bottom surface of the bit line”.
PNG
media_image8.png
473
543
media_image8.png
Greyscale
PNG
media_image9.png
392
277
media_image9.png
Greyscale
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1A-5J of Tanaka teach further comprising:
a shielding conductive pattern (“shield conductor material layer 122a”, col. 4, line 59, where “the parasitic capacitance of the bit line can be reduced by the shield conductor layer. Thereby, the resistance capacitance delay (RC-delay) can be reduced, and the dynamic random access memory can have enough sensing margins. Accordingly, the dynamic random access memory can have higher reliability and is conducive to apply to the low power dynamic random access memory structure”, col. 2, lines 25-32) adjacent to the bit line (“bit line BL”, col. 4, line 2) in the second direction (as seen in Fig. 1D, 122a runs parallel to BL in a top down view, thus after combination with Xiao, 122a will run parallel to 100 of Xiao, and will therefore be adjacent to 100 of Xiao in the Y direction of Xiao), the shielding conductive pattern extending in the first direction (by running parallel to 100 of Xiao, 122a of Tanaka will extend in the Z direction of Xiao),
wherein … the shielding conductive pattern is absent on the bottom surface of the bit line (as seen in Fig. 2J, 122a is only present to the sides of BL and is thus absent from the bottom surface of BL).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
a shielding conductive pattern adjacent to the bit line in the second direction, the shielding conductive pattern extending in the first direction,
wherein … the shielding conductive pattern is absent on the bottom surface of the bit line” as taught by Tanaka in the system of Xiao in combination with Kim for the purpose of reducing parasitic capacitance between bit lines and thereby improving device performance.
Claims 11, 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Tang et al. (US 20240349479 A1, filed 07/14/2023) in view of Kim et al. (US 20220139921 A1, published 05/05/2022) in view of Furukawa et al. (US 6,444,405 B1, published 09/03/2002).
Regarding claim 11, Figs. 1-19 of Xiao disclose a semiconductor memory device (“The following describes the manufacturing method of a semiconductor structure with reference to FIGS. 1 to 19 … The semiconductor structure is described below by using a DRAM as an example, but this embodiment is not limited thereto”, [0039]-[0040], as DRAM is a type of memory, the semiconductor structure is a semiconductor memory device) comprising:
a bit line (“bit line 100”, [0069]) extending in a first direction (“third direction Z”, [0062]) on a substrate (“substrate 10”, [0049], as seen in Fig. 18, 100 extends in the Z direction on 10);
a word line on the bit line (“word line structure 170”, [0095], where 170 includes “first word lines 171”, [0097], “second word line 172”, [0099], “third word line 173”, [0101], and “fourth word line 174”, [0103]), the word line extending in a second direction (as seen in Fig. 18, 171/172/173/174 extend in the “second direction Y”, [0053]);
an active pattern (“active pillar 140”, [0082], where 140 includes “first segment 141”, [0086], “second segment 142”, [0086], and “third segment 143”, [0086] and “the silicon pillar 20 is preprocessed to form the active pillar 140”, [0082], thus 140 is formed of silicon) between the word line and the back gate electrode (Xiao does not disclose a back gate electrode therefore a secondary reference will be used to teach this limitation below); and
a data storage pattern on the active pattern (“It should be noted that the bit line may be connected to the drain of the subsequently formed active pillar. In a transistor, a gate is connected to a word line, and a source is connected to a capacitor structure. The voltage signal on the word line is transmitted to the gate, such that the transistor is controlled to turn on or off, and data information stored in the capacitor structure is read through the bit line, or data information is written into the capacitor structure through the bit line for storage”, [0071], thus Xiao discloses a capacitor structure connected to a source of 140 that is used for storage, Xiao does not directly disclose a data storage pattern on the active pattern, therefore a secondary reference will be used to teach this limitation below), the data storage pattern connected to the active pattern (as “third segment 143 forms the source”, [0086], this capacitor structure will therefore be on the upper surface of 140),
wherein the word line includes a first line pattern (172 is a first line pattern) and a second line pattern (173 is a second line pattern) stacked in a vertical direction (as seen in Fig. 19, 172 and 173 are stacked in a vertical direction),
the first line pattern includes a conductive material (“A material of the second word line 172 may include, but is not limited to, tungsten or polycrystalline silicon”, [0100], thus 172 may be formed from tungsten) different from the second line pattern (“The material of the third word line 173 may include, but is not limited to, titanium nitride”, [0102], tungsten is different from titanium nitride).
Xiao does not disclose “a back gate electrode on the bit line, the back gate electrode extending in the second direction, the back gate being spaced apart from the word line in the first direction;
an active pattern between the word line and the back gate electrode;
a data storage pattern on the active pattern;
wherein … the back gate electrode includes a first electrode pattern and a second electrode pattern stacked in the vertical direction,
the first electrode pattern includes a conductive material different from the second electrode pattern.”
However, in a similar field of endeavor, Figs. 1-8C of Tang teach a back gate electrode (“conductive layer 226 may serve as back gate”, [0062], where “the interference between adjacent word lines may be prevented by applying a reference voltage (e.g., a ground voltage) to the back gates”, [0062], and “the material of the conductive layer 226 includes any suitable conductive material, such as tungsten, copper, aluminum, titanium nitride, tantalum nitride, doped polysilicon, etc”, [0062], thus 226 may be formed of copper) on the bit line (as seen in Fig. 18 of Xiao, 170 of Xiao is on 100 of Xiao, thus after combination of Tang with Xiao, 226 of Tang will be on 100 of Xiao as 226 will between instances of 170 of Xiao), the back gate electrode extending in the second direction (as 170 of Xiao extends in the Y direction of Xiao, so too will 226 of Tang after combination with Xiao), the back gate being spaced apart from the word line in the first direction (as seen in Fig. 7B, 226 is spaced apart from 227 where “One of the two first gates 227 extends continuously in the second direction D2 and serves as a word line of a DRAM”, [0075], thus after combination with Xiao, 227 of Tang will be spaced apart from 170 of Xiao in the Z direction of Xiao);
an active pattern between the word line and the back gate electrode (as seen in Fig. 7B, “semiconductor layer 211”, [0048], is between 226 and 227, where 211 of Tang is equivalent to 140 of Xiao as “The material of the semiconductor layer 211 may comprise silicon”, [0048] similar to 140 of Xiao).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a back gate electrode on the bit line, the back gate electrode extending in the second direction, the back gate being spaced apart from the word line in the first direction;
an active pattern between the word line and the back gate electrode” as taught by Tang in the system of Xiao for the purpose of reducing interference between word lines.
Xiao in combination with Tang fails to disclose “a data storage pattern on the active pattern;
wherein … the back gate electrode includes a first electrode pattern and a second electrode pattern stacked in the vertical direction,
the first electrode pattern includes a conductive material different from the second electrode pattern.”
However, in a similar field of endeavor, Figs. 1-3 of Kim teach a data storage pattern on the active pattern (as seen in Fig. 2A, “capacitor structures CAP”, [0020] are on the top of “semiconductor device 100”, [0020], thus after combination with Xiao, CAP of Kim will be on 140 of Xiao.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a data storage pattern on the active pattern” as taught by Kim in the structure of Xiao in combination with Tang for the purpose of providing a specific location for the capacitor structure.
Xiao in combination with Tang and Kim fails to disclose “wherein … the back gate electrode includes a first electrode pattern and a second electrode pattern stacked in the vertical direction,
the first electrode pattern includes a conductive material different from the second electrode pattern.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 34-39 of Furukawa teach wherein … the back gate electrode includes a first electrode pattern and a second electrode pattern stacked in the vertical direction (Furukawa states “Copper tends to diffuse into silicon oxide films and cannot firmly adhere to silicon oxide films. Therefore, it is generally necessary to provide a barrier metal film between a copper film and a silicon oxide film, in order to form copper plugs or copper wires in the through holes made in the silicon oxide film. The barrier metal film should be, for example, a titanium nitride film, which inhibits diffusion of copper and firmly adheres to the silicon oxide film”, col. 21, lines 46-53, therefore in order to prevent diffusion of the copper atoms of 226 of Tang into 225 of Tang when “the material of the second gate insulation layer 225 is silicon oxide”, Tang, [0062], 226 of Tang can be surrounded in a titanium nitride barrier layer, by surrounding 226 with a barrier layer, thus the back gate can include a first copper layer surrounded by a titanium nitride second layer that will be stacked in the vertical direction),
the first electrode pattern includes a conductive material different from the second electrode pattern (as discussed above, the first electrode pattern can be formed of copper, and the second electrode pattern can be formed of titanium nitride.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein … the back gate electrode includes a first electrode pattern and a second electrode pattern stacked in the vertical direction,
the first electrode pattern includes a conductive material different from the second electrode pattern.” as taught by Furukawa in the system of Xiao in combination with Tang and Kim for the purpose of preventing the migration of copper atoms into neighboring dielectric layers.
Regarding claim 12, Figs. 1-19 of Xiao in combination with Figs. 1-8C of Tang, Figs. 1-3 of Kim, and Figs. 34-39 of Furukawa disclose the semiconductor memory device of claim 11, Figs. 1-19 of Xiao further disclose wherein the word line further includes a third line pattern (171 is third line pattern) including a conductive material (“The material of the first word line 171 may include, but is not limited to, titanium nitride”, [0098]) different from the first line pattern (tungsten is different from titanium nitride), and
the first line pattern is between the second line pattern and the third line pattern (as seen in Fig. 19, a portion of 173 is between 172 and 171).
Regarding claim 14, Figs. 1-19 of Xiao in combination with Figs. 1-8C of Tang, Figs. 1-3 of Kim, and Figs. 34-39 of Furukawa disclose the semiconductor memory device of claim 11, Figs. 1-19 of Xiao further disclose wherein one of the first line pattern or the second line pattern includes an internal interface extending in the vertical direction (as seen in Fig. 19, 173 has an internal interface extending in the vertical direction).
Regarding claim 15, Figs. 1-19 of Xiao in combination with Figs. 1-8C of Tang, Figs. 1-3 of Kim, and Figs. 34-39 of Furukawa disclose the semiconductor memory device of claim 11, Figs. 34-39 of Furukawa further disclose wherein one of the first electrode pattern or the second electrode pattern includes an internal interface extending in the vertical direction (after combination of Furukawa with Tang, the titanium nitride layer will form an internal interface extending in the vertical direction with the copper layer).
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Lee (US 11,637,190 B2, published 04/25/2023) in view of Tanaka et al. (US 11183499 B2, filed 11/23/2021) in view of Tang et al. (US 20240349479 A1, filed 07/14/2023).
Regarding claim 17, Figs. 1-19 of Xiao disclose a semiconductor memory device (“The following describes the manufacturing method of a semiconductor structure with reference to FIGS. 1 to 19 … The semiconductor structure is described below by using a DRAM as an example, but this embodiment is not limited thereto”, [0039]-[0040], as DRAM is a type of memory, the semiconductor structure is a semiconductor memory device).
Xiao fails to disclose “a peri-gate structure on a substrate;
a first bonding pad connected to the peri-gate structure;
a second bonding pad on the first bonding pad, the second bonding pad being in contact with the first bonding pad”.
PNG
media_image10.png
736
681
media_image10.png
Greyscale
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1A-17 of Lee teach a peri-gate structure (“Peripheral transistors TR”, col. 3, line 30, where “peripheral transistor TR may include impurity regions IR, a gate insulating layer GI, and a gate electrode GM”, col. 3, lines 34-36, together GI and GM are a peripheral gate structure) on a substrate (as seen in Fig. 1A, GI and GM are on “substrate 100”, col. 3, line 14, further as seen in Fig. 1A, a memory cell structure is stacked on the region in which TR is formed, this structure can be applied to Xiao, where the structure of Xiao is stacked on the TR region of Lee);
a first bonding pad (“first conductors CB1”, col. 3, line 50) connected to the peri-gate structure (as seen in Fig. 1A, CB1 is connected to GI and GM via “First contacts CT1”, col. 3, line 50, and via TR);
a second bonding pad (“second conductor CB2”, col. 4, line 6) on the first bonding pad (as seen in Fig. 1A, CB2 is on CB1), the second bonding pad being in contact with the first bonding pad (as seen in Fig. 1A, CB2 is in contact with CB1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a peri-gate structure;
a first bonding pad connected to the peri-gate structure;
a second bonding pad on the first bonding pad, the second bonding pad being in contact with the first bonding pad;” as taught by Lee in the system of Xiao for the purpose of integrating peripheral transistors to increase device functionality.
Figs. 1-19 of Xiao further disclose a bit line (“bit line 100”, [0069]) extending in a first direction (“third direction Z”, [0062]) on the second bonding pad (after combination of Xiao and Lee, the entire structure of Xiao will be on CB2 of Lee, thus 100 of Xiao will be on CB2 of Lee), the bit line extending in a first direction as seen in Fig. 18, 100 extends in “third direction Z”, [0062]).
Xiao in combination with Lee fails to disclose “a shielding conductive pattern including a plurality of shielding conductive line patterns on the second bonding pad, the shielding conductive pattern extending in the first direction to be adjacent to the bit line”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1A-5J of Tanaka teach a shielding conductive pattern (“shield conductor material layer 122a”, col. 4, line 59, where “the parasitic capacitance of the bit line can be reduced by the shield conductor layer. Thereby, the resistance capacitance delay (RC-delay) can be reduced, and the dynamic random access memory can have enough sensing margins. Accordingly, the dynamic random access memory can have higher reliability and is conducive to apply to the low power dynamic random access memory structure”, col. 2, lines 25-32) including a plurality of shielding conductive line patterns (as seen in Fig. 2J, there is a plurality of 122a) on the second bonding pad (after combination, 122a of Tanaka will be adjacent to 100 of Xiao and thus on CB2 of Lee), the shielding conductive pattern extending in the first direction to be adjacent to the bit line (as seen in Fig. 1D, 122a runs parallel to “bit line BL”, col. 4, line 2, in a top down view, thus after combination with Xiao, 122a will run parallel to 100 of Xiao, and will therefore extend in the Z direction of Xiao).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a shielding conductive pattern including a plurality of shielding conductive line patterns on the second bonding pad, the shielding conductive pattern extending in the first direction to be adjacent to the bit line” as taught by Tanaka in the system of Xiao in combination with Lee for the purpose of reducing parasitic capacitance between bit lines and thereby improving device performance.
Figs. 1-19 of Xiao further disclose a first word line (“word line structure 170”, [0095], where 170 includes “first word lines 171”, [0097], “second word line 172”, [0099], “third word line 173”, [0101], and “fourth word line 174”, [0103], specifically the instances of 171/172/173/174 directly to the left of “word line isolation structures 50”, [0062], are a first word line) on the bit line (as seen in Fig. 18, 171/172/173/174 are on 100) and the shielding conductive pattern (as 122a of Tanaka will be at the same vertical level as 100 of Xiao, 171/172/173/174 will also be on 122a of Tanaka), the first word line extending in a second direction (as seen in Fig. 18, 171/172/173/174 extend in the “second direction Y”, [0053]);
a second word line (the instances of 171/172/173/174 directly to the right of 50 are a second word line) on the bit line (as seen in Fig. 18, 171/172/173/174 are on 100) and the shielding conductive pattern(as 122a of Tanaka will be at the same vertical level as 100 of Xiao, 171/172/173/174 will also be on 122a of Tanaka), the second word line extending in the second direction (as seen in Fig. 18, 171/172/173/174 extend in the “second direction Y”, [0053]), the second word line being spaced apart from the first word line in the first direction (as seen in Fig. 19, the instances of 171/172/173/174 directly to the right of 50 are spaced apart from the instances of 171/172/173/174 directly to the left of 50).
Xiao in combination with Lee and Tanaka fails to disclose “a back gate electrode between the first word line and the second word line, the back gate electrode extending in the second direction”.
However, in a similar field of endeavor, Figs. 1-8C of Tang teach a back gate electrode (“conductive layer 226 may serve as back gate”, [0062], where “the interference between adjacent word lines may be prevented by applying a reference voltage (e.g., a ground voltage) to the back gates”, [0062], and “the material of the conductive layer 226 includes any suitable conductive material, such as tungsten, copper, aluminum, titanium nitride, tantalum nitride, doped polysilicon, etc”, [0062], thus 226 may be formed of copper) between the first word line and the second word line (as the first and second instances of 171/172/173/174 of Xiao alternate, any position of 226 of Tang will necessarily be between one of each), the back gate electrode extending in the second direction (as 170 of Xiao extends in the Y direction of Xiao, so too will 226 of Tang after combination with Xiao).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a back gate electrode between the first word line and the second word line, the back gate electrode extending in the second direction” as taught by Tang in the system of Xiao in combination with Lee and Tanaka for the purpose of reducing interference between word lines.
Figs. 1-19 of Xiao further disclose a first active pattern (“active pillar 140”, [0082], where 140 includes “first segment 141”, [0086], “second segment 142”, [0086], and “third segment 143”, [0086], here 141 is interpretated as the first active pattern, and “the silicon pillar 20 is preprocessed to form the active pillar 140”, [0082], thus 140 is formed of silicon) on the bit line (as seen in Fig. 18, 141 is on 100) and between the first word line and the back gate electrode (as seen in Fig. 7B of Tang, 226 is separated from 227 by “semiconductor layer 211”, [0048], where “One of the two first gates 227 extends continuously in the second direction D2 and serves as a word line of a DRAM”, [0075], thus 141 of Xiao will be between a first instance of 171/172/173/174 of Xiao and 226 of Tang after combination of the references);
a second active pattern (here 142 is interpretated as the second active pattern) on the bit line (as seen in Fig. 18, 142 is on 100) and between the first word line and the back gate electrode (similar to 141, 142 will also be between a first instance of 171/172/173/174 of Xiao and 226 of Tang after combination of the references); and
a data storage pattern (“It should be noted that the bit line may be connected to the drain of the subsequently formed active pillar. In a transistor, a gate is connected to a word line, and a source is connected to a capacitor structure. The voltage signal on the word line is transmitted to the gate, such that the transistor is controlled to turn on or off, and data information stored in the capacitor structure is read through the bit line, or data information is written into the capacitor structure through the bit line for storage”, [0071], thus Xiao discloses a capacitor structure connected to a source of 140 that is used for storage) connected to the first active pattern and the second active pattern (as “third segment 143 forms the source”, [0086], this capacitor structure will therefore be on the upper surface of 140 and therefore 141 and 142),
wherein each of the first word line and the second word line includes a first line pattern (172 is a first line pattern) including a first conductive material (“A material of the second word line 172 may include, but is not limited to, tungsten or polycrystalline silicon”, [0100], thus 172 may be formed from tungsten), a second line pattern (173 is a second line pattern) including a second conductive material (“The material of the third word line 173 may include, but is not limited to, titanium nitride”, [0102]) different from the first conductive material (tungsten is different from titanium nitride), and a third line pattern (171 is third line pattern) including a third conductive material (“The material of the first word line 171 may include, but is not limited to, titanium nitride”, [0098]) different from the first conductive material (tungsten is different from titanium nitride).
Regarding claim 20, Figs. 1-19 of Xiao in combination with Figs. 1A-17 of Lee, Figs. 1A-5J of Tanaka, and Figs. 1-8C of Tang disclose the semiconductor memory device of claim 17, Figs. 1-19 of Xiao further disclose wherein at least one of the first line pattern, the second line pattern, or the third line pattern includes an internal interface extending in a vertical direction (as seen in Fig. 19, 171 has an internal interface extending in the vertical direction).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230170416 A1, published 06/01/2023) in view of Lee (US 11,637,190 B2, published 04/25/2023) in view of Tanaka et al. (US 11183499 B2, filed 11/23/2021) in view of Tang et al. (US 20240349479 A1, filed 07/14/2023) in view of Furukawa et al. (US 6,444,405 B1, published 09/03/2002).
Regarding claim 18, Figs. 1-19 of Xiao in combination with Figs. 1A-17 of Lee, Figs. 1A-5J of Tanaka, and Figs. 1-8C of Tang disclose the semiconductor memory device of claim 17.
Xiao in combination with Lee, Tanaka, and Tang fails to disclose “wherein the back gate electrode includes a plurality of electrode patterns stacked in a vertical direction.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 34-39 of Furukawa teach wherein the back gate electrode includes a plurality of electrode patterns stacked in a vertical direction ((Furukawa states “Copper tends to diffuse into silicon oxide films and cannot firmly adhere to silicon oxide films. Therefore, it is generally necessary to provide a barrier metal film between a copper film and a silicon oxide film, in order to form copper plugs or copper wires in the through holes made in the silicon oxide film. The barrier metal film should be, for example, a titanium nitride film, which inhibits diffusion of copper and firmly adheres to the silicon oxide film”, col. 21, lines 46-53, therefore in order to prevent diffusion of the copper atoms of 226 of Tang into 225 of Tang when “the material of the second gate insulation layer 225 is silicon oxide”, Tang, [0062], 226 of Tang can be surrounded in a titanium nitride barrier layer, by surrounding 226 with a barrier layer, thus the back gate can include a first copper layer surrounded by a titanium nitride second layer that will be stacked in the vertical direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the back gate electrode includes a plurality of electrode patterns stacked in a vertical direction” as taught by Furukawa in the system of Xiao in combination with Lee, Tanaka, and Tang for the purpose of preventing the migration of copper atoms into neighboring dielectric layers.
Allowable Subject Matter
Claims 5, 9, 13, 16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor memory device as recited in the claims of the instant application.
Regarding claim 5, the prior art of Xiao et al. (US 20230170416 A1) in view of Kim et al. (US 20220139921 A1) discloses a similar semiconductor memory device but fails to disclose the specific claims of the instant application regarding the structure and composition of a fifth line pattern e.g. “wherein the word line further includes a fifth line pattern between the first line pattern and the third line pattern, and
the fifth line pattern includes a fifth conductive material different from the first conductive material and the third conductive material”.
Regarding claim 9, the prior art of Xiao et al. (US 20230170416 A1) in view of Kim et al. (US 20220139921 A1) in view of Tanaka et al. (US 11,183,499 B2) discloses a similar semiconductor memory device but fails to disclose the specific claims of the instant application regarding the structure of the shielding conductive pattern e.g. “wherein the shielding conductive pattern includes a shielding conductive plate, and a plurality of shielding conductive line patterns protruding from the shielding conductive plate”.
Regarding claim 13, the prior art of Xiao et al. (US 20230170416 A1) in view of Tang et al. (US 20240349479 A1) in view of Kim et al. (US 20220139921 A1) in view of Furukawa et al. (US 6,444,405 B1) discloses a similar semiconductor memory device but fails to disclose the specific claims of the instant application regarding the structure and composition of the back gate electrode e.g. “wherein the back gate electrode further includes a third electrode pattern including a conductive material different from the first electrode pattern, and
the first electrode pattern is between the second electrode pattern and the third electrode pattern”.
Regarding claim 16, the prior art of Xiao et al. (US 20230170416 A1) in view of Tang et al. (US 20240349479 A1) in view of Kim et al. (US 20220139921 A1) in view of Furukawa et al. (US 6,444,405 B1) discloses a similar semiconductor memory device but fails to disclose the specific claims of the instant application regarding the structure of the shielding conductive pattern e.g. “wherein the shielding conductive pattern includes a shielding conductive plate and a plurality of shielding conductive line patterns protruding from the shielding conductive plate”.
Regarding claim 19, the prior art of Xiao et al. (US 20230170416 A1) in view of Lee (US 11,637,190 B2) in view of Tanaka et al. (US 11183499 B2) in view of Tang et al. (US 20240349479 A1) discloses a similar semiconductor memory device but fails to disclose the specific claims of the instant application regarding the structure of the shielding conductive pattern e.g. “wherein the shielding conductive pattern further includes a shielding conductive plate,
the shielding conductive line patterns protrude from the shielding conductive plate in a vertical direction”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights