Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application filed August 22, 2024.
Claims 1-14 are currently pending.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on Japanese Patent Application No. 2023-138187 filed on August 28, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 22, 2024 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on August 22, 2024 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., US 2023/0275149 A1 (hereinafter Wu) in view of Yamamoto et al., US 2021/0217886 A1 (hereinafter Yamamoto).
Regarding claim 1, Wu discloses: A semiconductor device comprising: a source electrode provided on a substrate (Wu, FIGs. 1, 3 show source region 118 [the source electrode] provided on semiconductor substrate 143 [the substrate], [0024]);
a gate electrode provided on the substrate and surrounding a part of the source electrode (Wu, FIGs. 1, 3 show gate electrode 109A [the gate electrode] provided on semiconductor substrate 143 [the substrate] and surrounding source region 118 [the source electrode], [0024]);
a drain electrode provided on the substrate and surrounding the gate electrode (Wu, FIGs. 1, 3 show drain region 127 [the drain electrode] provided on semiconductor substrate 143 [the substrate] and surrounding gate electrode 109A [the gate electrode], [0024]); and
a gate wiring provided on the substrate (Wu, FIGs. 1, 3, gate contact plug 113, [0031]), wherein a first end of the gate wiring is connected to only one portion of the gate electrode (Wu, FIG. 1 shows bottom end of gate contact plug 113 [the first end of the gate wiring] connected to only one portion of gate electrode 109A [the gate electrode])
Although Wu, FIG. 1 shows upper end of gate contact plug 113 [the second end of the gate wiring] level with upper surface of interlevel dielectric (ILD) layer 123, and available to connect to additional wiring, Wu does not explicitly teach: a second end of the gate wiring is connected to a first gate bus bar.
However, Yamamoto, in the same field of endeavor, teaches that the gate wiring includes a gate pad portion 18A [analogous to the bottom end of gate contact plug 113 of Wu, i.e., the first end of the gate wiring] and a gate bus connection portion 18B [the second end of the gate wiring connected to the gate bus] (Yamamoto, see FIGs. 11-13, [0181]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu with the teachings of Yamamoto, arriving at Applicant’s claimed second end of the gate wiring is connected to a first gate bus bar with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Yamamoto, to provide connection to the gate electrodes, while reducing distance between the gate electrode and the source electrode, thereby enhancing voltage resistance (Yamamoto, [0188]), resulting in improved device performance and reliability.
Regarding claim 2, Wu in view of Yamamoto teaches: The semiconductor device according to claim 1, wherein the gate electrode is provided in a loop shape on the substrate (Wu, FIG. 3 shows gate electrode 109A [the gate electrode] provided in a loop shape on semiconductor substrate 143 [the substrate], “the loop-shaped gate electrode 109A is cylindrical,” [0029]).
Regarding claim 3, Wu in view of Yamamoto teaches: The semiconductor device according to claim 1, wherein the drain electrode is provided on the substrate and surrounds the gate electrode in a first direction, a direction opposite to the first direction, and a second direction intersecting the first direction (Wu, FIGs. 1, 3 show drain region 127 [the drain electrode] provided on semiconductor substrate 143 [the substrate] and surrounding gate electrode 109A [the gate electrode] in the positive X-direction [the first direction], the negative X-direction [the direction opposite to the first direction], and in the negative Y-direction [the second direction intersecting the first direction], [0024]).
Regarding claim 4, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, wherein the drain electrode surrounds the gate electrode only from the first direction, the direction opposite to the first direction, and the second direction (Yamamoto, FIG. 13 shows the drain electrode as drain electrode 7 and drain branch-shaped portion 17C [0186-0187], surrounding gate electrode 8 [the gate electrode] only on three sides, only in the positive X-direction [the first direction], the negative X-direction [the direction opposite to the first direction], and in the negative Y-direction [the second direction intersecting the first direction], [0179-0180]).
Regarding claim 5, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, wherein the first end of the gate wiring (Yamamoto, FIG. 9, gate pad portion 18A) is connected to a portion of the gate electrode not surrounded by the drain electrode in a direction opposite to the second direction (Yamamoto, FIG. 9 shows gate pad portion 18A [the first end of the gate wiring] connected to upper portion of gate bus connection portion 18B [the portion of the gate electrode not surrounded by the drain electrode] in the positive Y-direction [the direction opposite to the second direction], [0181]),
Although Wu in view of Yamamoto teaches that the width of the gate bus connection portion 18B has different width in the X-direction than in the Y-direction (Yamamoto, FIG. 9 and associated text), Wu in view of Yamamoto does not explicitly teach that the portion of the gate electrode not surrounded by the drain electrode having a width of 1/2 of a width of the portion in the first direction with a center point in the first direction. However, given the teachings of Wu and Yamamoto, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to try the limited structural variations in width of the gate electrode in order to arrive at Applicant’s claimed portion of the gate electrode not surrounded by the drain electrode having a width of 1/2 of a width of the portion in the first direction with a center point in the first direction with a high likelihood of success and without undue experimentation. Furthermore, because Applicant’s specification does not indicate that the claimed range of width is critical or unexpected, the selection of an appropriate width would be an obvious matter of design choice for one of ordinary skill (MPEP 2144.04).
Regarding claim 6, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, wherein the drain electrode surrounds the gate electrode from a direction opposite to the second direction (Wu, FIGs. 1, 3 show drain region 127 [the drain electrode] surrounding gate electrode 109A [the gate electrode] in at least four directions, including from the positive Y-direction [the direction opposite to the second direction], [0024]; Yamamoto, see FIG. 12).
Regarding claim 7, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, however Wu in view of Yamamoto does not explicitly teach: wherein a width of the source electrode in the second direction is not more than three times and not less than one third times the width of the source electrode in the first direction. However, as discussed above, because Applicant’s specification does not indicate that the claimed range of width is critical or unexpected, the selection of an appropriate width would be an obvious matter of design choice for a person having ordinary skill in the art (MPEP 2144.04).
Regarding claim 9, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, wherein the substrate (Wu, FIGs. 1, 3, semiconductor substrate 143; Yamamoto, substrate 101) has an active region in which a semiconductor layer in the substrate is activated (Wu, FIG. 1, GAA transistor 125A including N-doped and P-doped [activated] regions, [0024-0026]; Yamamoto, FIGs. 9-13, “element region DR is an active region that contributes to the operation of the device by movement of electrons,” [0178]), and a region of the drain electrode surrounding the gate electrode in the first direction, the direction opposite to the first direction, and the second direction is provided on the active region (Wu, FIGs. 1, 3 show drain region 127 [the drain electrode] surrounding gate electrode 109A [the gate electrode] in the positive X-direction [the first direction], the negative X-direction [the direction opposite to the first direction], and in the negative Y-direction [the second direction intersecting the first direction] provided on N+ doped drain region, [0026]; Yamamoto, FIGs. 9-13 show drain electrode 7 [the drain electrode] provided on element region DR [the active region] and surrounding gate electrode 8 [the gate electrode]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Yamamoto and further in view of Hill, US 2020/0118922 A1 (hereinafter Hill).
Regarding claim 8, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, however Wu in view of Yamamoto is silent regarding: a metal layer provided under the substrate and electrically connected to the source electrode via a via hole penetrating the substrate.
However, Hill, in the same field of endeavor, teaches: a metal layer provided under the substrate (Hill, FIG. 5 shows ground plane 116 [the metal layer] under substrate 82 [the substrate], [0029]) and electrically connected to the source electrode via a via hole penetrating the substrate (Hill, FIG. 5, “via connections 108, 112 extend through substrate 82 and thus serve to connect source fingers 92 to a common node (e.g., a ground plane 116 visible in FIG. 5) on a lower surface 118 of substrate 82,” [0029]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu in view of Yamamoto with the teachings of Hill, arriving at Applicant’s claimed metal layer provided under the substrate and electrically connected to the source electrode via a via hole penetrating the substrate with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Hill, to provide electrical connection between the source and a common node, thereby providing for device functionality.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Yamamoto and further in view of Kosaka, US 2011/0084341 A1 (hereinafter Kosaka).
Regarding claim 10, Wu in view of Yamamoto teaches: The semiconductor device according to claim 3, however Wu in view of Yamamoto does not explicitly teach: FET groups each including a plurality of unit FETs arranged in the first direction, each of the unit FETs including the source electrode, the gate electrode, and the drain electrode, and adjacent ones of the unit FETs sharing the drain electrode; and
a drain bus bar to which drain electrodes of a plurality of unit FETs in a first FET group among the FET groups are connected, the first FET group being interposed between the first gate bus bar and the drain bus bar,
the first gate bus bar being connected to gate wirings of the plurality of unit FETs in the first FET group.
However, Kosaka, in the same field of endeavor, teaches: FET groups each including a plurality of unit FETs arranged in the first direction (Kosaka, FIG. 4a shows multiple unit FETs 20, [0029]), each of the unit FETs including the source electrode, the gate electrode, and the drain electrode (Kosaka, FIG. 4a, “a unit FET 20 having a source finger 22 [the source electrode], a drain finger 26 [the drain electrode] and a gate finger 24 [the gate electrode],” [0029]), and adjacent ones of the unit FETs sharing the drain electrode (Kosaka, FIG. 4a shows adjacent unit FETs 20 [the unit FETs] electrically sharing drain finger 26 [the drain electrode]); and
a drain bus bar to which drain electrodes of a plurality of unit FETs in a first FET group among the FET groups are connected (Kosaka, FIG. 4a, drain pad 27 [the drain bus bar] shown connected to a plurality of unit FETs 20 [the plurality of unit FETs] by drain fingers 26 [the drain electrode], [0030]), the first FET group being interposed between the first gate bus bar and the drain bus bar (Kosaka, FIG. 4a shows multiple unit FETs 20 [the first FET group] interposed between gate bus bar 28 [the first gate bus bar] and drain pad 27 [the drain bus bar]),
the first gate bus bar being connected to gate wirings of the plurality of unit FETs in the first FET group (Kosaka, FIG. 4a shows multiple unit FETs 20 [the first FET group] connected to gate bus bar 28 [the first gate bus bar] by gate fingers 24 [connected to the gate wirings].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu in view of Yamamoto with the teachings of Kosaka, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kosaka, to reduce the number of required via holes (Kosaka, [0035]), thereby improving manufacturing efficiency and device reliability.
Regarding claim 11, Wu in view of Yamamoto and further in view of Kosaka teaches: The semiconductor device according to claim 10, however Wu in view of Yamamoto and further in view of Kosaka does not explicitly teach: a second FET group included in the FET groups, the drain bus bar being interposed between the first FET group and the second FET group; and a second gate bus bar connected to a plurality of unit FETs included in the second FET group interposed between the drain bus bar and the second gate bus bar. However, absent a showing of new or unexpected results, mere duplication of parts, as with Applicant’s claimed second FET group included in the FET groups, the drain bus bar being interposed between the first FET group and the second FET group; and a second gate bus bar connected to a plurality of unit FETs included in the second FET group interposed between the drain bus bar and the second gate bus bar, is a common practice requiring only ordinary skill in the art and has no patentable significance absent a showing of new and unexpected results, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.
Regarding claim 12, Wu in view of Yamamoto and further in view of Kosaka teaches: The semiconductor device according to claim 11, however Wu in view of Yamamoto and further in view of Kosaka does not explicitly teach: wherein a width of the drain bus bar in the second direction is larger than a width of the drain electrode shared by the unit FETs adjacent to each other in the first direction. However, as discussed above, because Applicant’s specification does not indicate that the claimed range of width is critical or unexpected, the selection of an appropriate width would be an obvious matter of design choice (MPEP 2144.04).
Regarding claim 13, Wu in view of Yamamoto and further in view of Kosaka teaches: The semiconductor device according to claim 11, further comprising: a gate pad electrically connecting the first gate bus bar and the second gate bus bar (Yamamoto, FIG. 9, gate bus connecting portion 18B [the gate pad] shown electrically connected to “a plurality of gate electrodes 8 [the first gate bus bar and the second gate bus bar] extend in the shape of branches parallel to each other, from the gate bus connection portion 18B toward the element region DR,” [0191]; and a drain pad electrically connected to the drain bus bar (Yamamoto, FIG. 9, drain pad portion 17A [the drain pad] electrically connected to “a plurality of drain bus connection portions 17B [the drain bus bar] that extend from the drain pad portion 17A parallel to each other,” [0179]), the first FET group and the second FET group being interposed between the drain pad and the gate pad (Kosaka, FIG. 4a shows multiple unit FETs 20 [the first FET group] interposed between gate bus bar 28 [the first gate bus bar] and drain pad 27 [the drain bus bar]). As discussed above, absent a showing of new or unexpected results, mere duplication of parts, as with Applicant’s claimed the second FET group being interposed between the drain pad and the gate pad, is a common practice requiring only ordinary skill in the art and has no patentable significance absent a showing of new and unexpected results, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.
Regarding claim 14, Wu in view of Yamamoto and further in view of Kosaka teaches: The semiconductor device according to claim 11, however Wu in view of Yamamoto and further in view of Kosaka does not explicitly teach: a plurality of unit arranged in the second direction, each of the plurality of units including the first FET group, the second FET group, the drain bus bar, the first gate bus bar, and the second gate bus bar. However, as discussed above, absent a showing of new or unexpected results, mere duplication of parts, as with Applicant’s claimed a plurality of unit arranged in the second direction, each of the plurality of units including the first FET group, the second FET group, the drain bus bar, the first gate bus bar, and the second gate bus bar, is a common practice requiring only ordinary skill in the art and has no patentable significance absent a showing of new and unexpected results, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.
Conclusion
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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