Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 8, 2026 is being considered by the examiner.
Priority
Acknowledgement is made to claim of priority to Chinese Application No. 202311270850.9, filed on September 27, 2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1-16 are objected to because of the following informalities:
In claim 1, the phrases “comprising opposed a first surface and a second surface” and “comprising opposed a back surface and a functional surface” are not grammatically correct. The Examiner suggests rewording to for example “comprising a first surface and a second surface that is opposite to the first surface” and “comprising a back surface and a functional surface that is opposite to the back surface.”
In claim 9, the phrases “comprising opposed a first surface and a second surface” and “comprising opposed a back surface and a functional surface” are not grammatically correct. The Examiner suggests rewording to for example “comprising a first surface and a second surface that is opposite to the first surface” and “comprising a back surface and a functional surface that is opposite to the back surface.”
Dependent claims 2-8 and 10-16 are objected to at least on the same basis as the independent claims from which they depend.
Appropriate correction is required.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin (CN 115513154 A).
With respect to claim 17, Jin teaches in Fig. 1:
A packaging structure, comprising:
a semiconductor temperature control device (thermoelectric module 140) comprising a first columnar electrode (positive electrode column 131) and a second columnar electrode (negative electrode column 132) protruding on a first surface (bottom) of the semiconductor temperature control device (140);
a semiconductor chip (chip 120) comprising an external terminal (microbumps 230) on a first surface (bottom) of the semiconductor chip (120) that is opposite to a second surface (top) of the semiconductor chip (120) mounted on the first surface (bottom) of the semiconductor temperature control device (140);
a molding layer (packaging layers 190 and 210) covering the semiconductor chip (120) and the semiconductor temperature control device (140) and exposing the first columnar electrode (131), the second columnar electrode (132), and the external terminal (230);
and a first external connection protrusion disposed on the molding layer and electrically connected to the first columnar electrode, a second external connection protrusion disposed on the molding layer and electrically connected to the second columnar electrode, and a third external connection protrusion disposed on the molding layer and electrically connected to the external terminal. (see annotated Fig. 1 below, external connection protrusions are identified with traces connected to 132, 131, and 230 within wiring layer 110).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-10, 13-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jin (CN 115513154 A) in view of Eid (US 2021/0043573 A1).
With respect to claim 1, Jin teaches in Fig. 1:
A method for forming a packaging structure, comprising:
providing a semiconductor temperature control device (thermoelectric module 140), the semiconductor temperature control device comprising opposed a first surface (bottom) and a second surface (top), with a first columnar electrode (positive conductive post 131) and a second columnar electrode (negative conductive post 132) protruding on the first surface;
providing a semiconductor chip (chip 120), the semiconductor chip comprising opposed a back surface (top) and a functional surface (bottom), with an external terminal being on the functional surface (microbump 230);
mounting the back surface (top) of the semiconductor chip (120) on the first surface (bottom) of the semiconductor temperature control device (140);
forming a molding layer (first packaging layer 190 and second packaging layer 210) covering the semiconductor chip (120) and the semiconductor temperature control device (140), the molding layer exposing top surfaces of the first columnar electrode (131), the second columnar electrode (132), and the external terminal (230);
and forming, on the molding layer, a first external connection protrusion electrically connected to the first columnar electrode, a second external connection protrusion electrically connected to the second columnar electrode, and a third external connection protrusion electrically connected to the external terminal (see annotated Fig. 1 above, external connection protrusions are identified with traces connected to 132, 131, and 230 within wiring layer 110).
Jin fails to teach:
providing a substrate;
mounting the second surface of the semiconductor temperature control device on an upper surface of the substrate;
forming, on the upper surface of the substrate, a molding layer
Eid teaches in Fig. 10:
providing a substrate (heat spreader 114);
mounting the second surface (top) of the semiconductor temperature control device (122) on an upper surface of the substrate (bottom surface of 114);
forming, on the upper surface of the substrate, a molding layer (mold compound 112)
Jin discloses the claimed invention except for the substrate attacked to a side of the temperature control device. Eid teaches that it is known to attach a substrate to the side of the temperature control device opposite the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to attach the temperature control device to a substrate as taught by Eid for the purpose of drawing heat away from the temperature control device and chip. See MPEP 2144.
With respect to claim 2, Jin further teaches:
wherein the first external connection protrusion and the second external connection protrusion are configured to be electrically connected with positive and negative electrodes of a direct current (DC) power source,
so that the semiconductor temperature control device operates to absorb heat generated by the semiconductor chip, and the semiconductor temperature control device forms a cold end and a hot end during operation,
with the cold end being an end close to the first surface and the hot end being another end close to the second surface. (“In the application embodiment, the thermoelectric module 140 is set on one side of the chip 120 away from the wiring layer 110 by means of stacking, wiring layer 110 through at least two conductive posts 130 electrically connected with the thermoelectric module 140, so as to transmit current to the thermoelectric module 140, the thermoelectric module 140 of the two ends of the temperature gradient, so as to form the cold end 148 and heat end 149, wherein the thermoelectric module 140 of the cold end 148 and the chip 120 are oppositely set, the chip 120 works when the heat generated by the thermoelectric module 140 of cold end 148, to realize the purpose of cooling the chip 120.”)
With respect to claim 5, Jin further teaches:
wherein the semiconductor chip (120) is mounted on the first surface (bottom) of the semiconductor temperature control device (140) between the first columnar electrode (131) and the second columnar electrode (132), or mounted on the first surface of the semiconductor temperature control device on a side of the first columnar electrode and the second columnar electrode.
With respect to claim 6, Jin further teaches:
wherein, after the back surface of the semiconductor chip (120) is mounted on the first surface (bottom) of the semiconductor temperature control device (140), a top surface of the external terminal (bottom surface of 230) on the functional surface (bottom) of the semiconductor chip (120) is flush with the top surfaces (bottom surfaces) of the first columnar electrode (131) and the second columnar electrode (132) protruding on the first surface of the semiconductor temperature control device (140). (see Fig. 1)
With respect to claim 7, Jin further teaches:
forming, on the molding layer (190), a first redistribution layer electrically connected to the first columnar electrode (circuitry within 110 connected to the first protrusion as defined in annotated Fig. 1 above), a second redistribution layer electrically connected to the second columnar electrode (circuitry within 110 connected to the second protrusion as defined in annotated Fig. 1 above), and a third redistribution layer electrically connected to the external terminal, wherein the first external connection protrusion is disposed on the first redistribution layer and electrically connected to the first redistribution layer (circuitry within 110 connected to the third protrusion as defined in annotated Fig. 1 above), the second external connection protrusion is disposed on the second redistribution layer and electrically connected to the second redistribution layer, and the third external connection protrusion is disposed on the third redistribution layer and electrically connected to the third redistribution layer.
With respect to claim 8, Eid further teaches in Fig. 43:
wherein the substrate comprises a plurality of packaging areas (dies 1502) arranged in an array (see Fig. 43), and a sawing street area disposed between adjacent packaging areas (lines between individual 1502 that are separated in the singulation process);
Eid further teaches that the singulation process of Fig. 43 may be used with any of the temperature control packages of Eid. It would be obvious to use the teaching to form multiple ICs on a wafer prior to singulating to the packaging structure of Jin/Eid teach:
the semiconductor temperature control device (140 of Jin, analogous to 122 of Eid) and semiconductor chip (120 of Jin, analogous to 106 of Eid) are mounted correspondingly on the upper surface of each packaging area; the molding layer further covers the upper surface of the sawing street area of the substrate; and after forming the first external connection protrusion, the second external connection protrusion, and the third external connection protrusion, the molding layer and the substrate are diced along the sawing street area to form a plurality of discrete packages.
It would be obvious to the ordinary artisan to modify Jin/Eid with the teaching of Eid to form multiple ICs in a single wafer before singulation for the purpose of improving efficiency of manufacturing processes.
With respect to claim 9, Jin teaches:
A packaging structure, comprising:
a semiconductor temperature control device (thermoelectric module 140), the semiconductor temperature control device comprising opposed a first surface (bottom) and a second surface (top), with a first columnar electrode (positive electrode column 131) and a second columnar electrode (negative electrode column 132) protruding on the first surface,
a semiconductor chip (chip 120), the semiconductor chip comprising opposed a back surface (top) and a functional surface (bottom), with an external terminal being on the functional surface (microbumps 230), the back surface of the semiconductor chip being mounted on the first surface of the semiconductor temperature control device (140);
a molding layer (first packaging layer 190 and second packaging layer 210) covering the semiconductor chip (120) and the semiconductor temperature control device, the molding layer exposing top surfaces of the first columnar electrode, the second columnar electrode, and the external terminal;
and a first external connection protrusion disposed on the molding layer and electrically connected to the first columnar electrode, a second external connection protrusion disposed on the molding layer and electrically connected to the second columnar electrode, and a third external connection protrusion disposed on the molding layer and electrically connected to the external terminal.
(see annotated Fig. 1 above, external connection protrusions are identified with traces connected to 132, 131, and 230 within wiring layer 110).
Jin fails to teach:
a substrate;
the second surface of the semiconductor temperature control device being mounted on an upper surface of the substrate;
a molding layer disposed on the upper surface of the substrate
Eid teaches in Fig. 10:
a substrate (heat spreader 114);
the second surface (top) of the semiconductor temperature control device (122) mounted on an upper surface of the substrate (bottom surface of 114);
a molding layer disposed on the upper surface of the substrate (mold compound 112)
Jin discloses the claimed invention except for the substrate attacked to a side of the temperature control device. Eid teaches that it is known to attach a substrate to the side of the temperature control device opposite the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to attach the temperature control device to a substrate as taught by Eid for the purpose of drawing heat away from the temperature control device and chip. See MPEP 2144.
With respect to claim 10, Jin further teaches:
wherein the first external connection protrusion (131) and the second external connection protrusion (132) are configured to be electrically connected with positive and negative electrodes of a direct connect (DC) power source, so that the semiconductor temperature control device operates to absorb heat generated by the semiconductor chip, and the semiconductor temperature control device forms a cold end and a hot end during operation, with the cold end being an end close to the first surface and the hot end being another end close to the second surface. (“In the application embodiment, the thermoelectric module 140 is set on one side of the chip 120 away from the wiring layer 110 by means of stacking, wiring layer 110 through at least two conductive posts 130 electrically connected with the thermoelectric module 140, so as to transmit current to the thermoelectric module 140, the thermoelectric module 140 of the two ends of the temperature gradient, so as to form the cold end 148 and heat end 149, wherein the thermoelectric module 140 of the cold end 148 and the chip 120 are oppositely set, the chip 120 works when the heat generated by the thermoelectric module 140 of cold end 148, to realize the purpose of cooling the chip 120.”)
With respect to claim 13, Jin further teaches:
wherein the semiconductor chip (120) is mounted on the first surface (bottom) of the semiconductor temperature control device (140) between the first columnar electrode (131) and the second columnar electrode (132), or mounted on the first surface of the semiconductor temperature control device on a side of the first columnar electrode and the second columnar electrode.
With respect to claim 14, Jin further teaches:
wherein a top surface of the external terminal (bottom surface of 230) on the functional surface (bottom) of the semiconductor chip (120) is flush with the top surfaces (bottom surfaces) of the first columnar electrode (131) and the second columnar electrode (132) protruding on the first surface of the semiconductor temperature control device (140). (see Fig. 1)
With respect to claim 15, Jin further teaches:
further comprising: a first redistribution layer on the molding layer (190), and electrically connected to the first columnar electrode (circuitry within 110 connected to the first protrusion as defined in annotated Fig. 1 above), a second redistribution layer on the molding layer and electrically connected to the second columnar electrode (circuitry within 110 connected to the second protrusion as defined in annotated Fig. 1 above), and a third redistribution layer on the molding layer and electrically connected to the external terminal, wherein the first external connection protrusion is disposed on the first redistribution layer and electrically connected to the first redistribution layer (circuitry within 110 connected to the third protrusion as defined in annotated Fig. 1 above), the second external connection protrusion is disposed on the second redistribution layer and electrically connected to the second redistribution layer, and the third external connection protrusion is disposed on the third redistribution layer and electrically connected to the third redistribution layer.
With respect to claim 16, Jin further teaches:
wherein the external terminal (230) is a metal pillar (microbump) protruding from the functional surface (bottom) of the semiconductor chip (120) or an external solder pad disposed on the functional surface of the semiconductor chip.
With respect to claim 18, Jin teaches all limitations of claim 17 upon which claim 18 depends. Jin fails to teach:
further comprising: a substrate,
wherein a second surface of the semiconductor temperature control device that is opposite to the first surface of the semiconductor temperature control device is mounted to the substrate.
Eid teaches in Fig. 10:
further comprising: a substrate (heat spreader 114);
wherein a second surface (top) of the semiconductor temperature control device (122) that is opposite to the first surface (bottom) of the semiconductor temperature control device (122) mounted on an upper surface of the substrate (bottom surface of 114);
Jin discloses the claimed invention except for the substrate attacked to a side of the temperature control device. Eid teaches that it is known to attach a substrate to the side of the temperature control device opposite the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to attach the temperature control device to a substrate as taught by Eid for the purpose of drawing heat away from the temperature control device and chip. See MPEP 2144.
With respect to claim 19, Jin further teaches:
wherein the first external connection protrusion (131) and the second external connection protrusion (132) are configured to be electrically connected with positive and negative electrodes of a direct connect (DC) power source,
so that the semiconductor temperature control device operates to absorb heat generated by the semiconductor chip,
and the semiconductor temperature control device forms a cold end and a hot end during operation, with the cold end being an end close to the first surface and the hot end being another end close to the second surface. (“In the application embodiment, the thermoelectric module 140 is set on one side of the chip 120 away from the wiring layer 110 by means of stacking, wiring layer 110 through at least two conductive posts 130 electrically connected with the thermoelectric module 140, so as to transmit current to the thermoelectric module 140, the thermoelectric module 140 of the two ends of the temperature gradient, so as to form the cold end 148 and heat end 149, wherein the thermoelectric module 140 of the cold end 148 and the chip 120 are oppositely set, the chip 120 works when the heat generated by the thermoelectric module 140 of cold end 148, to realize the purpose of cooling the chip 120.”)
Claims 3-4 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jin (CN 115513154 A) in view of Eid (US 2021/0043573 A1) and Lee (US 2024/0332127 A1).
With respect to claim 3, Jin/Eid teach all limitations of claim 1 upon which claim 3 depends. Jin further teaches:
wherein the semiconductor temperature control device comprises: a plurality of N-type semiconductors (N-semiconductors 144) and a plurality of P-type semiconductors (P-semiconductors 143) arranged in a staggered manner and connected in series (connected through connecting piece 145);
Jin/Eid fails to teach:
a top layer ceramic substrate disposed on top surface of the plurality of N-type semiconductors and the plurality of P-type semiconductors; and a bottom layer ceramic substrate disposed on bottom surface of the plurality of N-type semiconductors and the plurality of P-type semiconductors;
and the first columnar electrode and the second columnar electrode protrude on a surface of the top layer ceramic substrate, and are electrically connected to one N-type semiconductor and one P-type semiconductor at both ends of the plurality of N-type semiconductors and the plurality of P-type semiconductors connected in series.
Lee teaches in Figs. 1 and 5A:
a top layer ceramic substrate (plate 210 which may be ceramic [0020]) disposed on top surface of the plurality of N-type semiconductors (206N) and the plurality of P-type semiconductors (206P); and a bottom layer ceramic substrate (plate 220 which may be ceramic [0020]) disposed on bottom surface of the plurality of N-type semiconductors (206N) and the plurality of P-type semiconductors (206P);
and the first columnar electrode (conductive traces 516 connected to N) and the second columnar electrode (conductive trace 516 connected to P) protrude on a surface of the top layer ceramic substrate, and are electrically connected to one N-type semiconductor and one P-type semiconductor at both ends of the plurality of N-type semiconductors and the plurality of P-type semiconductors connected in series (see Fig. 5A).
Jin/Eid discloses the claimed invention except for the ceramic substrates on either side of the N-type and P-type semiconductors in the temperature control module. Lee teaches that it is known to include ceramic substrates on both sides of the temperature control module. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Jin/Eid as taught by Lee for the purpose of improving heat dissipation within the device (para. [0020]). See MPEP 2144.
With respect to claim 4, Lee further teaches in Fig. 4:
wherein the back surface of the semiconductor chip (die 406) is mounted to the surface of the top layer ceramic substrate (thermally conductive plate 408c, equivalent to 220 of Fig. 1) of the semiconductor temperature control device by a thermal conductive adhesive.
Jin/Eid modified by Lee above discloses the claimed invention except for the thermal adhesive between the chip and the ceramic substrate. Lee teaches that it is known include a thermal conductive adhesive between the ceramic substrate and the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Jin/Eid as taught by Lee for the purpose of improving heat dissipation within the device (para. [0020]). See MPEP 2144.
With respect to claim 11, Jin/Eid teach all limitations of claim 9 upon which claim 11 depends. Jin further teaches:
wherein the semiconductor temperature control device comprises: a plurality of N-type semiconductors (N-semiconductors 144) and a plurality of P-type semiconductors (P-semiconductors 143) arranged in a staggered manner and connected in series (connected through connecting piece 145);
Jin/Eid fails to teach:
a top layer ceramic substrate disposed on top surface of the plurality of N-type semiconductors and the plurality of P-type semiconductors; and a bottom layer ceramic substrate disposed on bottom surface of the plurality of N-type semiconductors and the plurality of P-type semiconductors;
and the first columnar electrode and the second columnar electrode protrude on a surface of the top layer ceramic substrate, and are electrically connected to one N-type semiconductor and one P-type semiconductor at both ends of the plurality of N-type semiconductors and the plurality of P-type semiconductors connected in series.
Lee teaches in Figs. 1 and 5A:
a top layer ceramic substrate (plate 210 which may be ceramic [0020]) disposed on top surface of the plurality of N-type semiconductors (206N) and the plurality of P-type semiconductors (206P); and a bottom layer ceramic substrate (plate 220 which may be ceramic [0020]) disposed on bottom surface of the plurality of N-type semiconductors (206N) and the plurality of P-type semiconductors (206P);
and the first columnar electrode (conductive traces 516 connected to N) and the second columnar electrode (conductive trace 516 connected to P) protrude on a surface of the top layer ceramic substrate, and are electrically connected to one N-type semiconductor and one P-type semiconductor at both ends of the plurality of N-type semiconductors and the plurality of P-type semiconductors connected in series (see Fig. 5A).
Jin/Eid discloses the claimed invention except for the ceramic substrates on either side of the N-type and P-type semiconductors in the temperature control module. Lee teaches that it is known to include ceramic substrates on both sides of the temperature control module. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Jin/Eid as taught by Lee for the purpose of improving heat dissipation within the device (para. [0020]). See MPEP 2144.
With respect to claim 12, Lee further teaches:
wherein the back surface of the semiconductor chip (die 406) is mounted to the surface of the top layer ceramic substrate (thermally conductive plate 408c, equivalent to 220 of Fig. 1) of the semiconductor temperature control device by a thermal conductive adhesive.
Jin/Eid modified by Lee above discloses the claimed invention except for the thermal adhesive between the chip and the ceramic substrate. Lee teaches that it is known include a thermal conductive adhesive between the ceramic substrate and the chip. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Jin/Eid as taught by Lee for the purpose of improving heat dissipation within the device (para. [0020]). See MPEP 2144.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jin (CN 115513154 A) as applied to claim 17 above and in view Lee (US 2024/0332127 A1).
With respect to claim 20, Jin teaches all limitations of claim 17 upon which claim 20 depends. Jin fails to teach:
wherein the semiconductor chip comprises a high bandwidth memory (HBM).
Lee teaches:
wherein the semiconductor chip (die 406) comprises a high bandwidth memory (HBM) ([0022] “the die 406 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM)”).
Jin discloses the claimed invention except for the die comprising high bandwidth memory. Lee teaches that it is known to include a HBM die as the die that is cooled by a temperature control component. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Jin as taught by Lee for the purpose of removing heat generated by a memory chip. See MPEP 2144.
Conclusion
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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