DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 08/25/2026.
Currently claims 1-18 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-13, in the reply filed on 08/25/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/22/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 8-13 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 5, the claim first recites “a lowermost part of an upper surface of the recessed portion,” but Equation 1 then defines H as the distance from “the lowermost part of the recessed portion.” There is insufficient antecedent basis for “the lowermost part of the recessed portion,” and it is unclear whether H is measured from the lowermost point of the upper surface of the recessed portion or from some other lowermost part of the recessed portion. For examination, H is interpreted as the distance from the lowermost point of the upper surface of the recessed portion to the first and/or second gate insulating film. Correction is required.
Regarding claim 8, the claim recites “a drift region disposed on a first side of the substrate” and “a body region disposed on a second side of the substrate.” A substrate has opposing major surfaces (front and back sides), and it is unclear whether the “first side” and “second side” denote the opposing major surfaces of the substrate or laterally separated portions of the same (upper) surface; the latter appears to be intended. For examination, the “first side” and “second side” are interpreted as laterally separated portions of the substrate. Claims 9-13 are rejected as depending from claim 8. Clarification is required.
Regarding claim 9, claim 8 defines the recessed portion by “an upper surface of the connection part”; the recessed portion has no separately defined bottom surface distinct from the lowermost part of that upper surface. The claimed distance “from the lowermost part of an upper surface of the recessed portion to a bottom surface of the recessed portion” is therefore either zero or indeterminate. For examination, claim 9 is interpreted as reciting the distance from the lowermost part of the upper surface of the recessed portion to the bottom surface of the connection part. Correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 7 are rejected under 35 U.S.C. 102 (a) (1) as anticipated by US 2016/0351706 A1 (Jung).
Regarding claim 1, Jung teaches, a high voltage semiconductor device (100; high voltage semiconductor device; Fig. 2; [0052] – [0053]) comprising: a substrate (102; substrate; Fig. 2; [0052] - [0053]);
a drift region (122; second drift region; Fig. 2; [0052], [0054]) disposed within the substrate (102);
a body region (WELL; well region; Fig. 2; [0053] – [0054]) disposed within the substrate (102);
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a drain region (132; drain region; Fig. 2; [0052]) disposed within the drift region (122);
a source region (130; source region; Fig. 2; [0052] - [0053]) disposed within the body region (WELL);
a gate region (110; gate structure; Fig. 2; [0052], [0055]) disposed on the substrate (102);
a dummy gate region (140; first electrode structure; Jung Fig. 2; [0052], [0057], [0059]) having a side connected to the gate region (110) disposed on the substrate (102).
Regarding claim 2, Jung teaches, the device of claim 1, wherein the gate region (110) comprises:
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a first gate insulating film (112; gate insulating layer; Jung Fig. 2; [0055]) disposed on the substrate (102);
a first gate electrode (114; gate electrode; Jung Fig. 2; [0055]) disposed on the first gate insulating film (112);
a first gate spacer (116; gate spacer; Jung Fig. 2; [0057]) disposed on a sidewall of the first gate electrode (114);
wherein the dummy gate region (140) comprises:
a second gate insulating film (142; first insulating layer pattern; Jung Fig. 2; [0055]) disposed on the substrate (102);
a second gate electrode (144; first electrode pattern; Jung Fig. 2; [0055]) disposed on the second gate insulating film (142);
a second gate spacer (146; first electrode spacer; Jung Fig. 2; [0057]) disposed on a sidewall of the second gate electrode (144).
Regarding claim 3, Jung teaches, the device of claim 2, wherein:
“the first gate spacer comprises a first inner gate spacer on a side adjacent to the dummy gate region,” which is the portion of Jung’s gate spacer on the side of the gate structure 110 facing the first electrode structure 140 (116; gate spacer; Jung Fig. 2; [0057]).
“whereas the second gate spacer comprises a second inner gate spacer on a side adjacent to the gate region,” which is the portion of Jung’s first electrode spacer facing the gate structure 110 (146; first electrode spacer; Jung Fig. 2; [0057]).
“wherein the first inner gate spacer is physically connected to the second inner gate spacer to form a connection part.” in that the space between the gate structure 110 and the first electrode structure 140 is filled up with the gate spacer 116 and the first electrode spacer 146, which meet to form a single connected spacer fill (116/146; gate spacer / first electrode spacer filling the space between gate structure 110 and first electrode structure 140; Jung Figs. 2, 15; [0057], [0082]).
Regarding claim 4, Jung teaches, the device of claim 3, wherein:
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“the connection part has a recessed portion defined by an upper surface of the connection part extending from the first gate electrode and the second gate electrode toward a center of the connection part.” in that Jung Fig. 2 depicts the upper surface of the spacer fill between gate electrode 114 and first electrode pattern 144 sloping downward from the top of each electrode to a V-shaped low point at the center of the fill (116/146; gate spacer / first electrode spacer fill; Jung Fig. 2; [0057]). Drawings may be relied upon for what they reasonably disclose and suggest to one of ordinary skill in the art (MPEP 2125).
Regarding claim 7, Jung teaches, the device of claim 4, further comprising: a silicide film disposed on the drain region, the source region, the first gate electrode, and the second gate electrode (metal (e.g., titanium) silicides are formed on the gate electrode 114, the source and drain regions 130 and 132, and the electrode patterns 144 and 154 (metal silicide; Jung Fig. 16; [0085]).
Claims 8 and 12 are rejected under 35 U.S.C. 102 (a) (1) as anticipated by US 2016/0351706 A1 (Jung).
Regarding claim 8, as best understood in view of the 112(b) rejection above, Jung teaches,
a high voltage semiconductor device (100; high voltage semiconductor device; Fig. 2; [0052] – [0053]) comprising:
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a substrate (102; substrate; Fig. 2; [0052] - [0053]);
a drift region (122; second drift region; Fig. 2; [0052], [0054]) disposed within the substrate (102);
a body region (WELL; well region; Fig. 2; [0053] – [0054]) disposed within the substrate (102);
a drain region (132; drain region; Fig. 2; [0052]) disposed within the drift region (122);
a source region (130; source region; Fig. 2; [0052] - [0053]) disposed within the body region (WELL);
a first gate electrode (114; gate electrode; Jung Fig. 2; [0055]) disposed on the substrate (102);
a second gate electrode (144; first electrode pattern; Jung Fig. 2; [0055]) disposed apart from the first gate electrode (114) on the substrate (102);
“a connection part filling a separation space between the first gate electrode and the second gate electrode on the substrate, the connection part including an insulating material,” in that the space between the gate structure 110 and the first electrode structure 140 is filled up with the gate spacer 116 and the first electrode spacer 146, which function as silicide blocking (insulating) layers (116/146; gate spacer / first electrode spacer fill; Jung Fig. 2; [0057]–[0058]).
“wherein the connection part has a recessed portion defined by an upper surface of the connection part extending from the first gate electrode and the second gate electrode toward a center of the separation space.” in that Jung Fig. 2 depicts the upper surface of the spacer fill sloping downward from the tops of gate electrode 114 and first electrode pattern 144 to a V-shaped low point at the center of the separation space (116/146; gate spacer / first electrode spacer fill; Jung Fig. 2; [0057]) (MPEP 2125).
Regarding claim 12, Jung teaches, the device of claim 8, wherein: the second gate electrode (144) is electrically connected to a source electrode (160) connected to the source region (130) (Figs. 2, 5; [0059], [0064]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as unpatentable over US 2016/0351706 A1 (Jung) and further in view of US 2023/0170417 A1 (Park).
Regarding claim 6, Jung teaches, the device of claim 4, including a low-concentration first drift region 120 in contact with the source region 130 ([0054]), but does not explicitly teach, an LDD region disposed within the body region;
However, in analogous art, Park teaches, an LDD region (136; LDD region (HV-NLDD); Fig. 2; [0016], [0065] – [0066]) in contact with the source region (132), the LDD region (136) being disposed within the body region (130).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jung and Park before him/her, because Park’s LDD region, formed by implantation self-aligned to the gate spacers without a separate mask, allows the body region width to be minimized and improves integration and on-resistance ([0013], [0037], [0055]). Absent this teaching in Jung, a person with ordinary skill in the art would be motivated to reach out to Park while forming the high voltage semiconductor device of Jung.
Claim 11 is rejected under 35 U.S.C. 103 as unpatentable over US 2016/0351706 A1 (Jung) and further in view of US 2023/0170417 A1 (Park).
Regarding claim 11, Jung does not explicitly teach, the high voltage semiconductor device of claim 8, further comprising: a body contact region contacting the source region within the body region.
However, in analogous art, Park teaches, a body contact region (134; body contact; Park Fig. 2; [0021], [0065]) contacting the source region (132) within the body region (130).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jung and Park before him/her, (1) because a heavily doped body contact abutting the source lets the body region be biased at the source potential through a common source/body electrode ([0065]), suppressing body-potential floating. Absent this teaching in Jung, a person with ordinary skill in the art would be motivated to reach out to Park while forming the high voltage semiconductor device of Jung.
Claim 13 is rejected under 35 U.S.C. 103 as unpatentable over US 2016/0351706 A1 (Jung) and further in view of US 2022/0216308 A1 (Lao).
Regarding claim 13, Jung does not explicitly teach, the high voltage semiconductor device of claim 8, further comprising: a gate field plate disposed between a bottom of the second gate electrode and the substrate.
However, in analogous art, Lao teaches, the high voltage semiconductor device of claim 8, further comprising: a gate field plate (601; insulating layer; Lao Fig. 5; [0036]–[0038]) disposed between a bottom of the second gate electrode (690) and the substrate (110).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jung and Lao before him/her, because placing a thicker insulating layer under the drift-side electrode forms field plates of different heights that reduce the surface field and increase breakdown voltage ([0038]). Absent this teaching in Jung, a person with ordinary skill in the art would be motivated to reach out to Lao while forming the high voltage semiconductor device of Jung.
Allowable Subject Matter
Claims 5 and 9-10 are objected to as being dependent upon rejected base claims but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims, and if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action.
Regarding claim 5, the closest prior art, US 2016/0351706 A1 (Jung), in conjunction with US 2023/0170417 A1 (Park) and US 2022/0216308 A1 (Lao), fails to disclose, “the high voltage semiconductor device of claim 4, wherein the recessed portion has a distance from a lowermost part of an upper surface of the recessed portion to the first gate insulating film and/or the second gate insulating film according to Equation 1:
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, wherein H denotes the distance from the lowermost part of the recessed portion to the first gate insulating film and/or the second gate insulating film, R denotes a top to bottom thickness of the first gate electrode or the second gate electrode, D denotes a distance between the first gate electrode and the second gate electrode”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the high voltage semiconductor device of claim 4, wherein the recessed portion has a distance from a lowermost part of an upper surface of the recessed portion to the first gate insulating film and/or the second gate insulating film according to Equation 1:
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, wherein H denotes the distance from the lowermost part of the recessed portion to the first gate insulating film and/or the second gate insulating film, R denotes a top to bottom thickness of the first gate electrode or the second gate electrode, D denotes a distance between the first gate electrode and the second gate electrode,’ is material to the inventive concept of the application at hand to solve the gap-exposure problem by physically connecting the inner spacers of the gate region and dummy gate region so the separation space is filled.
Regarding claim 9, the closest prior art, US 2016/0351706 A1 (Jung), in conjunction with US 2023/0170417 A1 (Park) and US 2022/0216308 A1 (Lao), fails to disclose, “the high voltage semiconductor device of claim 8, wherein the recessed portion has a distance from a lowermost part of an upper surface of the recessed portion to a bottom surface of the recessed portion that is greater than a depth from a surface of the substrate to a bottom of the drain region and/or the source region”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the high voltage semiconductor device of claim 8, wherein the recessed portion has a distance from a lowermost part of an upper surface of the recessed portion to a bottom surface of the recessed portion that is greater than a depth from a surface of the substrate to a bottom of the drain region and/or the source region,’ is material to the inventive concept of the application at hand to solve the gap-exposure problem by physically connecting the inner spacers of the gate region and dummy gate region so the separation space is filled.
Regarding claim 10, the closest prior art, US 2016/0351706 A1 (Jung), in conjunction with US 2023/0170417 A1 (Park) and US 2022/0216308 A1 (Lao), fails to disclose, “the high voltage semiconductor device of claim 8, wherein the connection part has a minimum thickness greater than a depth from a surface of the substrate to a bottom of the drain region and/or the source region”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the high voltage semiconductor device of claim 8, wherein the connection part has a minimum thickness greater than a depth from a surface of the substrate to a bottom of the drain region and/or the source region,’ is material to the inventive concept of the application at hand to solve the gap-exposure problem by physically connecting the inner spacers of the gate region and dummy gate region so the separation space is filled.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. US 2022/0367711 A1 (Lee) - A high voltage semiconductor device is disclosed that enables an improvement in the breakdown voltage relative to the on-resistance by forming a top region in or at the surface of the substrate when the device includes a field plate adjacent to a gate electrode.
3. US 2022/0285247 A1 (Song) - A high voltage semiconductor device is disclosed which is capable of improving the breakdown voltage characteristics in an off-state and in an on-state by electrically connecting a first source metal to a source in a core region and in corner regions.
3. US 2023/0253497 A1 (Chao) - A high voltage semiconductor device is disclosed including a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region.
4. US 2020/0373395 A1 (Ho) - An integrated chip is disclosed including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/08/2026
