Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 5-6, 9 and 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. No. 2024/0250134 A1), hereafter referred to as Chen, in view of Lai et al. (US Pub. No. 2023/0067311 A1), hereafter referred to as Lai.
As to claim 1, Chen discloses a multi-stack semiconductor device (fig 26A, 10), comprising:
a back-side power rail (110A) extending in a first horizontal direction (X-direction);
a first field effect transistor (GAA FET) at a level over the back-side power rail (110A); and
a back-side source/drain via rail (98A) between the back-side power rail (110A) and the first FET (GAA FET), the back-side source/drain via rail (98A) electrically connecting the back-side power rail (110A) to the first FET (GAA FET);
wherein the back-side source/drain via rail (98A) extend in the first horizontal direction (X-direction), and
the back-side source/drain via rail at least partially overlaps the back-side power rail in a vertical direction (110A and 98A vertically overlap).
Chen does not disclose a second FET over the first FET;
a power rail over the second FET and extending in the first horizontal direction; and
a source/drain via rail between the power rail and the second FET, the source/drain via rail electrically connecting the power rail to the second FET.
Nonetheless, Lai discloses a similar multi-stack semiconductor device (fig 1B) comprising a second FET (80p; [0027]) over a first FET (80n); and a power rail (20F, VSS) over the second FET (80p) and extending in the first horizontal direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a second FET stacked above a first FET as taught by Lai in the stack of Chen since this will decrease the footprint of the circuit on the semiconductor device.
As to claim 2, Chen in view of Liu disclose the multi-stack semiconductor device of claim 1 (paragraphs above).
Chen further discloses wherein the first FET (GAA FET) comprises a first channel (22B), a first gate line (66) covering the first channel (22B) and extending in a second horizontal direction (Y-direction) intersecting the first horizontal direction, and a first source/drain region (48) on both sides of the first channel (22B) in the first horizontal direction (X-direction), and
Liu further discloses the second FET (80p) comprises a second channel (80p), a second gate line (150) covering the second channel (80p) and extending in the second horizontal direction (Y-direction), and a second source/drain region (132p) on both sides of the second channel (80p) in the first horizontal direction (X-direction).
As to claim 5, Chen in view of Liu disclose the multi-stack semiconductor device of claim 1 (paragraphs above).
Chen further discloses wherein the source/drain via rail comprises a conductive layer and a conductive barrier layer ([0062], fig 36B), and
the conductive barrier layer covers a side surface of the conductive layer and a lower surface of the conductive layer ([0062]).
As to claim 6, Chen in view of Liu disclose the multi-stack semiconductor device of claim 5 (paragraphs above).
Chen further discloses wherein the conductive layer comprises molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), or aluminum (Al), or any combination thereof, or any alloy thereof ([0062]), and
the conductive barrier layer comprises Ti, Ta, W, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbon nitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or tungsten silicon nitride (WSiN), or any combination thereof ([0062]).
As to claim 9, Chen in view of Liu disclose the multi-stack semiconductor device of claim 1 (paragraphs above).
a back-side source/drain contact (82) between the back-side source/drain via rail (98) and the first FET (GAA FET); and
a source/drain contact between the source/drain via rail and the second FET (as combined with Liu the second FET would have the second source/drain contact with the source/drain rail),
wherein at least a portion of the back-side source/drain contact (82) overlaps the back-side source/drain via rail (98A) in the vertical direction (Z-direction), and
at least a portion of the source/drain contact overlaps the source/drain via rail in the vertical direction (as combined with Liu, the second FET would include the second source/drain contact in the same arrangement as shown with the backside source/drain contact).
As to claim 12, Chen in view of Liu disclose the multi-stack semiconductor device of claim 1 (paragraphs above).
Chen further discloses wherein the back-side power rail is configured to supply a first power to the back-side source/drain via rail ([0064]-[0065]), and
the power rail is configured to supply a second power to the source/drain via rail ([0064]-[0065]).
As to claim 13, Chen discloses a multi-stack semiconductor device (fig 26A, 10) comprising:
a first back-side power rail (110A) and a second back-side power rail (110B) extending in a first horizontal direction (X-direction);
a back-side signal rail (82) between the first back-side power rail (110A) and the second back-side power rail (110B), the back-side signal rail being spaced apart from the first back-side power rail (110A) in a second horizontal direction (Y-direction), the second horizontal direction (X-direction) intersecting the first horizontal direction (Y-direction), and the back-side signal rail (82) extending in the first horizontal direction (X-direction);
a back-side source/drain via rail (98A) connected to the first back-side power rail (110A);
a first field effect transistor (GAA FET) at a level over the back-side source/drain via rail (98A); and
wherein the first back-side power rail is configured to supply first power ([0065]), and
the second back-side power rail is configured to supply second power different from the first power ([0065]).
Chen does not disclose a second FET over the first FET.
Nonetheless, Lai discloses a similar multi-stack semiconductor device (fig 1B) comprising a second FET (80p; [0027]) over a first FET (80n); and a power rail (20F, VSS) over the second FET (80p) and extending in the first horizontal direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a second FET stacked above a first FET as taught by Lai in the stack of Chen since this will decrease the footprint of the circuit on the semiconductor device.
As to claim 14, Chen in view of Lai disclose the multi-stack semiconductor device of claim 13 (paragraphs above).
Chen further discloses a power trap via (82A”) electrically connecting the back-side power rail (110B).
Chen does not disclose a source/drain via rail over the second FET.
Nonetheless, Lai discloses a similar multi-stack semiconductor device (fig 1B) comprising a second FET (80p; [0027]) over a first FET (80n); and a power rail (20F, VSS) over the second FET (80p) and extending in the first horizontal direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a second FET stacked above a first FET as taught by Lai in the stack of Chen since this will decrease the footprint of the circuit on the semiconductor device.
As to claim 15, Chen in view of Lai disclose the multi-stack semiconductor device of claim 13 (paragraphs above).
Chen further discloses wherein a horizontal width of a source/drain via rail in the second horizontal direction is less than or equal to a horizontal width of the power rail (fig 26A, 110A and 98A).
Chen does not disclose a source/drain via rail over the second FET; and
a power rail over the source/drain via rail.
Nonetheless, Lai discloses a similar multi-stack semiconductor device (fig 1B) comprising a second FET (80p; [0027]) over a first FET (80n); and a power rail (20F, VSS) over the second FET (80p) and extending in the first horizontal direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a second FET stacked above a first FET as taught by Lai in the stack of Chen since this will decrease the footprint of the circuit on the semiconductor device.
As to claim 16, Chen in view of Lai disclose the multi-stack semiconductor device of claim 13 (paragraphs above).
Chen further discloses wherein a horizontal width of the back-side source/drain via rail (98A) in the second horizontal direction (Y-direction) is less than or equal to a horizontal width of the first back-side power rail in the second horizontal direction (110A in the Y-direction).
As to claim 17, Chen discloses a multi-stack semiconductor device (fig 26A, 10) comprising:
a first back-side power rail (110A) and a second back-side power rail (110B) extending in a first horizontal direction (X-direction);
a back-side source/drain via rail (98A) over the first back-side power rail (110A) and extending in the first horizontal direction (X-direction);
a first field effect transistor (GAA FET) at a level over the back-side source/drain via rail (98A);
wherein the first FET includes a first channel (22B), a first gate line (66) covering the first channel (22B) and extending in a second horizontal direction (Y-direction) intersecting the first horizontal direction (X-direction), and a first source/drain region (48) on both sides of the first channel (22B) in the first horizontal direction (X-direction),
the back-side source/drain via rail (98A) overlaps the first back-side power rail (110A) in a vertical direction (Z-direction), and
the first back-side power rail (110A) is configured to supply first power ([0065]), and
the second back-side power rail (110B) is configured to supply second power different from the first power ([0065]).
Chen does not disclose a second FET over the first FET;
a source/drain via rail over the second FET and extending in the first horizontal direction; and
a first power rail and a second power rail over the source/drain via rail and extending in the first horizontal direction,
the second FET includes a second channel, a second gate line covering the second channel and extending in the second horizontal direction, and a second source/drain region on both sides of the second channel in the first horizontal direction, and
the source/drain via rail overlaps the first power rail in the vertical direction.
Nonetheless, Lai discloses a similar multi-stack semiconductor device (fig 1B) comprising a second FET (80p; [0027]) over a first FET (80n); and a power rail (20F, VSS) over the second FET (80p) and extending in the first horizontal direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a second FET stacked above a first FET as taught by Lai in the stack of Chen since this will decrease the footprint of the circuit on the semiconductor device.
As to claim 18, Chen in view of Liu disclose the multi-stack semiconductor device of claim 17 (paragraphs above).
Chen further discloses a power tap via (82A) connecting the second back-side power rail (110A) and the second power rail to each other (110B).
As to claim 19, Chen in view of Liu disclose the multi-stack semiconductor device of claim 17 (paragraphs above).
Chen further discloses a back-side gate contact (82A”) contacting the first gate line (66);
a back-side signal rail (82B) connected to the back-side gate contact (82A’’), the back-side signal rail (82B) being between the first back-side power rail (110A) and the second back-side power rail (110B), and the back-side signal rail (82B) extending in the first horizontal direction (X-direction).
Chen does not disclose a gate contact contacting the second gate line; and
a front-side signal rail connected to the gate contact, the front-side signal rail being between the first power rail and the second power rail, and the front-side signal rail extending in the first horizontal direction.
Nonetheless, Lai discloses a similar multi-stack semiconductor device (fig 1B) comprising a second FET (80p; [0027]) over a first FET (80n); and a power rail (20F, VSS) over the second FET (80p) and extending in the first horizontal direction (X-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a second FET stacked above a first FET as taught by Lai in the stack of Chen since this will decrease the footprint of the circuit on the semiconductor device.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lai and further in view of Song et al. (US Pub. No. 2022/0093594 A1), hereafter referred to as Song.
As to claim 3, Chen in view of Liu disclose the multi-stack semiconductor device of claim 2 (paragraphs above).
Chen in view of Liu does not disclose an electrical single diffusion break over the back-side source/drain via rail.
Nonetheless, Song discloses an electrical single diffusion break over a back-side source/drain rail (fig 2, 207; [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the diffusion break of Song in the multi-stack semiconductor device of Chen in view of Liu since this will provide electrical isolation between the regions of the circuit.
As to claim 4, Chen in view of Liu disclose the multi-stack semiconductor device of claim 2 (paragraphs above).
Chen in view of Liu does not disclose a single diffusion break under the source/drain via rail.
Nonetheless, Song discloses a single diffusion break under a source/drain rail (fig 2, 207; [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the diffusion break of Song in the multi-stack semiconductor device of Chen in view of Liu since this will provide electrical isolation between the regions of the circuit.
Allowable Subject Matter
Claims 7-8, 10-11 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the back-side source/drain via rail or source/drain rail comprises: a first rail portion extending in the first horizontal direction; and a first protrusion portion protruding from a side surface of the first rail portion, as recited in claims 7-8; or a back-side source/drain via at a same level as the back-side source/drain via rail in the vertical direction; and a source/drain via at a same level as the source/drain via rail in the vertical direction, wherein the back-side source/drain via and the source/drain via have a pillar shape, as recited in claim 10; or wherein the back-side source/drain via rail comprises a first rail portion and a first protrusion portion, the first rail portion extends in the first horizontal direction, the first protrusion portion protrudes from a side surface of the first rail portion in the second horizontal direction, the source/drain via rail comprises a second rail portion and a second protrusion portion, the second rail portion extends in the first horizontal direction, the second protrusion portion protrudes from a side surface of the second rail portion in the second horizontal direction, as recited in claim 20. Claim 11 is allowable because of its dependence from claim 10.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2023/0042548A1 teaches in figure 7A-E layers 125a-b.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 8/25/2026
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