Prosecution Insights
Last updated: October 04, 2026
Application No. 18/812,312

METHOD FOR MANUFACTURING LIGHT EMITTING DIODE STRUCTURE

Non-Final OA §112
Filed
Aug 22, 2024
Priority
May 05, 2020 — provisional 63/020,061 +1 more
Examiner
YEMELYANOV, DMITRIY
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Raysolve Optoelectronics (Suzhou) Company Limited
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
425 granted / 572 resolved
+6.3% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
41 currently pending
Career history
611
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
56.4%
+16.4% vs TC avg
§102
21.9%
-18.1% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “forming the second semiconductor layer on a third substrate” of Claim 3. must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites “performing the second implantation operation to form the second implanted region and the second non-implanted region that is on the first implanted region.” It is not clear whether the positional limitation “that is on” applies only to the second non-implanted region or to the entirety of the fourth doping semiconductor layer resulting from the second implantation operation. Claim 4 recites “performing the second implantation operation to form the second implanted region and the second non-implanted region that is on the first implanted region.” It is not clear whether the positional limitation “that is on” applies only to the second non-implanted region or to the entirety of the fourth doping semiconductor layer resulting from the second implantation operation. Claim 8 recites “wherein performing a first implantation operation to form a first implanted region and a first non-implanted region in the second doping semiconductor layer comprises” Claim 1 already introduced “a first implantation operation to form a first implanted region and a first non-implanted region” It is not clear if Claim 8 refers to the first implantation operation of Claim 1 or is trying to introduce an additional, second recitation of a first implantation process. The Examiner recommends replacing “a” with –the--. Allowable Subject Matter Claims 1-3, 5-7, 9-20. The following is an examiner's statement of reasons for allowance: With regards to claim 1, none of the prior art teaches or suggests, alone or in combination, “performing a first etch operation to remove a portion of the second semiconductor layer and expose at least the first non-implanted region in the second doping semiconductor layer; performing a second etch operation to expose a plurality of contacts of a driving circuit formed in the first substrate; and electrically connecting the first non-implanted region in the second doping semiconductor layer and the second non-implanted region in the fourth doping semiconductor layer with the plurality of contacts.” in the combination required by the claim. Claims 2, 3, 5-7 and 9-20 are allowed by virtue of their dependency on the independent claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kususe et al (US 20060231852 A1) (Fig. 13), Yao etal. (US 20090302334 A1) (Fig. 6), Yu et al. (US 20120238046 A1) and Morris et al. (US 20200251638 A1) (Fig. 9) and related specifications disclose an LED array separated by isolation ion implanted region. Prior art fails disclose specific method steps required by claim 1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/ Examiner, Art Unit 2891 1. A method for manufacturing a light emitting diode (LED) structure, comprising: forming a first semiconductor layer on a first substrate, the first semiconductor layer comprising a first doping semiconductor layer, a first multiple quantum well (MQW) layer on the first doping semiconductor layer, and a second doping semiconductor layer on the first MQW layer; performing a first implantation operation to form a first implanted region and a first non-implanted region in the second doping semiconductor layer; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising a third doping semiconductor layer, a second MQW layer on the third doping semiconductor layer, and a fourth doping semiconductor layer on the second MQW layer; performing a second implantation operation to form a second implanted region and a second non-implanted region in the fourth doping semiconductor layer; performing a first etch operation to remove a portion of the second semiconductor layer and expose at least the first non-implanted region in the second doping semiconductor layer; performing a second etch operation to expose a plurality of contacts of a driving circuit formed in the first substrate; and electrically connecting the first non-implanted region in the second doping semiconductor layer and the second non-implanted region in the fourth doping semiconductor layer with the plurality of contacts. 2. The method of claim 1, wherein forming the first semiconductor layer on the first substrate comprises: forming the first semiconductor layer on a second substrate; bonding the first semiconductor layer onto the first substrate through a first bonding layer; and removing the second substrate. 3. The method of claim 1, wherein forming the second semiconductor layer on the first semiconductor layer comprises: forming the second semiconductor layer on a third substrate; bonding the second semiconductor layer onto the first semiconductor layer through a second bonding layer; and removing the third substrate. 4. The method of claim 1, wherein performing the second implantation operation to form the second implanted region and the second non-implanted region in the fourth doping semiconductor layer comprises: performing the second implantation operation to form the second implanted region and the second non-implanted region that is on the first implanted region. 6. The method of claim 1, wherein the first semiconductor layer comprises a first LED unit and a second LED unit formed therein, and the first LED unit and the second LED unit emit light of a first color; the second semiconductor layer comprises a third LED unit formed therein, and the third LED unit emits light of a second color different from the first color; and each of the first LED unit, the second LED unit, and the third LED unit comprises: the first doping semiconductor layer, the first MQW layer and the second doping semiconductor layer. 7. The method of claim 6, further comprising: forming a color conversion layer on the first LED unit to convert light of the first color to light of a third color different from the first color and the second color. 8. The method of claim 6, wherein performing a first implantation operation to form a first implanted region and a first non-implanted region in the second doping semiconductor layer comprises: implanting an ion-implanted material into the second doping semiconductor layer to form the first implanted region and the first non-implanted region in the second doping semiconductor layer. 9. The method of claim 8, wherein the ion-implanted material of the first LED unit extends to the ion-implanted material of the second LED unit. 10. The method of claim 8, wherein each of the first LED unit, the second LED unit, and the third LED unit comprises a light emitting region surrounded by the ion-implanted material in the second doping semiconductor layer. 11. The method of claim 8, further comprising: forming a passivation layer over the first semiconductor layer and the second semiconductor layer; and removing a portion of the passivation layer to expose the first non-implanted region in the second doping semiconductor layer, the second non-implanted region in the fourth doping semiconductor layer, and the plurality of contacts. 12. The method of claim 11, wherein another portion of the passivation layer covers the ion-implanted material and exposes a light emitting region of each of the first LED unit, the second LED unit, and the third LED unit. 13. The method of claim 11, wherein electrically connecting the first non-implanted region in the second doping semiconductor layer and the second non-implanted region in the fourth doping semiconductor layer with the plurality of contacts, comprises: forming an electrode layer on the passivation layer, the electrode layer electrically connecting the first non-implanted region in the second doping semiconductor layer and the second non-implanted region in the fourth doping semiconductor layer with the plurality of contacts. 14. The method of claim 13, wherein the electrode layer is in contact with a portion of the second doping semiconductor layer through a first opening on the passivation layer, and in contact with the contact through a second opening. 15. The method of claim 14, wherein the second opening of the third LED unit is formed through the first doping semiconductor layer of the third LED unit, the first MQW layer of the third LED unit, the second doping semiconductor layer of the third LED unit, and the ion-implanted material between the first LED unit and the second LED unit. 16. The method of claim 13, wherein the first LED unit, the second LED unit and the third LED unit are separately connected to different contacts through the electrode layer. 17. The method of claim 8, wherein top surfaces of the second doping semiconductor layer of the first LED unit, the second doping semiconductor layer of the second LED unit, and the ion-implanted material are substantially coplanar. 18. The method of claim 6, wherein the first non-implanted region is configured to define a light emitting region of each of the first LED unit and the second LED unit, and the first implanted region is configured to isolate the first LED unit with the second LED unit. 19. The method of claim 6, wherein the second non-implanted region is configured to define a light emitting region of the third LED unit, and the second implanted region is configured to isolate the third LED unit with the first LED unit and the second LED unit. 20. The method of claim 6, wherein the first LED unit, the second LED unit, and the third LED unit are non-overlapping in a top view of the LED structure.
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Prosecution Timeline

Aug 22, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
94%
With Interview (+19.2%)
2y 7m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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