Prosecution Insights
Last updated: August 17, 2026
Application No. 18/812,476

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND SEMICONDUCTOR MANUFACTURING SYSTEM

Non-Final OA §103§112
Filed
Aug 22, 2024
Priority
Sep 01, 2023 — JP 2023-142068
Examiner
COUSINEAU, CONNOR DANIEL
Art Unit
Tech Center
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
1 granted / 1 resolved
+40.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
10 currently pending
Career history
6
Total Applications
across all art units

Statute-Specific Performance

§101
12.5%
-27.5% vs TC avg
§103
46.9%
+6.9% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2023-142068, filed on 09/01/2023. Claim Rejections - 35 USC § 112(d) The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 6 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Specifically, claim 6 is presented as allowing the physical coefficient change circuitry to approximate the output value to another semiconductor manufacturing apparatus instead of the semiconductor manufacturing apparatus claimed in claim 1. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO US 20220207492 A1 in view of SHAPIRO US 20130317629 A1. Regarding claim 1, YAMAMOTO discloses an information processing apparatus comprising: a simulation execution circuitry configured to execute a simulation of a process state, which is being executed in a semiconductor manufacturing apparatus, using a physical model of the semiconductor manufacturing apparatus by setting operating conditions of the physical model to same conditions as those of the semiconductor manufacturing apparatus (YAMAMOTO discloses ¶56 “The simulation execution unit 108 executes the simulation by the simulation model according to the same process parameters as those for the semiconductor manufacturing apparatus 10 that is performing the process, so as to calculate the process state of the semiconductor manufacturing apparatus 10 that is performing the process.” ¶29 “The virtual sensor data are calculated based on a simulation model (physical model) to be described later.”); a physical coefficient change circuitry configured to change a physical coefficient of the physical model such that an output value of the physical model approximates to a corresponding output value of the semiconductor manufacturing apparatus (YAMAMOTO discloses ¶71 “By using the provided physical data, virtual data, and process parameters, the simulation model editing unit 148 edits the simulation model to reduce a difference between the physical data and the virtual data for the same process parameters (to make an optimum simulation model) through, for example, a machine learning.”); a deterioration state analysis circuitry configured to analyze a deterioration state of the semiconductor manufacturing apparatus (YAMAMOTO discloses ¶107” Further, the information processing system 1 according to the present embodiment may also determine the influence of a portion in a deteriorated state on the process…” ¶90 “When the process that is being performed by the semiconductor manufacturing apparatus 10 is ended, the process proceeds from step S18 to step S20, and the simulation result determination unit 110 of the autonomous control controller 13 compares the physical sensor data and the virtual sensor data for the same position and time, to determine whether the physical sensor data and the virtual sensor data for the same position and time match each other.”); and a deterioration state output circuitry configured to output information regarding the deterioration state of the semiconductor manufacturing apparatus analyzed by the deterioration state analysis circuitry (YAMAMOTO discloses ¶104 “As for the failure pre-detecting process, the failure pre-detection unit 120 may search for the type and the cause of the failure from failure determination data, and calculate the number of process performing times or the time period of the process that is available until the manufacturing is affected, from the searched type and cause of the failure and the past failure history. Further, from the searched type and cause of the failure, the failure pre-detection unit 120 may specify parts that need to be replaced”). YAMAMOTO does not disclose expressly modifying the coefficients during runtime and equating those changes to deterioration/wear. SHAPIRO discloses configured to change the coefficients of the model are also representative of differences occurring between the physical system and the model (¶75-76 and 79 which disclose receiving the current coefficients, automatically adjusting the coefficients to ensure model accuracy, and to reflect the most accurate relationship between the simulated values and the measured values). YAMAMOTO and SHAPIRO are analogous art because they are from the same field of endeavor using a digital twin to represent the ideal conditions of a machine to determine changes in the operation. At the time of the invention, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to try determining deterioration based on changes to the model’s coefficient(s) because such also represents a change in the physical system compared to the digital twin similar to the sensor-based comparison used in Yamamoto. The suggestion/motivation for doing so would have been substituting sensor-based determination for coefficient-based detection provides the predictable solution of determining that the physical system is changing compared to the model which is representative of deterioration (SHAPIRO ¶17-18 “Improving process stability, allowing operation closer to target, constraint and optimum values. Forecasting, process simulation, determining the ability to meet obligations.”). Therefore, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to combine YAMAMOTO and SHAPIRO for the benefit of modifying the coefficients during runtime and equating those changes to wear to obtain the invention as specified in claim 1. Regarding claim 2, the limitations of claim 1 have been discussed above. Wherein the simulation execution circuitry executes the simulation of the process state, which is being executed in the semiconductor manufacturing apparatus, using the physical model whose physical coefficient has been changed by the physical coefficient change circuitry (YAMAMOTO discloses ¶38 “The base simulation model is edited to adapt to each semiconductor manufacturing apparatus 10 through, for example, a deep learning. The editing is performed, for example, every time each semiconductor manufacturing apparatus 10 is operated, so that the prediction accuracy of the simulation model in each semiconductor manufacturing apparatus 10 is improved as the number of the operation times increases.”). Regarding claim 3, the limitations of claim 1 have been discussed above. Further comprising: a prediction circuitry configured to predict a timing and a content of maintenance required for the semiconductor manufacturing apparatus, based on the deterioration state of the semiconductor manufacturing apparatus analyzed by the deterioration state analysis circuitry (YAMAMOTO discloses ¶63 “the maintenance list management unit 116 specifies a maintenance item from parts that need to be replaced (parts necessary for a maintenance task) as a result of the pre-detection by the simulation result determination unit 110 such as the failure pre-detection or the maintenance time pre-detection.”, ¶78 “the contents for supporting the task of the maintenance item, … which are included the task request form displayed on the operation terminal.”, ¶105 “Thus, the maintenance list management unit 116 … and generate the maintenance list to cope with the failure, at a timing calculated in consideration of the number of process performing times or the time period of the process that is available until the manufacturing is affected.”). Regarding claim 4, the limitations of claim 3 are discussed above. Further comprising: an inventory management circuitry configured to manage an inventory of parts required for the maintenance, the timing and the content of which are predicted by the prediction circuitry (YAMAMOTO discloses ¶113 “In the information processing system 1 according to the present embodiment, the information of the replacement parts necessary for the task of the maintenance item of the semiconductor manufacturing apparatus 10 is notified in advance to the factory side server 38, so that the supply timing of the replacement parts may be brought to an earlier timing.”, ¶114 “manages the information on the ordering of replacement parts from the semiconductor manufacturing apparatuses 10 of multiple customers, so that costs for managing parts may be reduced by analyzing demands for parts through, for example, a machine learning, adjusting a production plan based on predicted demands for replacement parts, and optimizing the inventory management.”). Regarding claim 5, the limitations of claim 1 are discussed above. Further comprising: an adjustment circuitry configured to adjust process parameters of the operating conditions of the semiconductor manufacturing apparatus to uniformize a quality of wafers manufactured by the semiconductor manufacturing apparatus, based on a result of the simulation of the process state, which is being executed in the semiconductor manufacturing apparatus, executed using the physical model (YAMAMOTO discloses ¶143 “Further, examples of the additional sensor 12 include a temperature sensor installed in the wafer surface, a temperature sensor installed in the surface of the lifting mechanism that faces a heat reserving cylinder and a reactor, and a gas introduction temperature sensor.”, ¶144 “FIG. 14 is a diagram illustrating an example of the process of generating and updating the temperature related simulation model.”, ¶91 “When it is determined that the physical sensor data and the virtual sensor data do not match each other, the simulation result determination unit 110 performs a process parameter adjusting process of step S22 for optimizing the process parameters, so as to obtain customer's desired results after the process is performed”). Adjusting the process for optimizing the process parameters to obtain customers desired results is interpreted as uniformizing the wafer quality around the customers desired results. Regarding claim 6, the limitations of claim 1 are discussed above. YAMAMOTO discloses modifying the model based on multiple semiconductor apparatus (YAMAMOTO discloses ¶37 “By editing a simulation model based on the information on the multiple semiconductor manufacturing apparatuses 10 as described later, a base simulation model may be edited (corrected) based on the operations of the multiple semiconductor manufacturing apparatuses 10. The base simulation model is a model that corresponds to the greatest common divisor based on the multiple semiconductor manufacturing apparatuses 10.”). YAMAMOTO does not disclose expressly modifying the coefficients during runtime and equating those changes to deterioration/wear. SHAPIRO discloses changes the coefficients of the model are also representative of differences occurring between the physical system and the model (¶75-76 which disclose receiving the current coefficients, automatically adjusting the coefficients to ensure model accuracy, and to reflect the most accurate relationship between the simulated values and the measured values. ¶79 “The coefficients of function are thus adjusted by the module 717 to reflect the most accurate relationship between the simulated variable values and the measured variable values.”). YAMAMOTO and SHAPIRO are analogous art because they are from the same field of endeavor using a digital twin to represent the ideal conditions of a machine to determine changes in the operation. At the time of the invention, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to try determining deterioration based on changes to the model’s coefficient(s) because such also represents a change in the physical system compared to the digital twin similar to the sensor-based comparison used in Yamamoto. The suggestion/motivation for doing so would have been substituting sensor-based determination for coefficient-based detection provides the predictable solution of determining that the physical system is changing compared to the model which is representative of deterioration (SHAPIRO ¶17-18 “Improving process stability, allowing operation closer to target, constraint and optimum values. Forecasting, process simulation, determining the ability to meet obligations.”). Therefore, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to combine YAMAMOTO and SHAPIRO for the benefit of modifying the coefficients during runtime and equating those changes to wear to obtain the invention as specified in claim 6. Regarding claim 7, the limitations of claim 1 are discussed above. YAMAMOTO discloses a deviation for each process that could be used to detect a change in the coefficients (YAMAMOTO discloses ¶106 “In the simulation by the simulation model, the virtual process result data in which a difference exists between the physical sensor data and the virtual sensor data may be calculated so that the influence of the difference on the process may be determined. Further, by accumulating and checking a deviation (tendency of the change) for each process, it is possible to determine how many processes are available until the lot-out (until the production is affected).”). YAMAMOTA does not disclose expressly a tendency based on the changes in the physical coefficient. SHAPIRO discloses a tendency based on the changes in the physical coefficient. (SHAPIRO discloses ¶52 “The ultimate goal of process simulation is to determine transfer functions that relate input disturbances to output changes over time. The Real-time Optimization Module (RTO, see FIG. 5 for details) empirically generates Input/Output transfer functions using data obtained from the simulated open-loop step performed on the current dynamic process model”.). YAMAMOTO and SHAPIRO are analogous art because they are from the same field of endeavor using a digital twin to represent the ideal conditions of a machine to determine changes in the operation. At the time of the invention, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to try determining a tendency based on changes to the model’s coefficient(s) because the deterioration data would show a pattern as more data is fed back into the digital twin. The suggestion/motivation for doing so would have been substituting a deviation on the data to a tendency on the changes of the physical coefficients (SHAPIRO ¶17-18 “Improving process stability, allowing operation closer to target, constraint and optimum values. Forecasting, process simulation, determining the ability to meet obligations.”). Therefore, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to combine YAMAMOTO and SHAPIRO for the benefit of modifying the coefficients during runtime and equating those changes to wear to obtain the invention as specified in claim 7. Regarding claim 8, providing an information processing apparatus configured to (YAMAMOTO discloses the information processing apparatus 1), the claim limitations are otherwise identical to claim 1 and have been discussed above. Regarding claim 9, a semiconductor manufacturing apparatus (YAMAMOTO discloses the semiconductor manufacturing apparatus 10); and an information processing apparatus (YAMAMOTO discloses the information processing apparatus 1). The claim limitations are otherwise identical to claim 1 and have been discussed above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CONNOR D COUSINEAU whose telephone number is (571)447-9620. The examiner can normally be reached Monday-Friday 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached at (571) 272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.D.C./Examiner, Art Unit 2115 /MARK A CONNOLLY/Primary Examiner, Art Unit 2115 7/31/26
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Prosecution Timeline

Aug 22, 2024
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 7m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allowance rate.

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