Prosecution Insights
Last updated: October 02, 2026
Application No. 18/812,545

SEMICONDUCTOR MODULE

Non-Final OA §102§103
Filed
Aug 22, 2024
Priority
Jan 16, 2024 — RE 10-2024-0006973
Examiner
SLUTSKER, JULIA
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
843 granted / 1097 resolved
+16.8% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
30 currently pending
Career history
1129
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
20.8%
-19.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1097 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 3, 4, 9, 10, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR’470 (KR 21080061470, Machine Translation is provided). Regarding claim 1, KR’470 discloses a semiconductor module comprising: a module substrate (Fig.2, numeral 100); a controller device (300) and a memory device (200) mounted on a surface of the module substrate (100); and a plurality of tabs (400) at a side of the module substrate (100), wherein the module substrate has a first through hole (H) that vertically extends through the module substrate (100), wherein the first through hole is between the controller device (300) and the memory device (200), wherein the first through hole (H) extends in a first direction (D1) that runs across between the controller device (300 and the memory device (200), wherein a length of the first through hole (H) along the first direction (D1) is less than a width of the controller device (300) along the first direction (D1) (Figs.2, 4). Regarding claim 3, KR’470 discloses wherein the controller device (300) has a lateral surface in a second direction (D2) toward the first through hole (H), and when viewed in the second direction, the first through hole (H) is between lateral surfaces of the controller device (300) in the first direction (D1) (Fig.4). Regarding claim 4, KR’470 discloses wherein the first through hole includes a plurality of first through hole (H)s, and the plurality of first through holes is arranged in the first direction (D1) (Fig. 4). Regarding claim 9, KR’470 discloses wherein the controller device (300) is spaced apart from the memory device (200) in a second direction (D2) that intersects the first direction (D2), the tabs (400) are spaced apart in the second direction from the controller device, and the tabs are arranged in the first direction (Figs. 2, 4). Regarding claim 10, KR’470 discloses wherein the controller device (300) and the memory device (200) are mounted on a top surface of the module substrate (100), and the controller device (300) and the memory device (200) are electrically connected to the tabs through a plurality of lines (120) provided on a bottom surface of the module substrate (100) (Fig.3). Regarding claim 18, KR’470 discloses a semiconductor module (Figs. 2, 4), comprising: a substrate (100); a first heating device (200) mounted on a top surface of the substrate (100); and a second heating device (300) mounted on the top surface of the substrate (100) and spaced apart in a first direction (D1) from the first heating device, wherein the substrate (100) has a through hole (H) between the first heating device (200) and the second heating device (300), the through hole (H) vertically extending through the substrate (100), wherein the through hole extends in a second direction (D2) that runs across between the first heating device (200) and the second heating device (300), wherein a length along the second direction of the through hole (H) is less than a width along the second direction of the first heating device (200) and a width along the second direction (D2) of the second heating device (300) (Fig.3), and wherein the through hole is filled with air (page 3, paragraph 4). Regarding claim 19, KR’470 discloses wherein, when viewed in the first direction, the through hole (H) is between lateral surfaces in the second direction of the first heating device (200) and between lateral surfaces in the second direction of the second heating device (300). Regarding claim 20, KR’470 discloses wherein the through hole includes a plurality of through holes (H), and the plurality of through holes is arranged in the second direction (Fig.4). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR’470. Regarding claim 2, KR’470 does not disclose wherein the length of the first through hole is 0.4 times to 0.8 times the width of the controller device. KR’740 however discloses the length of the first through hole is adjusted to optimize the flow of air through the hole (page 3, paragraph 4). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have the length of the first hole to be in the claimed range for the purpose of optimization air flow through the hole. Regarding claim 5, KR’470 does not disclose wherein a sum of lengths of the first through holes is 0.4 times to 0.8 times the width of the controller device. KR’740 however discloses the length of the first through hole is adjusted to optimize the flow of air through the hole (page 3, paragraph 4). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have a sum of lengths of the first through holes to be in the claimed range for the purpose of optimization air flow through the holes. Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over KR’470 as applied to claim 1 above, and further in view of Kang (US 2019/0131203). Regarding claim 6, KR’470 discloses wherein the module substrate has a second through hole (H) that vertically extends through the module substrate (100) (Fig.4). KR’470 does not disclose a power device mounted on the surface of the module substrate, wherein the second through hole is between the controller device and the power device or between the memory device and the power device. Kang however discloses a power device (Fig.1, numeral 400) mounted on the surface of the module substrate ([0024]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify KR’470 with Kang to have disclose a power device mounted on the surface of the module substrate, wherein the second through hole is between the controller device and the power device or between the memory device and the power device for the purpose of fabrication a multi-chip package (Kang, [0022]). Regarding claim 7, KR’470 in view of Kang discloses wherein the second through hole (H) extends between the controller device (300) and the power device (Kang, Fig.1, numeral 400) in a direction that runs across between the controller device (300) and the power device, and wherein a length of the second through hole (H) along a second direction (D1) is less than a width of the controller device (300) along the second direction (D1), the second direction running across between the controller device (300) and the power device (Kang, Fig.1, numeral 400). Regarding claim 8, KR’470 in view of Kang discloses wherein the second through hole (H) extends between the memory device (200) and the power device (Kang, Fig.1, numeral 400) in a direction that runs across between the memory device (200) and the power device (Kang, Fig. 1, numeral 400). Claim(s) 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR’470 in view of Kang. Regarding claim 11, KR’470 discloses a semiconductor module, comprising: a module substrate (Fig.2, 4, numeral 100); a controller device (300), a memory device (200), that are spaced apart from each other on a top surface of the module substrate (100); and a plurality of tabs (400) on a side of the module substrate in a first direction (D1), wherein the controller device (300) are on a side of the memory device (200) in the first direction (D1), wherein the module substrate (100) has a first through hole (H) and a second through hole (H) that vertically extend through the module substrate (100), wherein the first through hole (H) extends in a second direction (D2) between the controller device (300) and the memory device (200), the second direction (D2) intersecting the first direction (D1). KR’470 does not disclose a power device mounted on the surface of the module substrate, wherein the second through hole is between the controller device and the power device or between the memory device and the power device. Kang however discloses a power device (Fig.1, numeral 400) mounted on the surface of the module substrate ([0024]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify KR’470 with Kang to have disclose a power device mounted on the surface of the module substrate, wherein the second through hole is between the controller device and the power device or between the memory device and the power device for the purpose of fabrication a multi-chip package (Kang, [0022]). Regarding claim 12, KR’470 discloses wherein a length along the second direction of the first through hole is less than a width along the first direction of the controller device (Fig.4). Regarding claim 13, KR’470 does not disclose wherein the length of the first through hole is 0.4 times to 0.8 times the width of the controller device. KR’740 however discloses the length of the first through hole is adjusted to optimize the flow of air through the hole (page 3, paragraph 4). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have the length of the first hole to be in the claimed range for the purpose of optimization air flow through the hole. Regarding claim 14, KR’470 discloses wherein the first through hole includes a plurality of first through holes (H), and the plurality of first through holes is arranged in the second direction (Fig.4). Regarding claim 15, Kang discloses wherein the controller device (300) and the power device (400) are spaced apart from each other in the second direction, and KR’470 discloses the second through hole (H) extends in the first direction between the controller device (300) and the power device (400). Regarding claim 16, KR’470 discloses wherein a length of the second through hole H) along the first direction is less than a width of the controller device (300) along the first direction (Fig.4). Regarding claim 17, KR’470 in view of Kang discloses wherein the controller device (300), the memory device (200), and the power device (Kang, Fig.1, numeral 400) are electrically connected to the tabs through a plurality of lines (120) provided on a bottom surface of the module substrate (page 3, paragraph 2; Fig.3). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Aug 22, 2024
Application Filed
Aug 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.9%)
2y 5m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1097 resolved cases by this examiner. Grant probability derived from career allowance rate.

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