Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 22, 2024, claims 1-19 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed August 22, 2024 have been considered.
Claim Objections
Claims 2-4 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5 is/are rejected, as understood, under 35 U.S.C. 102(A)(1) as being anticipated by Hiroki et al. [JP 2011040161 A].
With respect to claim 1, Hiroki et al. disclose a semiconductor memory apparatus [figs. 20 and 29] comprising: a sub-wordline driver [“…Subword lines SWLL0 and SWLL1 are driven by subword line driver SWDE0, subword lines SWLR3 and SWLR6 are driven by subword line driver SWDE1, and subword line SWLL8 (and subword line SWLL9 (not shown)) is driven by subword line driver SWDE2.” – 3rd par. of the Emobodiment 2 section] configured to receive a wordline control signal to enable a wordline coupled with a bitline [“…These sub word line pairs are arranged one row apart from each other. The data stored in the memory cell is always read onto bit lines BL and ZBL” – 4th par. of the Emobodiment 2 section. It is noted that the wordlines (which control access) interact with the bitlines (which transfer data) to read the memory cell. Additionally, When a sub wordline is activated (goes high), it turns on the access transistor in the memory cell, which connects the storage node to the bitline pair (BL/ZBL), allowing data to transfer.], and configured to delay the wordline control signal to generate a bitline switching signal [“…By setting bit line equalize instruction signal BLEQ to a low resistance conductive state, the period during which bit lines BLL and ZBLL are precharged to intermediate voltage VBL is determined by the delay time of delay circuit 113. “ – 32nd par. of the Emodiment 6 section. It is noted that the equalization/precharge period (controlled by 113) must conclude before or in coordination with the activation of the wordline. The delay circuit ensures that the bitline equalization circuit is active for the precise amount of time required before the wordline activates and potentially switches the bitline state. Further, it implies that the bitline precharge signal is timed (delayed) to ensure proper equalization,, rather than directly saying the wordline signal itself is delayed, but it controls the sequence of events (precharge then activate wordline)]; a bitline sense amplifier configured to amplify and latch signals received through a first input node and a second input node [“…When this cell data read period is completed, sense amplifier activation signals SON and ZSOP are activated, and sense amplifier circuit S / A is activated. The sense amplifier circuit S / A differentially amplifies the potential difference (ΔV1 + ΔV2) between the bit lines BL and ZBL.” – 10th par. of the Embodiment 1 section]; and a bitline switching circuit configured to electrically couple the bitline with the first input node and a bitline bar with the second input node, in response to the bitline switching signal [“Bit lines BLL and ZBLL are coupled to common bit lines CBL and ZCBL via bit line isolation gate BIGL. Bit line isolation gate BIGL is selectively turned on / off in response to bit line isolation instruction signal BLIL from isolation control circuit 104l.” – 5th par. of the Emobodiment 6 section].
With respect to claim 5, Hiroki et al. disclose the bitline switching circuit comprises: a first switch that electrically couples the bitline to the first input node in response to the bitline switching signal [any transistors in BIGR or BIGL connected to one of the bit lines]; and a second switch that electrically couples the bitline bar to the second input node in response to the bitline switching signal [any other transistors in BIGR or BIGL connected to the other respective bitline]. See fig. 29.
Claim(s) 6-9 is/are rejected, as understood, under 35 U.S.C. 102(A)(1) as being anticipated by 서영훈 [KR 20150015809 A] – for discussion purposes this reference will be referred to as REF ‘809.
With respect to claim 6, REF ‘809 discloses an operating method of a semiconductor memory apparatus, the method comprising: electrically isolating a bitline from a first input node of a bitline sense amplifier [“… the first isolation / offset remover 151 may block the connection between the bit line BL and the sensing bit line SABL in response to the isolation signal ISO. “ – 18th par. of the Description of Embodiments section], and electrically isolating a bitline bar from a second input node of the bitline sense amplifier [“The second isolation / offset remover 152 may block the connection between the complementary bit line BLB and the complementary sensing bit line SABLB in response to the isolation signal ISO. “ – 18th par. of Description of Embodiments section]; performing a mismatch compensation operation with the bitline sense amplifier [“The sense amplifier 150 in accordance with the present invention performs offset elimination and pre-sensing operations in response to an isolation signal ISO and an offset cancellation signal OC to provide bit line coupling noise It is possible to reduce the sense amplifier offset noise (S / A offset noise).” – 15th par. of the Description of Embodiments section], and enabling a wordline to electrically couple a memory cell to the bitline [“The row decoder 120 may select any one of a plurality of word lines connected to the memory cell array 140.” – 5th par. of Description of Embodiments section]; electrically coupling the first input node with the bitline, and electrically coupling the second input node with the bitline bar [19th par. of Description of Embodiments section]; and developing a voltage level difference of a first node and a second node by amplifying voltage levels of the first and second input nodes [“ The sense amplifier unit 153 can sense and amplify the voltage difference between the bit line BL and the complementary bit line BLB according to the first and second control signals LA and LAB.” – 19th par. of the Description of Embodiments section].
With respect to claim 7, REF ‘809 discloses the performing the mismatch compensation operation includes electrically coupling the first input node with the first node and electrically coupling the second input node with the second node [“ The sense amplifier unit 153 can sense and amplify the voltage difference between the bit line BL and the complementary bit line BLB according to the first and second control signals LA and LAB.” – 19th par. of the Description of Embodiments section].
With respect to claim 8, REF ‘809 discloses before enabling the wordline, precharging the second node [“the memory device 100 may perform a refresh operation based on a charge amount of a capacitor included in the memory cell MC. At this time, the bit line BL connected to the memory cell MC is precharged to the precharge voltage Vpre. Thereafter, as the word line WL is activated…” – 13th par. of the Description of Embodiments section].
With respect to claim 9, REF ‘809 discloses before the enabling of the wordline, electrically coupling the bitline with the first input node and electrically coupling the bitline bar with the second input node for a predetermined time [“the memory device 100 may perform a refresh operation based on a charge amount of a capacitor included in the memory cell MC. At this time, the bit line BL connected to the memory cell MC is precharged to the precharge voltage Vpre. Thereafter, as the word line WL is activated…” – 13th par. of the Description of Embodiments section].
Allowable Subject Matter
Claims 11-19 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2: The semiconductor memory apparatus of claim 1, wherein the sub-wordline driver is configured to generate the bitline switching signal by delaying the wordline control signal by a time during which a mismatch compensation operation of the bitline sense amplifier is performed.
-with respect to claim 3: The semiconductor memory apparatus of claim 1, wherein the bitline sense amplifier comprises: an input circuit configured to change a voltage level of a first node based on a signal received through the first input node, and configured to change a voltage level of a second node based on a signal received through the second input node; a latch circuit configured to change the voltage levels of the first and second nodes based on the voltage levels of the first and second nodes; an isolation switching circuit configured to electrically couple the first input node with the second node and the second input node with the first node, based on an isolation switching signal; and a compensation switching circuit configured to electrically couple the first input node with the first node and the second input node with the second node, based on a mismatch compensation signal.
-with respect to claim 10: The method of claim 6, further comprising, after the electrically coupling of the first input node with the bitline and the electrically coupling of the second input node with the bitline bar, electrically coupling the first input node with the second node, and electrically coupling the second input node with the first node.
-with respect to claim 11, a sub-wordline driver configured to receive a wordline control signal and enable one of a first wordline coupled with a first bitline and a second wordline coupled with a second bitline based on the wordline control signal, and configured to delay the wordline control signal to generate one of a first bitline switching signal and a second bitline switching signal; a bitline sense amplifier configured to amplify and latch voltage levels of a global bitline and a global bitline bar.
-with respect to claim 16, enabling one of first and second wordlines to electrically couple one of the first and second bitlines to a memory cell; electrically coupling a bitline electrically coupled with an enabled wordline between the first and second bitlines with the global bitline; and developing a voltage level difference of a first node and a second node by amplifying voltage levels of the global bitline and the global bitline bar.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 29, 2026