DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2023/0413573 Im.
1. Referring to claim 1, Im teaches a memory cell array, comprising: a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: a cell transistor having: a source region, (Figure 16 not shown &Paragraph 0033), electrically connected to a bit line, (Figure 16 #20), extending in the first direction; a drain region, (Figure 16 not shown &Paragraph 0033); a word line layer, (Figure 16 #18R); a lower channel layer, (Figure 16 #16B), electrically connected to the source region, (Figure 16 not shown &Paragraph 0033), and the drain region, (Figure 16 not shown &Paragraph 0033), and disposed below the word line layer, (Figure 16 #18R), in the first direction; and an upper channel layer, (Figure 16 #16A), electrically connected to the source region, (Figure 16 not shown &Paragraph 0033), and the drain region, (Figure 16 not shown &Paragraph 0033), and disposed above the word line layer, (Figure 16 #18R), in the first direction; and a cell capacitor, (Figure 16 #DC), electrically connected to the drain region, (Figure 16 not shown &Paragraph 0033); and a plurality of inter-level isolation layers, (Figure 16 #12), each separating adjacent memory levels of the plurality of memory levels.
2. Referring to claim 4, Im teaches a memory cell array of claim 1, wherein the cell transistor further comprises: a gate oxide layer encapsulating the word line layer, (Figure 16 #18R), wherein the gate oxide layer comprises silicon oxide (SiO2), (Figure 16 #17 & Paragraph 0078).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
3. Claims 2, 3, 5, and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
4. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the memory cell array of claim 1, wherein the word line layer comprises tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium nitride (TiN), iridium (Ir), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), rhodium (Rh), or conductive oxides or nitrides thereof, or any combination thereof and has a thickness in the first direction of between 5 nm and 20 nm; the memory cell array of claim 1, wherein the lower channel layer and the upper channel layer each comprise silicon (Si) and has a thickness in the first direction of between 5 nm and 10 nm; the memory cell array of claim 1, wherein the source region and the drain region each comprise epitaxially grown n-type doped silicon (Si); and/or the memory cell array of claim 1, wherein the cell transistor further comprises: a first spacer layer interfacing the word line layer with the source region; and a second spacer layer interfacing the word line layer with the drain region.
5. The prior art, (U.S. PUBS No. 2023/0413573), teaches a memory cell array, comprising: a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: a cell transistor having: a source region electrically connected to a bit line extending in the first direction; a drain region; a word line layer; a lower channel layer electrically connected to the source region and the drain region and disposed below the word line layer in the first direction; and an upper channel layer electrically connected to the source region and the drain region and disposed above the word line layer in the first direction; and a cell capacitor electrically connected to the drain region; and a plurality of inter-level isolation layers, each separating adjacent memory levels of the plurality of memory levels, but is silent to the combination of a method of forming cell transistors in a semiconductor memory device, comprising: performing a word line (WL) slit fill process, to fill WL slits formed in a stacking mold with a nitride layer, wherein: the stacking mold comprises a plurality of unit stacks, each unit stack comprising: a lower sacrificial layer, a lower channel layer over the lower sacrificial layer, an upper sacrificial layer on the lower channel layer, and an upper channel layer on the upper sacrificial layer stacked in a first direction, each unit stack has DTI gaps partially filled with an insulator layer and extending in a second direction that is orthogonal to the first direction, and the WL slits are each disposed between the lower channel layer and the upper channel layer between adjacent unit stacks of the stacking mold; selectively removing the insulator layer within the DTI gaps; and selectively removing the lower sacrificial layer and forming inter-level isolation gaps each between the lower channel layer and the upper channel layer between adjacent unit stacks of the stacking mold.
6. The prior art, (U.S. PUBS No. 2023/0413573), teaches a memory cell array, comprising: a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: a cell transistor having: a source region electrically connected to a bit line extending in the first direction; a drain region; a word line layer; a lower channel layer electrically connected to the source region and the drain region and disposed below the word line layer in the first direction; and an upper channel layer electrically connected to the source region and the drain region and disposed above the word line layer in the first direction; and a cell capacitor electrically connected to the drain region; and a plurality of inter-level isolation layers, each separating adjacent memory levels of the plurality of memory levels, but is silent to the combination of a method of forming cell transistors in a semiconductor memory device, comprising: forming a transistor slit through a stacking mold in a first direction, the transistor slit extending in a second direction that is orthogonal to the first direction, the stacking mold comprising a plurality of unit stacks, each unit stack comprising: a lower sacrificial layer, a lower channel layer over the lower sacrificial layer, an upper sacrificial layer on the lower channel layer, and an upper channel layer on the upper sacrificial layer stacked in the first direction; performing a recess forming process, to form recesses in the upper sacrificial layers from sidewalls of the transistor slit; forming a first insulator layer on exposed surfaces of the lower channel layers and the upper channel layers within the transistor slit and the recesses; filling the transistor slit and the recesses with a first nitride layer; performing a deep trench isolation (DTI) lateral cut process, to form DTI gaps through the stacking mold in the first direction, the DTI gaps extending in a third direction that is orthogonal to the first and second directions; filling the DTI gaps with a second insulator layer; selectively removing the first nitride layer from the transistor slit and the recesses; forming word line (WL) slits each between the lower channel layer and the upper channel layer between adjacent unit stacks of the stacking mold; performing a WL slit fill process, to fill the WL slits and the recesses with a second nitride layer; selectively removing the second insulator layer; selectively removing the lower sacrificial layer and forming inter-level isolation gaps each between the lower channel layer and the upper channel layer between adjacent unit stacks of the stacking mold; filling the inter-level isolation gaps with inter-level isolation layers; performing a gate oxide formation process, to form a gate oxide layer on exposed inner surfaces of the WL slit and the recesses; and performing a WL slit fill process, to fill the WL slits with a word line layer.
7. These combinations have been found to not be anticipated or render obvious over the prior art, hence claims 7-20 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 8/20/26
Prosecution Insights