DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/11/2026 has been entered.
Claim Interpretation
Claim interpretations raised in the office action mailed on 11/18/2025 are hereby incorporated by reference.
Response to Arguments
Applicant's arguments filed 01/20/2026 have been fully considered but they are not persuasive.
The terms “counting circuit” and “counting values”
Referring to the context of the pending claims, it seems that the Applicant outputs a value based on a comparison result. An example might be outputting a value of “0” if a data signal value is less than a threshold value and outputting a value of “1” if the data signal is equal to or larger than the threshold value. Further, a counter is well known in the art to be a circuit component counting the number of clock pulses. Applicant’s attention is respectfully directed towards such language in the claims that might hint towards different interpretations. Therefore, relying on the context of the claims discussed herein, exemplary claim 1 merely shows adjusting a current control signal based on a comparison between a threshold voltage and a data signal.
Response to Applicant’s Specific Arguments
The Applicant states that “Particularly, referring to FIG. 2B of Wang, it can be estimated that a time difference TD1 occurs between the rising time Tr of the rising edge of an odd-numbered channel ODD-CH and the falling time Tf1 of the falling edge of an even-numbered channel EVEN- CH. In this case, the slew rate adjustment circuit 350 may reduce the slew rate of the rising edge (i.e., increase the rising time) so that the rising time Tr and the falling time Tf1 can be equalized.” Then the Applicant concludes that “in Wang, the configuration used as a comparison reference for adjusting the slew rate is the falling edge in the case of a rising edge, and the rising edge in the case of a falling edge. Therefore, the cited sections of Wang do not appear to disclose or even suggest "the determination circuit comprising: a comparator outputting a comparison result generated by comparing the data signal with a threshold voltage; and a counting circuit counting a transition period of the data signal based on the comparison result and outputting counting values corresponding to a duration of the transition period; and a control circuit coupled to an output of the determination circuit and receives the countinq values from the determination circuit, the control circuit compares the countinq values with a threshold range and outputs a current control signal adjusted according to a result of comparing the counting values with the threshold range to the output buffer," as amended independent claim 1 recites.” However, Applicant’s specific argument is unclear as to whether the prior art does not teach the comparison limitation or the counting limitation as underlined herein.
Regarding the “comparison result limitation, Wang clearly states that the adjustment circuit 350 determines whether an adjustment to the slew rate is to be made. See paragraphs 35 and 36.
Regarding the “counting the transition” limitation, Wang shows that the output buffer 340 shown in FIG. 5 includes an input stage 341 and an output stage 342. The slew rate adjustment
circuit 350 may adjust/set current source configurations of tail current sources CS1 and
CS2 in the input stage 341. See paragraphs 35 and 36.
Further, it is respectfully requested that the Applicant provides clarification regarding the language “counting a transition period.” It is not clear whether the term means measuring the transition period since the context of the pending claims does not show actual counting of pulses.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (Publication number: US 2022/0013052) in view of Yang et al (Publication number: US 2024/0233652) in view of Yasuda et al (Publication number: US 2020/0252563).
Consider Claim 1, Wang et al shows a display device (see figure 3), comprising:
(a) A display panel configured to display an image by utilizing a data signal (See figure 3); (Read as display panel 30).
(b) A data driving circuit configured to supply the data signal to the display panel through a channel (see figure 3; and paragraph 28); (Read as source driver 300).
(c) A driving controller configured to control the data driving circuit (see paragraph 31); (Read as timing controller).
(d) Wherein the data driving circuit comprises: an output buffer configured to output the data signal to the channel coupled to an output of the output buffer (See figure 3; and paragraph 28); (Read as output buffer 340).
(e) A circuit connected to the channel, and configured to receive the data signal and to determine a driving capability of the output buffer by utilizing a transition period of the data signal, a comparator outputting a comparison result qenerated by comparinq the data signal with a threshold voltage; and a countinq circuit countinq a transition period of the data signal based on the comparison result and outputtinq countinq values corresponding to a duration of the transition period (see figures 2b, 2C, and 3; and paragraphs 26, 27, 32, and 33); (The slew rate adjustment circuit 350 may judge whether a slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
(f) A control circuit coupled to an output of the determination circuit and receives a result including the driving capability of the output buffer from the determination circuit a current control signal for adjusting a driving intensity of the output buffer to the output buffer based on the result including the driving capability of the output buffer received from the determination circuit , the control circuit compares the counting values with a threshold range and outputs a current control signal adjusted according to a result of comparing the countinq values with the threshold range to the output buffer (see figures 3 and 5; paragraphs 35 and 36); (The output buffer 340 shown in FIG. 5 includes an input stage 341 and an output stage 342. The slew rate adjustment circuit 350 may adjust/set current source configurations of tail current sources CS1 and CS2 in the input stage 341. When the slew rate adjustment circuit 350 determines that no adjustment is to be made to the slew rate of the output signal So, the slew rate adjustment circuit 350 may select a double current source X2 of the tail current sources CS1 and CS2).
However, Wang et al shows a circuit connected to the channel, but does not specifically show that the circuit is a “determination circuit.”
In the same field of endeavor, Yang et al shows that the circuit is a “determination circuit” at the output of the output buffer and receives the data signal output from the output buffer (see figure 4; and paragraph 97); (See the reception of an enable signal EN at the output buffer 450. Further, data voltage DV taught by Yang is equivalent to the “So” signal taught by the instant application).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate controller 460 of Yang et al into the driving circuit of Wang et al in order to provide an enable signal for the output buffers in order to output the data voltages in response to a trigger (see Yang et al; paragraph 97).
However, Wang et al in view of Yang et al do not specifically show that the determination circuit compares a duration of a transition period of the data signal output from the output buffer with a threshold range.
In related art, Yasuda et al shows that the determination circuit compares a duration of a transition period of the data signal output from the output buffer with a threshold range (see figure 12; paragraphs 210-212); (When the avalanche amplification stops, the cathode of the APD 3302 is once again charged by the voltage HVDD, and the APD 3302 returns to Geiger mode (operation C). A change in the voltage at the buffer input end caused by the operations A to C undergoes pulse shaping by the buffer 3303, and is measured by the comparator 3304 and the counter 3305. The number of photons incident on APD 3302 can be measured by repeating these operations).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Yasuda et al into the teaching of Wang et al and Yang et al in order to achieve higher moving image framerates (see Yasuda et al; paragraphs 4 and 5).
Consider Claim 2, Wang et al shows that the determination circuit comprises: a counting circuit configured to count the transition period to output a counting value (see figures 2b, 2C, and 3; and paragraphs 26, 27, 32, and 33); (The slew rate adjustment circuit 350 may judge whether a slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
Consider Claim 3, Wang et al show that the transition period includes: a rising transition period set to a time period from a first threshold point where the data signal reaches a low threshold voltage to a second threshold point where the data signal reaches a high threshold voltage; and a falling transition period set to a time period from a third threshold point where the data signal reaches the high threshold voltage to a fourth threshold point where the data signal reaches the low threshold voltage (see figures 2b, 2C, and 3; and paragraphs 26, 27, 32, and 33); (The slew rate adjustment circuit 350 may judge whether a slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
Consider Claim 4, Wang et al shows that the determination circuit further comprises: a first comparator configured to compare the data signal and the high threshold voltage to output a first comparison result; and a second comparator configured to compare the data signal and the low threshold voltage to output a second comparison result, and wherein the counting circuit is configured to determine a counting start point and a counting end point by utilizing the first and second comparison results (see paragraphs 40 and 46); (The slew rate adjustment circuit 350 is coupled to a second input terminal of the AND gate G81, a second input terminal of the AND gate G83, a second input terminal of the AND gate G85, a second input terminal of the OR gate G82, a second input terminal of the OR gate G84 and a second input terminal of the OR gate G86, so as to provide the comparison result CR of the current sub-pixel data and the next sub-pixel data. It is assumed herein that the comparison result CR with a high logic level indicates “the output signal So will have a rising edge,” and the comparison result CR with a low logic level indicates “the output signal So will have a falling edge).”
Consider Claim 5, Wang et al shows that the counting circuit is configured to: output a first counting value by counting a duration of the rising transition period; and output a second counting value by counting a duration of the falling transition period (see figures 2b, 2C, and 3; and paragraphs 26, 27, 32, and 33); (The slew rate adjustment circuit 350 may judge whether a slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
Consider Claim 6, Wang et al shows that the control circuit is configured to: compare the first and second counting values with a threshold range; when all the first and second counting values are within the threshold range, output the current control signal with a reference value; and when at least one of the first counting value or the second counting value is outside the threshold range, output the current control signal with a compensation value different from the reference value (see paragraphs 47 and 48); (The slew rate adjustment circuit 950 may judge whether the slew rate to be adjusted is at the rising edge or the falling edge of the output signal So. Based on a notification from the slew rate adjustment circuit 950, the slew rate adjustment circuit 960 may judge whether the slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
Consider Claim 7, Wang et al shows that the transition period is set to a time period from a first threshold point where the data signal reaches a low threshold voltage to a second threshold point where the data signal reaches a high threshold voltage, and wherein the counting circuit is configured to: output the counting value by counting a duration of the transition period (see figures 2b, 2C, and 3; and paragraphs 26, 27, 32, and 33); (The slew rate adjustment circuit 350 may judge whether a slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
Consider Claim 8, Wang et al shows that the determination circuit further comprises: a first comparator configured to compare the data signal and the high threshold voltage to output a first comparison result; and a second comparator configured to compare the data signal and the low threshold voltage to output a second comparison result, and wherein the counting circuit is configured to determine a counting start point and a counting end point by utilizing the first and second comparison results (see figures 3 and 5; paragraphs 35 and 36); (The output buffer 340 shown in FIG. 5 includes an input stage 341 and an output stage 342. The slew rate adjustment circuit 350 may adjust/set current source configurations of tail current sources CS1 and CS2 in the input stage 341. When the slew rate adjustment circuit 350 determines that no adjustment is to be made to the slew rate of the output signal So, the slew rate adjustment circuit 350 may select a double current source X2 of the tail current sources CS1 and CS2).
Consider Claim 9, Wang et al shows that the control circuit is configured to: compare the counting value with a threshold range; when the counting value is within the threshold range, output the current control signal with a reference value; when the counting value is outside the threshold range, output the current control signal with a compensation value different from the reference value (see paragraphs 47 and 48); (The slew rate adjustment circuit 950 may judge whether the slew rate to be adjusted is at the rising edge or the falling edge of the output signal So. Based on a notification from the slew rate adjustment circuit 950, the slew rate adjustment circuit 960 may judge whether the slew rate to be adjusted is at the rising edge or the falling edge of the output signal So).
Consider Claim 10, Yang et al shows that the determination circuit is configured to receive an enable signal or a disable signal from the driving controller, to be activated in response to the enable signal, and to be deactivated in response to the disable signal (see figure 4; and paragraph 97); (See the reception of an enable signal EN at the output buffer 450. Further, data voltage DV taught by Yang is equivalent to the “So” signal taught by the instant application).
Consider Claims 11 and 12, Wang et al shows that the data driving circuit further comprises: a switching circuit configured to switch a connection between the channel and the determination circuit in response to a switching signal, wherein the driving controller is configured to provide the switching signal to the switching circuit (see paragraph 51).
Consider Claim 13, Yang et al shows that the channel comprises a plurality of channels, wherein the output buffer comprises a plurality of output buffers respectively connected to the plurality of channels, and wherein the determination circuit is connected to some channels from among the plurality of channels (see figure 4).
Consider Claim 14, Wang et al shows that the determination circuit comprises: a first determination circuit connected to a first channel from among the plurality of channels, and configured to output a first result value associated with a transition period of a first data signal output to the first channel; a second determination circuit connected to a second channel from among the plurality of channels, and configured to output a second result value associated with a transition period of a second data signal output to the second channel; and a third determination circuit connected to a third channel from among the plurality of channels, and configured to output a third result value associated with a transition period of a third data signal output to the third channel (see figure 7); (see the slew adjustment circuit adjusting the output signal on multiple channels).
Consider Claim 17, Yang et al shows that each of the first to third determination circuits receives an enable signal or a disable signal from the driving controller, is activated in response to the enable signal, and is deactivated in response to the disable signal (see figure 4; and paragraph 97); (See the reception of an enable signal EN at the output buffer 450. Further, data voltage DV taught by Yang is equivalent to the “So” signal taught by the instant application).
Consider Claims 18 and 19, Wang et al shows that the data driving circuit further comprises: a first switching circuit configured to switch a connection between the first channel and the first determination circuit in response to a first switching signal; a second switching circuit configured to switch a connection between the second channel and the second determination circuit in response to a second switching signal; and a third switching circuit configured to switch a connection between the third channel and the third determination circuit in response to a third switching signal, wherein the driving controller is configured to provide the first to third switching signals to the data driving circuit (see figure 7); (see the slew adjustment circuit adjusting the output signal on multiple channels).
Consider Claim 20, Wang et al shows that the control circuit is configured to: supply the current control signal to the plurality of output buffers in common (see figure 3).
Allowable Subject Matter
Claims 15-16 are allowed.
The best prior art of record, i.e., Wang et al (Publication number: US 2022/0013052) in view of Yang et al (Publication number: US 2024/0233652) in view of Yasuda et al (Publication number: US 2020/0252563) do not specifically show the limitations of “wherein the channel comprises a plurality of channels, wherein the output buffer comprises a plurality of output buffers respectively connected to the plurality of channels, wherein the determination circuit is connected to some channels from among the plurality of channels, wherein the determination circuit comprises: a first determination circuit connected to a first channel from among the plurality of channels, and configured to output a first result value associated with a transition period of a first data signal output to the first channel; a second determination circuit connected to a second channel from among the plurality of channels, and configured to output a second result value associated with a transition period of a second data signal output to the second channel; and a third determination circuit connected to a third channel from among the plurality of channels, and configured to output a third result value associated with a transition period of a third data signal output to the third channel.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 02/20/2026