DETAILED ACTION
Claims 1,11 are amended. Claims 2,12 were previously canceled. Claims 21-22 are new.
Claims 1, 3-11, 13-22 are pending.
Priority: 8/22/2024
Assignee: Ampere
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/22/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Claim(s) 1, 3-11, 13-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1, 11 are rejected for reciting a limitation that is unclear, inconsistent and indefinite.
Amended Claim 1 recites, ‘wherein the page table entry includes the virtual address, the physical address, an access permission, and a memory type attribute corresponding to the virtual address’.
The spec does not recite this limitation.
Para-0070 of the spec recites, ‘In Fig. 8, a page table entry for the partial translation cache includes a tag segment….and a data segment…..The tag segment includes a virtual address and the data segment includes, for example, four physical addresses….’.
The claim recites ‘the physical address’ (singular), but the spec states the data segment includes ‘four physical addresses’, creating a scope mismatch.
The claim recites additional parameters such as 'an access permission' and 'a memory type attribute,' but the spec fails to provide support for these parameters in the context of the page table entry's data segment.
Para-0039 of the spec recites, ‘Attributes indicate such things as the type of memory being accessed (e.g., device, normal, etc.)’. Consequently, it is unclear how ‘memory type’ is associated with ‘type of memory being accessed’. It is unclear how the OS maps specific memory types to specific virtual address ranges via page table entries.
The claim mixes page table entry parameters of the partial translation cache (spec, Fig. 8) with TLB data segment attributes (See spec, Fig. 4, Para-0045), without defining where the boundaries lie.
Since the claim improperly incorporates TLB-specific data segment attributes into the page table entry of the partial translation cache without adequate written descriptive support or structural clarity, the scope of claim 1 is uncertain. Hence claim 1 is indefinite and rejected. Claim 11 has the same issue and is also rejected.
2.Amended Claims 1, 11 are rejected for reciting a limitation that is unclear, ambiguous and indefinite.
Claim 1 recites, ‘accessing a physical memory location corresponding to the physical address based on the access permission and the memory type attribute’.
The claim recites elements and active steps —specifically ‘reading a physical address corresponding to the virtual address from a page table entry of the partial translation cache’ —that are inconsistent with and unsupported by the spec's disclosure of a bypass context.
In Fig. 3, Para-0037, the spec at stages 330a to 330n explicitly teaches that ‘if a transaction maps to a bypass context, translation is not required…. and no address translation is performed' and ‘default attributes are applied’ (what are they?).
But the claim positively requires reading a physical address and performing an access based on attributes (permissions, memory type) retrieved from a cache entry (when were they set??).
The spec fails to provide written description for setting/using the claimed ‘access permission’ and ‘memory type attribute’ during the access step, suggesting lack of possession. In addition, what the ‘default attributes’ are and how ‘default attributes are applied’ also lack descriptive support.
Therefore it is unclear whether a bypass mode (where no translation occurs) is encompassed within the claim scope, rendering the metes and bounds of the claim vague and indefinite regarding how the ‘reading’, applying ‘default attributes’, and ‘accessing’ operate during a bypass condition. Hence claim 1 is rejected. Claim 11 has the same issue and is also rejected.
Note: The misread flowchart creates a disconnect between what is depicted in Fig. 3 of the spec and what is recited in the claim.
3.Claims 21, 22 are rejected for reciting a limitation that is unclear, inconsistent and indefinite.
Claim 21 recites 'the partial translation cache stores virtual address to physical address translations of intermediate levels of a physical address page table'.
The claim recites ‘physical address page table’ for the intermediate levels, but as shown below, the spec describes storing ‘VA to PA translations of the non-leaf levels of the Stage-1 page table’, creating a contradiction.
Para-0055 of the spec recites, ‘The Stage-1 partial translation cache can store the full VA to PA translations of the non-leaf levels of the Stage-1 page table. When Stage-2 translation is enabled, the MMU can directly read a Stage-1 translation table entry instead of….the Stage-2 page walk'.
The claim recites ‘physical address page table’ that lacks definition in the spec and is inconsistent with the structural description of ‘Stage-1 page table’. It is unclear whether the intermediate levels belong to a physical address page table or a Stage-1 virtual address translation table.
In other words, it is unclear how intermediate levels of a 'physical address page table' relate to the ‘Stage-1 page table’ translations described in the spec. This inconsistency between the claim language and the spec renders the scope of the claim uncertain and indefinite. Hence claim 21 is rejected. Claim 22 has the same issue and is also rejected.
Note: Though not explicitly disclosed, based on Paras-0029,0030 of the spec, non-leaf levels are considered equivalent to intermediate levels.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Claim(s) 1, 3-11, 13-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1.Amended Claims 1, 11 are rejected for reciting a limitation that is unsupported by the spec.
Claim 1 recites, ‘receiving a virtual address for a partial translation cache, wherein the ……partial translation cache stores translations from virtual addresses to physical addresses, reading a physical address corresponding to the virtual address from a page table entry of the partial translation cache’.
The spec does not recite this limitation. The claim recites the limitation of 'reading a physical address corresponding to the virtual address from a page table entry of the partial….cache', whereas the spec only describes reading the physical address from 'one or more page table entries of one or more levels of the partial….cache' (See Para-0006 of the spec).
The spec fails to provide descriptive support that conveys that the inventor was in possession of the specific paragraph restricted to a single page table entry, as distinguished from broader multiple page table entries across multiple levels.
Because the amended limitation is not a true narrowing of the original disclosure but rather a new idea not originally described, claim 1 recites new matter and is rejected. Claim 11 has the same issue and is also rejected. For examination, the spec is followed.
2.Amended Claims 1, 11 are rejected for reciting a limitation that is unsupported by the spec.
Claim 1 recites, ‘the partial translation cache stores translations from virtual addresses to physical addresses; reading a physical address corresponding to the virtual address from a page table entry of the partial translation cache’.
The limitation conflicts with the spec because Para-0054 of the spec recites, 'a partial translation cache is a cache that stores the contents of all the page table entries accessed during a page walk prior to the leaf page table entry. The contents of the leaf page table entry are stored in a TLB’.
The claim states the partial translation cache reads a physical address from a page table entry stored within it. But the spec defines the partial translation cache strictly as storing entries prior to the leaf entry, with leaf entries going to the TLB (a leaf entry provides the final virtual-to-physical address mapping).
The spec does not support storing the final physical address translation inside the partial translation cache because it assigns that role to the TLB.
The spec does not reasonably convey that the inventor possessed a partial translation cache configured to store and read page table entries containing the final physical address as recited in the claim.
Because the spec explicitly limits the partial translation cache to storing non-leaf page table entries while the limitation improperly broadens it to read physical addresses directly from its own entries, claim 1 recites a scope unsupported by the spec and is rejected. Claim 11 has the same issue and is also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 8-11, 13-14, 16, 18-20 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Sandberg-1 (20230409487) in view of Brucker (20250190363) and Swaine (20230289294).
As per Claim 1, Sandberg-1 discloses a method of operating a memory management unit (MMU) (Sandberg-1, [0115 – In Fig. 1, processing element/PE 104 has a memory management unit/MMU 112 which functions as address translation circuitry for translating input addresses, e.g. virtual addresses specified by instructions executed by the PE 104, into output addresses, e.g. physical addresses identifying locations within the memory system]), comprising:
receiving a virtual address for a partial translation cache (Sandberg-1, [0128 – In Fig. 4, the address translation circuitry receives the virtual address and performs an initial lookup in the page walker cache 400/PWC]),
wherein the partial translation cache (Sandberg-1, [0125 – In Figs. 1, 3, an address translation cache 114 which stores partial address translation data is a PWC. The PWC can store both full and partial address translation data]) stores translations from virtual addresses to physical addresses (Sandberg-1, [0160 - The full address translation data can be indicative of a translation from a VA to an IPA, an IPA to a PA, or a VA to a PA, the partial address translation data could also be indicative of mappings from either a VA or an IPA to an IPA or a PA]);
reading a physical address corresponding to the virtual address (Sandberg-1, [0161 - The output address identified by full address translation data is a physical address obtained from a stage-2 translation table]) from a page table entry (Sandberg-1, [0003 - Each PTE of the multi-level page table structure can be a branch PTE or a leaf PTE]) of the partial translation cache (Sandberg-1, [0128 - In Fig. 4, the lookup/read in PWC 400 will result in a hit if any sequential most significant portions of the input address hit in the cache. Therefore, there will be a cache hit if the most significant N-bit portion of the VA, e.g. the L0 index portion 305 in Fig. 3, hits in PWC 400]; [0126 - In Fig. 3, the information within descriptor 347 is used to produce the full address translation data, and the entry of the page table 345 storing the block descriptor is a leaf PTE]),
wherein the page table entry includes the virtual address, the physical address, an access permission (Sandberg-1, [0115 – In Fig. 1, the page table structures define the address mappings between input and output addresses and also define memory access permissions which define whether certain software processes executing on PE 104 are allowed to access certain addresses, implying memory type attribute]; [0116 - Fig. 1 shows one requestor device]), and a memory type attribute corresponding to the virtual address (Sandberg-1, [0049 - Full address translation data specifies the output address/PA specified by a leaf page table entry corresponding to a given input address/VA]);
accessing a physical memory location corresponding to the physical address (Sandberg-1, [0161 - The output address identified by full address translation data is a physical address obtained from a stage-2 translation table]) based on the access permission and the memory type attribute (Sandberg-1, [0121 - In Fig. 1, MMU 112 controls memory access permission checks and performing address translations between virtual addresses specified by the load/store unit 246 based on operands of data access instructions and physical addresses identifying storage locations of data in the memory system; Here the load/store unit detects the type of a memory access]).
The spec does not disclose a PTE of the partial translation cache comprising a VA, PA, permissions and a memory type attribute.
Brucker discloses,
wherein the page table entry includes ([See 112(b)]) the virtual address (Brucker, [0065 – In Fig. 3, step 302 receiving a memory access request specifying a VA from the processing circuitry 11]), the physical address, an access permission (Brucker, [Fig. 6: TLB 14]; [0053 – In Fig. 1, the page table structures include page descriptors defining the address mappings between virtual and physical addresses and also define memory access permissions that define whether certain software processes executing on processing circuitry 4 are allowed to access certain addresses]), and a memory type attribute corresponding to the virtual address (Brucker, [0054 - Fig. 1 shows one requester device]; [0030 - The completion of the memory access may be indicated differently depending on the type of memory access. For example, a load/read access is completed when the target data has been loaded from memory and forwarded to the requesting device, whereas a store/write access is completed when the target data has been written in memory; This implies that a write access to a cacheable memory type updates the cache]);
accessing a physical memory location corresponding to the physical address (Brucker, [0064 - The VA is converted into a physical page number and hence allowing the required physical address in memory to be identified. This enables the particular item of data corresponding to the VA to be accessed by the processing circuitry 11 by issuing the required PA to memory 40 via interconnect 30]) based on the access permission (Brucker, [0053 - stage 2 translations, IPA to PA, are set by more secure processes/privileged permissions such as a hypervisor]) and the memory type attribute (Brucker, [0030 - The completion of the memory access may be indicated differently depending on the type of memory access]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the control circuitry of Brucker into the partial translation cache of Sandberg-1, for the benefit of using an address translation cache to store recently translated address translations to utilize the available capacity in the cache as efficiently as possible (Brucker, 0022).
Swaine discloses,
accessing a physical memory location corresponding to the physical address (Swaine, [0103 - The addressing of a page table entry refers to the physical address of that page table entry, as in Fig. 5]; [0087 - TCU 132 derives the required VA to PA translation by accessing data stored in memory using page table walk/PTW]) based on the access permission (Swaine, [0051 - The address processing circuitry comprises permission circuitry, in which the information relating to an input memory address defines at least an access permission associated with the input memory address]) and the memory type attribute (Swaine, [0010 - detecting whether indicator data is set]; [Fig. 13: step 1310, indicator data set? Skip]; [0081 - A page table based approach is used to obtain permission data, attribute data etc., in relation to a translated address/PA; This implies that the memory access type, read/write, is verified against the permissions and the indicator data, ensuring that optimized lookups respect safety and protection constraints]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 3, the rejection of claim 1 is incorporated, and Sandberg-1, Brucker, Swaine disclose,
converting the virtual address to an intermediate physical address within the partial translation cache (Swaine, [0081 – partial translation]; [0079 – In Fig. 2, a virtual address/VA required by an executing program or other system module such as PE 100 is translated to an intermediate physical address/IPA by the stage 1 MMU]);
and converting the intermediate physical address to the physical address within the partial translation cache (Swaine, [0079 - The IPA is translated to a physical address/PA by the stage 2 MMU. A hypervisor has oversight of the stage 2, IPA to PA translation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 4, the rejection of claim 1 is incorporated, and Sandberg-1, Brucker, Swaine disclose,
wherein reading the physical address comprises:
reading a first set of bits of the virtual address (Swaine, [Fig. 6, step 600, Get Level 0 base address]; [0094 – In Fig. 5, a first portion 312 of virtual address/VA 222, being the 9 most significant bits]; [0094 – As per Fig. 5, to obtain a first entry in the page table hierarchy, in ‘level 0 table’ 310, a base address stored in a base address register 300 corresponding to TTBR 135 of Fig. 1 is obtained at Fig. 6:step 600]);
converting the first set of bits of the virtual address into a first portion of the physical address (Swaine, [0094 - A first portion 312 of VA 222, being the 9 most significant bits, is added to the base address as an offset, at Fig. 6:step 610 so as to provide the IPA of an entry 314 in table 310]);
determining whether the first portion of the physical address matches a first page table entry of a first level of the partial translation cache (Swaine, [0094 – In Fig. 5, in order to access entry 314 indicated by the IPA, a PA indicating the location of the entry in physical memory is needed. Therefore, at Fig. 6:step 620, the IPA of the page table entry 314 is supplied to the stage 2 translation process for translation into a corresponding PA. When the corresponding PA is received, the relevant page table entry is looked up in physical memory or in the level 2 walk cache 137, if the relevant page is cached, at step 630]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 6, the rejection of claim 4 is incorporated, and Sandberg-1, Brucker, Swaine disclose,
wherein reading the physical address comprises:
determining that the first portion of the physical address does not match the first page table entry of the first level of the partial translation cache (Swaine, [Fig. 6: step 630, is the relevant page cached ? No]; [0095 – In Fig. 6:step 640, a detection is made if ‘level 3’ has been reached in the page table hierarchy. If not, control passes to Fig. 6:step 650 at which the retrieved page table entry is used as a base address of a next table in the hierarchy]);
reading a second set of bits of the virtual address (Swaine, [0095 – In Fig. 5, page table entry 324 provides a base address to the next level table in the hierarchy, a ‘level 2 table’ 330. Control returns to step 610]; [0096 - At the second iteration of Fig. 6:step 610, a further part 322 of VA 222, or next 9 bits [38:30] of VA 222, forms an offset from the base address of table 330]);
converting the second set of bits of the virtual address to a second portion of the physical address (Swaine, [0096 – As per Fig. 5, the offset from the base address of table 320 provides the IPA of entry 324 in the table 320. At Fig. 6:step 620, the IPA of the page table entry 324 is supplied to the stage 2 translation process for translation into a corresponding PA]);
determining whether the second portion of the physical address matches a second page table entry of a second level of the partial translation cache (Swaine, [Fig. 6: step 630, is the relevant page cached?]; [0096 - The IPA is subjected to stage 2 translation to provide a PA which can be looked up to obtain the base address of Fig. 5:‘level 2 table’ 330]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker, for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 8, the rejection of claim 6 is incorporated, and Sandberg-1, Brucker, Swaine disclose,
wherein reading the physical address comprises:
determining that the second portion of the physical address does not match the second page table entry of the second level of the partial translation cache (Swaine, [0094 – In Fig. 6: step 630, when the corresponding PA is received, the relevant page table entry is looked up in physical memory or in the level 2 walk cache 137 if the relevant page is cached]; [Fig. 6: step 630, is the relevant page cached ? No]; [0095 – In Fig. 6:step 640, a detection is made if ‘level 3’ has been reached in the page table hierarchy]; [0097 - When the steps 630 and 640 are carried out in respect of a PTE defined by an IPA 344 in Fig. 5:table 340, the answer to the detection at Fig. 6: step 640 is ‘yes’]);
reading a third set of bits of the virtual address (Swaine, [0095 – In Fig. 5, page table entry 334 provides a base address to the next level table in the hierarchy, a ‘level 3 table’ 340. Control returns to step 610]; [0096 - At the third iteration of Fig. 6:step 610, a further part 322 of VA 222, or next 9 bits [29:21] of VA 222, forms an offset from the base address of table 330]);
converting the third set of bits of the virtual address to a third portion of the physical address (Swaine, [Fig. 6: step 660, remainder of VA as page offset]; [0096 – As per Fig. 5, the offset from the base address of table 330 provides the IPA of entry 334 in the table 340]);
determining whether the third portion of the physical address matches a third page table entry of a third level of the partial translation cache (Swaine, [0096 - The IPA is subjected to stage 2 translation to provide a PA which can be looked up to obtain the base address of Fig. 5:‘level 3 table’ 340]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker, for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 9, the rejection of claim 8 is incorporated, and Sandberg-1, Brucker, Swaine disclose,
wherein reading the physical address comprises:
determining that the third portion of the physical address matches the third page table entry of the third level of the partial translation cache (Swaine, [0097 - The page table entry indicated by IPA 344 provides a page address and access permissions relating to a physical memory page. The remaining portion 352 of VA 222, the least significant 12 bits [11:0] provides a page offset 502 to a target address 500 within the memory page defined by the page table entry at IPA 344]);
reading the physical address from the third page table entry of the third level of the partial translation cache (Swaine, [Fig. 6: step 670, return required PA/IPA]; [0097 – In Fig. 6:step 660, the combination of the least significant portion of VA 222 and the final page table entry, from the ‘level 3 table’ 340 provides at step 670 the PA/physical address 500 as a translation of VA 222, carried out by the stage 2 MMU]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker, for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 10, the rejection of claim 1 is incorporated, and Sandberg-1, Brucker, Swaine disclose,
wherein the virtual address (Swaine, [0083 – In Fig. 1, during operation of PE 100, TLB 102 receives VA 220 relating to a required memory access, read or write]) is associated with a guest system (Swaine, [0079 - virtual machines running on the same processor; Here each VM is a guest system running applications]; [0002 - Each application running on an operating system can have its own virtual memory mappings]),
and the physical address is associated with a host system (Swaine, [Fig. 14: Host OS, Host Hardware]; [0151 – In Fig. 14, a simulator/guest machine may run on host processor 1730]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the two-stage MMU of Swaine into the partial translation cache of Sandberg-1, Brucker, for the benefit of the two-state MMU comprising a stage 1 MMU and a stage 2 MMU. A virtual address required by an executing program is translated to an intermediate physical address by the stage 1 MMU. The IPA is translated to a physical address by the stage 2 MMU. Thus the two-stage MMU performs two-stage address translation (Swaine, 0079).
As per Claim 11, Sandberg-1 discloses an apparatus (Sandberg-1, [0003 - An apparatus comprising: an address translation cache comprising a plurality of cache entries, each cache entry to store address translation data dependent on one or more PTEs of a multi-level page table structure in memory, wherein each PTE of the multi-level page table structure is a branch PTE or a leaf PTE]), comprising:
one or more memories (Sandberg-1, [0120 – In Fig. 2, a load/store unit 246 for performing load/store operations to access data in a memory system 207, 250, 252, 132]);
and one or more processors (Sandberg-1, [0116 – In Fig. 1, system 102 could have two or more devices PEs, which may include further PEs, such as CPUs]);
a memory management unit (MMU) coupled to the one or more processors and the one or more memories (Sandberg-1, [0115 – In Fig. 1, MMU 112 functions as address translation circuitry for translating input addresses, e.g. virtual addresses into output addresses, e.g. physical addresses identifying locations within the memory system]), the MMU configured to:
The remaining limitations are similar to claim 1 and therefore the same mappings are incorporated.
As per Claim 13, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 14, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 16, it is similar to claim 6 and therefore the same mappings are incorporated.
As per Claim 18, it is similar to claim 8 and therefore the same mappings are incorporated.
As per Claim 19, it is similar to claim 9 and therefore the same mappings are incorporated.
As per Claim 20, it is similar to claim 10 and therefore the same mappings are incorporated.
Claims 5, 7, 15, 17 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Sandberg-1 (20230409487) in view of Brucker (20250190363), Swaine (20230289294) and Sandberg-2 et al (20220188245).
As per Claim 5, the rejection of claim 4 is incorporated, and Sandberg-1, Brucker, Swaine disclose a partial translation cache.
Sandberg-2 further discloses,
wherein reading the physical address comprises:
determining that the first portion of the physical address matches the first page table entry in the first level of the partial translation cache (Sandberg-2, [Fig. 5: step 100, Obtain PTE at level n; Here n=1]; [0104 – In Fig. 5, step 100 the page table walk circuitry 16,36 obtains the relevant PTE at level n of the page table structure. To identify the address of the required PTE, the page table walk circuitry adds a level-n page table base address to an offset determined from the level-n index portion 44-n of the Fig. 2:target address/VA. If n=0, level-0 base address is obtained from the TTBR, while if n>0, then the base address of the level-n page table is identified based on an address pointer in a parent PTE at level n−1. Thus the address of the required PTE is identified]);
and reading the physical address from the first page table entry of the first level of the partial translation cache (Sandberg-2, [Fig. 5: step 102, PTE type indicated by parent PTE at level-1? Absolute]; [Fig. 5: step 104, Determine address pointer from absolute address specified in PTE]; [0105 - If the PTE at level n is a block/leaf PTE then this would terminate the traverse of the page table structure if the translated address is a PA]; [0054 - The final level of page table for a given branch of the page table structure may include a block/leaf entry, which specifies an address pointer for identifying the translated memory address which corresponds to the target address for which the translation was requested]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the absolute address of Sandberg-2 into the hierarchical page table levels of Sandberg-1, Brucker, Swaine, for the benefit of using a memory management circuitry, where each page table entry identifies an address pointer for identifying one of: a translated address, and an address of a child page table at a next level of the page table structure (Sandberg-2, 0003).
As per Claim 7, the rejection of claim 6 is incorporated, and Sandberg-1, Brucker, Swaine, Sandberg-2 disclose,
wherein reading the physical address comprises:
determining that the second portion of the physical address matches the second page table entry of the second level of the partial translation cache (Sandberg-2, [Fig. 5: step 100, Obtain PTE at level n; Here n=2]; [0104 – In Fig. 5, step 100 the page table walk circuitry 16,36 obtains the relevant PTE at level n of the page table structure. To identify the address of the required PTE, the page table walk circuitry adds a level-n page table base address to an offset determined from the level-n index portion 44-n of the Fig. 2:target address/VA. If n=0, level-0 base address is obtained from the TTBR, while if n>0, then the base address of the level-n page table is identified based on an address pointer in a parent PTE at level n−1. Thus the address of the required PTE is identified]);
and reading the physical address from the second page table entry of the second level of the partial translation cache (Sandberg-2, [Fig. 5: step 102, PTE type indicated by parent PTE at level-1? Absolute]; [Fig. 5: step 104, Determine address pointer from absolute address specified in PTE]; [0105 - If the PTE at level n is a block/leaf PTE then this would terminate the traverse of the page table structure if the translated address is a PA]; [0054 - The final level of page table for a given branch of the page table structure may include a block/leaf entry, which specifies an address pointer for identifying the translated memory address which corresponds to the target address for which the translation was requested]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the absolute address of Sandberg-2 into the hierarchical page table levels of Sandberg-1, Brucker, Swaine, for the benefit of using a memory management circuitry, where each page table entry identifies an address pointer for identifying one of: a translated address, and an address of a child page table at a next level of the page table structure (Sandberg-2, 0003).
As per Claim 15, it is similar to claim 5 and therefore the same mappings are incorporated.
As per Claim 17, it is similar to claim 7 and therefore the same mappings are incorporated.
Claims 21, 22 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Sandberg-1 (20230409487) in view of Brucker (20250190363), Swaine (20230289294), Sandberg-2 et al (20220188245) and Mukherjee et al (20160140048).
As per Claim 21, the rejection of claim 1 is incorporated and Sandberg-1, Brucker, Swaine disclose a partial translation cache.
Sandberg-2 further discloses,
wherein the partial translation cache (Sandberg-2, [0103 - A TLB may cache partial translations]; [0051 – In Fig. 1:core 4, MMU 12 includes TLB 14, which is a cache of some page table entries of the page table structure(s). The MMU also includes page table walk circuitry 16 for performing a page table walk operation to obtain PTEs from the page table structure(s) stored in memory, for use in the address translation]) stores virtual address to physical address translations of intermediate (Sandberg-2, [0104 - Fig. 5 shows the steps performed if a page table access is required for a certain level, n, of the page table structure]) levels (Sandberg-2, [0080 – The format of a table PTE/branch entry is shown in the upper part of Fig. 3]; [0081 - In Fig. 3, if the table flag 62 is 1 then the PTE is a table PTE/branch/non-leaf]; [0083 - In Fig. 3, a table PTE includes a next-level PTE type indicator 66 (Rn+1); These parameters help to determine ‘all non-leaf levels’/intermediate levels]; [0080 – Fig. 3 shows a structure of a PTE 42 which is used to implement relative address pointers. The format of a table PTE/branch entry is shown in the upper part of Fig. 3]; [0019 - PTEs which have an address pointer pointing to a child page table at a next level of the page table structure are called table entries or branch/non-leaf entries]; [0054 – In Fig. 2, PTEs 42 which point to a subsequent page table are known as table entries or branch/non-leaf entries, thereby implying identifying ‘non-leaf levels’]) of a physical address page table (Sandberg-2, [Fig. 3 shows a non-leaf/branch PTE of the physical address page table]; [0104 – In Fig. 5, if the current level of the page table walk is associated with stage 2 of a 2-stage MMU which translates from IPA to PA, the address obtained from the level-n base address Tn and the level-n index portion 44-n is a physical address which can be specified in a access request to read the required PTE from the memory. If the translation relates to stage 1 of a 2-stage MMU, the acquired address of the PTE is an IPA which then may require further stage 2 translation to obtain the physical address of the required PTE]; [0016 – In Fig. 6, a block table is used to indicate the base address and size of a bounding address region, thereby identifying non-leaf/intermediate levels]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the branch entries of Sandberg-2 into the partial translation cache of Sandberg-1, Brucker, Swaine for the benefit of identifying PTEs which have an address pointer pointing to a child page table at a next level of the page table structure as table entries or branch entries. The PTE which points to a given child page table is a parent PTE of that child page table, and is a parent PTE of the child PTEs within the child page table (Sandberg-2, 0019).
Mukherjee clarifies that the non-leaf levels of Sandberg-2 correspond to intermediate levels as follows,
wherein the partial translation cache (Mukherjee, [0032 - A single, unified walker cache including entries for a number of page table levels]; [Fig. 2: walker cache 232]; [0073 - The intermediate page address 466 represents a partially translated physical memory address]) stores virtual address to physical address translations of intermediate levels (Mukherjee, [0069 – In Fig. 4, walker cache 232 maintains a set of recently used intermediate translations, i.e., translations from a portion of a virtual memory address to an intermediate page address]) of a physical address page table (Mukherjee, [0070 – In Fig. 4, the walker cache 232 includes a number of entries/rows 460. Each entry represents an intermediate translation and includes a table level value 462, a cached virtual memory address portion 464, and an intermediate page address 466 corresponding to the cached virtual memory address portion 464]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the unified walker cache of Mukherjee into the partial translation cache of Sandberg-1, Brucker, Swaine, Sandberg-2 for the benefit of increasing the speed of virtual to physical memory address translation (Mukherjee, 0069).
As per Claim 22, it is similar to claim 21 and therefore the same mappings are incorporated.
Response to Arguments
The Applicant's arguments filed on June 22, 2026 have been fully considered, but moot in view of the new ground of rejection.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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