Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendment, filed 06/12/2026, has been received, entered into the record, respectfully and fully considered.
By this amendment, claims 1-6, 8, 11, 13-16, and 18 have been amended, Claim 12 has been canceled. Thus, claims 1-11, and 13-20 have been examined.
Any objection, claim interpretation and claim rejection not repeated below is withdrawn due to Applicant's amendments.
Response to Arguments
Applicant's arguments filed 06/12/2026 have been fully considered and have been addressed as follows.
Applicant argued on page 20 of the remarks:
Jo merely adjusts the calculation speed based on the UCN# and ITR#. Jo does
not disclose or suggest adjusting the calculation speed based on the progress stage of the decoding operation, as structurally and functionally recited in Feature 1 of the claimed invention.
In response to Applicant’s Argument, Examiner would like to point out that Jo [0035], teaches “When it is determined that the decoding operation has passed, the syndrome checker 120 may transmit a UCN value or a number of UCNs UCN# and a number of iterations (i.e., the iteration number) ITR#, which are detected during the iterations of the decoding operation, to the iteration calculator 110.” Any step related to decoding is part of progress stage of the decoding operation.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
"a preliminary operation unit" in claim 11
"a plurality of unit preliminary operation units" in claim 11
"a speed setting unit" in claim 11
"a determination unit" in claim 11
"a main operation unit" in claim 11
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation:
Claim 11 recites the limitation of "a preliminary operation unit", and which has a corresponding structure as seen in Fig.6, Fig.17, 622, [0090] The LDPC decoder 600A may include a preliminary operation unit 622.
Claim 11 recites the limitation of "a plurality of unit preliminary operation units ", and which has a corresponding structure as seen in Fig.17, 622A; [0194]-[0199].
Claim 11 recites the limitation of "a speed setting unit ", and which has a corresponding structure as seen in Fig.16A, 640; [0185]-[0187].
Claim 11 recites the limitation of "a main operation unit ", and which has a corresponding structure as seen in Fig.6, 612; [0086]-[0088].
A review of the specification shows "a determination unit" has NO corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim limitations "a determination unit" configured to perform various functions in claim 11 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the sufficient corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While these claim limitations s are disclosed in the specification, they are not described sufficient structure and/or a specific algorithm for performing the claimed various functions, for example, various boxes labeled as “a determination unit” in Fig.5, 530.. Therefore, the claim 11 is indefinite and is rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitation "a determination unit" configured to perform various functions in Claim 11 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the sufficient corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While these claim limitations s are disclosed in the specification, they are not described sufficient structure and/or a specific algorithm for performing the claimed various functions, for example, various boxes labeled as “a determination unit" " in Fig.5, 530. Therefore, the claim 11 is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Any claim not specifically mentioned above, is rejected due to its dependency on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-13 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al., US 20210359710, hereinafter JO, in view of Bazarsky et al., US 20180175889, hereinafter Bazarsky.
As per claim 1, JO teaches A method for decoding in a memory system comprising a memory device and a controller, the method comprising:
establishing a plurality of check nodes and a plurality of variable nodes corresponding to the plurality of check nodes of a codeword; (FIG.1, [0027] may output a message MSG by decoding a codeword CDWD output from a memory device; [0061], FIG.7, S71)
setting a preliminary operation speed by controlling a count of enabled unit preliminary operation units per unit time.
performing the preliminary operation on the plurality of the variable nodes according to the preliminary operation speed to generate predictive error information of each of the plurality of the variable nodes, by the enabled unit preliminary operation units included in the controller; and
wherein the preliminary operation speed is set to increase as a progress rate of the preliminary operation or a progress rate of the main decoding operation increases.
([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed; [0036] The iteration calculator 110 may control the speed of calculation of a codeword CDWD to be subsequently input either based on the UCN value UCN# or the number of iterations ITR# or based on the UCN value UCN# and the number of iterations ITR#.....
[0035] When it is determined that the decoding operation has passed, the syndrome checker 120 may transmit a UCN value or a number of UCNs UCN# and a number of iterations (i.e., the iteration number) ITR#, which are detected during the iterations of the decoding operation, to the iteration calculator 110.
[0050] The bit controller 33 may set the number of bits by which a calculation operation is performed in one cycle. The initial number of bits may also be set in the bit controller 33, but the number of bits by which each calculation operation is performed may be changed in response to a second speed code 2SPC.)
EXCEPT
performing a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
Bazarsky teaches
performing a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
([0013], methods for selecting thresholds for use by a bit-flipping ECC decoder based on various parameters, such as logical values, error counts, and counts of particular bits…...)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified JO to incorporate the teaching of the elements from Bazarsky as indicated above, in order to improve the operating speed of the error correction decoder. (Jo, [0002]).
As per claim 11, JO teaches A memory system comprising:
a memory device configured to output a codeword read from a plurality of memory cells; and ;
a controller configured to establish a plurality of variable nodes and a plurality of check nodes from the codeword
(FIG.1, [0027], may output a message MSG by decoding a codeword CDWD output from a memory device]; [0061], FIG.7, S71)
wherein the controller comprises:
a preliminary operation unit including a plurality of unit preliminary operation units configured to perform a preliminary operation according to a preliminary operation speed, to generate predictive error information of each of the plurality of the variable nodes;
a speed setting unit configured to set the preliminary operation speed by controlling a count of enabled unit preliminary operation units per a unit time,
a determination unit configured to determine each of the plurality of the variable nodes as a target variable node or a skip variable node based on the predictive error information; and
……
wherein the speed setting unit increases the preliminary operation speed as a progress rate of the preliminary operation or a progress rate of the main decoding operation increases.
([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed; [0036] The iteration calculator 110 may control the speed of calculation of a codeword CDWD to be subsequently input either based on the UCN value UCN# or the number of iterations ITR# or based on the UCN value UCN# and the number of iterations ITR#.....
[0035] When it is determined that the decoding operation has passed, the syndrome checker 120 may transmit a UCN value or a number of UCNs UCN# and a number of iterations (i.e., the iteration number) ITR#, which are detected during the iterations of the decoding operation, to the iteration calculator 110.
[0050] The bit controller 33 may set the number of bits by which a calculation operation is performed in one cycle. The initial number of bits may also be set in the bit controller 33, but the number of bits by which each calculation operation is performed may be changed in response to a second speed code 2SPC.)
EXCEPT
a main operation unit configured to perform a main decoding operation for error correction on the at least one target variable node,
Bazarsky teaches
a main operation unit configured to perform a main decoding operation for error correction on the at least one target variable node,
([0013], methods for selecting thresholds for use by a bit-flipping ECC decoder based on various parameters, such as logical values, error counts, and counts of particular bits…...)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified JO to incorporate the teaching of the elements from Bazarsky as indicated above, in order to improve the operating speed of the error correction decoder. (Jo, [0002]).
As per claim 2, Jo- Bazarsky teaches the method applied above in claim 1, Jo further teaches wherein the setting of the preliminary operation speed includes differently setting a count of the variable nodes, on which the preliminary operation is performed during a unit time, according to the progress rate of the preliminary operation. ([0050] The bit controller 33 may set the number of bits by which a calculation operation is performed in one cycle. The initial number of bits may also be set in the bit controller 33, but the number of bits by which each calculation operation is performed may be changed in response to a second speed code 2SPC.)
As per claim 3 Jo- Bazarsky teaches the method applied above in claim 1, Jo further teaches wherein the progress rate of the preliminary operation includes a count of iterations of the preliminary operation and an execution order of a plurality of sub-preliminary operations included in the preliminary operation.
([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed;)
As per claim 13, Jo- Bazarsky teaches The memory system applied above in claim 11, Jo further teaches wherein the progress rate of the preliminary operation includes a count of iterations of the preliminary operation and an execution order of a plurality of sub-preliminary operations included in the preliminary operation. ([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed;
As per claim 7, Jo- Bazarsky teaches the method applied above in claim 1, Jo further teaches further comprising: re-setting a preliminary operation speed of a preliminary operation scheduled to be performed, according to an error rate calculated during the performing of the main decoding operation.
([0009] adjusting, based on at least one of the counted number of iterations and the counted number of UCNs, at least one of the number of variable nodes and the clock speed for performing the LDPC decoding operation on a subsequent codeword.
[0037] Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved.)
As per claim 17, Jo- Bazarsky teaches The memory system applied above in claim 11, Jo further teaches wherein the controller re-sets a preliminary operation speed of a preliminary operation scheduled to be performed, based on main error information calculated during the main decoding operation.
([0009] adjusting, based on at least one of the counted number of iterations and the counted number of UCNs, at least one of the number of variable nodes and the clock speed for performing the LDPC decoding operation on a subsequent codeword.
[0037] Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved.)
As per claim 8, Jo- Bazarsky teaches the method applied above in claim 7, Bazarsky further teaches wherein the error rate includes at least one of a count of unsatisfied check nodes calculated during the error correction, a count of iterations of the main decoding operation performed during the error correction, and a count of uncorrectable errors. ([0012]-[0014])
As per claim 18, Jo- Bazarsky teaches The memory system applied above in claim 17, Bazarsky further teaches wherein the main error information includes at least one of a count of unsatisfied check nodes calculated during the error correction, a count of iterations of the main decoding operation performed during the error correction, and a count of uncorrectable errors.
([0012]-[0014])
As per claim 9, Jo- Bazarsky teaches the method applied above in claim 7, Jo further teaches wherein the re-setting of the preliminary operation speed includes:
comparing the error rate with a threshold value; and
re-setting the preliminary operation speed to be lower than a speed of an immediately preceding preliminary operation, or to be higher than a speed set for the preliminary operation speed of the preliminary operation scheduled to be performed according to the comparison result.
([0037] In this way, the present embodiment may control the speed of an error correction calculation on a codeword to be subsequently input based on the result of an error correction calculation on the previously input codeword. Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved. In contrast, when the number of error bits is large, the calculation speed may be adjusted to be lower, thus reducing power consumed by the error correction decoder 1200 while improving the reliability of error correction.)
As per claim 19, Jo- Bazarsky teaches The memory system applied above in claim 17, Jo further teaches wherein the controller re-sets the preliminary operation speed to be lower than a speed of an immediately preceding preliminary operation, or to be higher than a speed set for the preliminary operation speed of the preliminary operation scheduled to be performed, according to a result of comparing the main error information with a threshold value.
([0037] In this way, the present embodiment may control the speed of an error correction calculation on a codeword to be subsequently input based on the result of an error correction calculation on the previously input codeword. Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved. In contrast, when the number of error bits is large, the calculation speed may be adjusted to be lower, thus reducing power consumed by the error correction decoder 1200 while improving the reliability of error correction.)
As per claim 10, Jo- Bazarsky teaches the method applied above in claim 7, Jo further teaches wherein performing the preliminary operation comprises
determining to re-set the preliminary operation speed when the progress rate of the preliminary operation is greater than or equal to a specific value. ([0036])
As per claim 20, Jo- Bazarsky teaches The memory system applied above in claim 17, Jo further teaches wherein, when the progress rate of the preliminary operation is greater than or equal to a specific value, the controller determines to re-set the preliminary operation speed. ([0036])
Examiner’s Notes
There are no art rejection for Claims 4-6, and 14-16, claim 14-16 are under 112b rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fainzilber et al., US 9614547 Multi-stage Decoder
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RONG TANG whose telephone number is (469)295-9106. The examiner can normally be reached Monday - Friday 7:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
Prosecution Insights