Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/23/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 6, 8, 13-14, 16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 line 2, Claim 6 line 1, Claim 16 line 2 and claim 16 line 1 recite the limitation "the number of the variable nodes". There is insufficient antecedent basis for this limitation in the claim.
Claim 3 line 2, Claim 4 line 8, Claim 8 line, Claim 13 line 2, Claim 14 line 2 and Claim 18 line 3 recite the limitation "the number of iterations". There is insufficient antecedent basis for this limitation in the claim.
Any claim not specifically mentioned above, is rejected due to its dependency on the rejected claim.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 11, similarly claim 1 recites “setting a preliminary operation speed based on a progress rate……”, “performing the preliminary operation according to the preliminary operation speed……”; “performing a main decoding operation for error correction……;” As is evident on present Specification [0077] “The LDPC decoding method may include a preliminary operation 520 for estimating (or calculating) predictive error information ERR_PRE.” [0081] “the controller 130 may perform the main decoding operation using a two-bit weighted bit flipping algorithm in which each of the plurality of the variable nodes VN includes a value bit and a state bit”. These limitations thus describe a “mathematical calculations,” which is specifically identified as an exemplar in the “mathematical concepts” grouping of abstract ideas. Thus, the above cited steps recites a concept that falls into the “mathematical concept” groups of abstract ideas.
Claim 11 recite additional elements “a memory device”, “a controller”, which are described as mere instructions to use the generically recited memory device and controller to implement the abstract idea. See MPEP 2106.05(f).
Claims 11/1 recite additional elements: – “output a codeword read from a plurality of memory cells……”, / “establishing a plurality of check nodes and a plurality of variable nodes corresponding to the plurality of check nodes of a codeword ……”. These steps represent mere data gathering that is necessary for use of the recited judicial exception and is recited at a high level of generality. Thus they are insignificant extra-solution activity See MPEP 2106.05(g).
The combination of these additional elements is no more than using generic circuit components a tool to perform an abstract idea mathematical calculation. Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application under Step 2A Prong 2 because they do not impose any meaningful limits on practicing the abstract idea.
As discussed as the above, the claimed output steps are mere data gathering, that are recited at a high level of generality, and is well-known, See MPEP 2106.05(d) II and The additional elements are routinely used for the purposes claimed, see Djordjevic et al., US 20140101512, [0048]. The claim does not provide an inventive concept that would amount to significantly more at Step 2B.
Claims 2, 4-6, 12, and 14-16 further details “setting of the preliminary operation speed”, i.e. math concept.
Claims 3, 13 further details “the progress rate of the preliminary operation”, i.e. math concept.
Claims 7-10, and 17-20 further details “re-setting a preliminary operation speed of a preliminary operation”, i.e. math concept.
Accordingly, none of the additional elements in claims above would integrate the abstract idea into a practical application under Step 2A Prong 2 because they do not impose any meaningful limits on practicing the abstract idea. The additional elements are routinely used for the purposes claimed, see cited reference Ansari et al., US 20210124711, [0086], [0040]. Thus, there are no elements recited in the claim language of claims 2-10 and 12-20 that would amount to significantly more in Step 2B.
Therefore claims 1-20 are not patent eligible in their current form.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-13 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JO et al., US 20210359710, hereinafter JO, in view of Bazarsky et al., US 20180175889, hereinafter Bazarsky.
As per claim 1, JO teaches A method for decoding a memory system, the method comprising:
establishing a plurality of check nodes and a plurality of variable nodes corresponding to the plurality of check nodes of a codeword; (FIG.1, [0027] may output a message MSG by decoding a codeword CDWD output from a memory device; [0061], FIG.7, S71)
setting a preliminary operation speed based on a progress rate of a preliminary operation for generating predictive error information of each of the plurality of the variable nodes;
performing the preliminary operation according to the preliminary operation speed; and
([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed; [0036] The iteration calculator 110 may control the speed of calculation of a codeword CDWD to be subsequently input either based on the UCN value UCN# or the number of iterations ITR# or based on the UCN value UCN# and the number of iterations ITR#.....)
EXCEPT
performing a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
Bazarsky teaches
performing a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
([0013], methods for selecting thresholds for use by a bit-flipping ECC decoder based on various parameters, such as logical values, error counts, and counts of particular bits…...)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified JO to incorporate the teaching of the elements from Bazarsky as indicated above, in order to improve the operating speed of the error correction decoder. (Jo, [0002]).
As per claim 11, JO teaches A memory system comprising:
a memory device configured to output a codeword read from a plurality of memory cells; and ; (FIG.1, [0027, may output a message MSG by decoding a codeword CDWD output from a memory device]; [0061], FIG.7, S71)
a controller configured to:
set a preliminary operation speed, based on a progress rate of the preliminary operation for generating predictive error information of each of a plurality of the variable nodes,
perform the preliminary operation according to the preliminary operation speed, and
([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed; [0036] The iteration calculator 110 may control the speed of calculation of a codeword CDWD to be subsequently input either based on the UCN value UCN# or the number of iterations ITR# or based on the UCN value UCN# and the number of iterations ITR#.....)
EXCEPT
perform a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
Bazarsky teaches
perform a main decoding operation for error correction on at least a part of the plurality of the variable nodes based on the predictive error information.
([0013], methods for selecting thresholds for use by a bit-flipping ECC decoder based on various parameters, such as logical values, error counts, and counts of particular bits…...)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified JO to incorporate the teaching of the elements from Bazarsky as indicated above, in order to improve the operating speed of the error correction decoder. (Jo, [0002]).
As per claim 2, Jo- Bazarsky teaches the method applied above in claim 1, Jo further teaches wherein the setting of the preliminary operation speed includes differently setting the number of the variable nodes, on which the preliminary operation is performed during a unit time, according to the progress rate of the preliminary operation. ([0050] he bit controller 33 may set the number of bits by which a calculation operation is performed in one cycle. The initial number of bits may also be set in the bit controller 33, but the number of bits by which each calculation operation is performed may be changed in response to a second speed code 2SPC.)
As per claim 12, Jo- Bazarsky teaches The memory system applied above in claim 11, Jo further teaches wherein the controller includes a preliminary operation unit including a plurality of unit preliminary operation units for performing the preliminary operation, and
sets the preliminary operation speed by varying the number of a plurality of unit preliminary operation units driven during a unit time.
([0050] he bit controller 33 may set the number of bits by which a calculation operation is performed in one cycle. The initial number of bits may also be set in the bit controller 33, but the number of bits by which each calculation operation is performed may be changed in response to a second speed code 2SPC.)
As per claim 3 Jo- Bazarsky teaches the method applied above in claim 1, Jo further teaches wherein the progress rate of the preliminary operation includes the number of iterations of the preliminary operation and an execution order of a plurality of sub-preliminary operations included in the preliminary operation.
([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed;)
As per claim 13, Jo- Bazarsky teaches The memory system applied above in claim 11, Jo further teaches wherein the progress rate of the preliminary operation includes the number of iterations of the preliminary operation and an execution order of a plurality of sub-preliminary operations included in the preliminary operation. ([0009] counting the number of iterations and the number of UCNs after each iteration, the operation being performed with a particular number of variable nodes at a particular clock speed;
As per claim 7, Jo- Bazarsky teaches the method applied above in claim 1, Jo further teaches further comprising: re-setting a preliminary operation speed of a preliminary operation scheduled to be performed, according to an error rate calculated during the performing of the main decoding operation.
([0009] adjusting, based on at least one of the counted number of iterations and the counted number of UCNs, at least one of the number of variable nodes and the clock speed for performing the LDPC decoding operation on a subsequent codeword.
[0037] Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved.)
As per claim 17, Jo- Bazarsky teaches The memory system applied above in claim 11, Jo further teaches wherein the controller re-sets a preliminary operation speed of a preliminary operation scheduled to be performed, based on main error information calculated during the main decoding operation.
([0009] adjusting, based on at least one of the counted number of iterations and the counted number of UCNs, at least one of the number of variable nodes and the clock speed for performing the LDPC decoding operation on a subsequent codeword.
[0037] Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved.)
As per claim 8, Jo- Bazarsky teaches the method applied above in claim 7, Bazarsky further teaches wherein the error rate includes at least one of the number of unsatisfied check nodes calculated during the error correction, the number of iterations of the main decoding operation performed during the error correction, and the number of uncorrectable errors. ([0012]-[0014])
As per claim 18, Jo- Bazarsky teaches The memory system applied above in claim 17, Bazarsky further teaches wherein the main error information includes at least one of the number of unsatisfied check nodes calculated during the error correction, the number of iterations of the main decoding operation performed during the error correction, and the number of uncorrectable errors.
([0012]-[0014])
As per claim 9, Jo- Bazarsky teaches the method applied above in claim 7, Jo further teaches wherein the re-setting of the preliminary operation speed includes:
comparing the error rate with a threshold value; and
re-setting the preliminary operation speed to be lower than a speed of an immediately preceding preliminary operation, or to be higher than a speed set for the preliminary operation speed of the preliminary operation scheduled to be performed according to the comparison result.
([0037] In this way, the present embodiment may control the speed of an error correction calculation on a codeword to be subsequently input based on the result of an error correction calculation on the previously input codeword. Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved. In contrast, when the number of error bits is large, the calculation speed may be adjusted to be lower, thus reducing power consumed by the error correction decoder 1200 while improving the reliability of error correction.)
As per claim 19, Jo- Bazarsky teaches The memory system applied above in claim 17, Jo further teaches wherein the controller re-sets the preliminary operation speed to be lower than a speed of an immediately preceding preliminary operation, or to be higher than a speed set for the preliminary operation speed of the preliminary operation scheduled to be performed, according to a result of comparing the main error information with a threshold value.
([0037] In this way, the present embodiment may control the speed of an error correction calculation on a codeword to be subsequently input based on the result of an error correction calculation on the previously input codeword. Accordingly, when the number of error bits is small, the calculation speed may be adjusted to be higher, thus enabling the performance of the error correction decoder 1200 to be improved. In contrast, when the number of error bits is large, the calculation speed may be adjusted to be lower, thus reducing power consumed by the error correction decoder 1200 while improving the reliability of error correction.)
As per claim 10, Jo- Bazarsky teaches the method applied above in claim 7, Jo further teaches wherein performing the preliminary operation comprises
determining to re-set the preliminary operation speed when the progress rate of the preliminary operation is greater than or equal to a specific value. ([0036])
As per claim 20, Jo- Bazarsky teaches The memory system applied above in claim 17, Jo further teaches wherein, when the progress rate of the preliminary operation is greater than or equal to a specific value, the controller determines to re-set the preliminary operation speed. ([0036])
Examiner’s Notes
There are no art rejection for Claims 4-6, and 14-16, however they are under 112 & 101 rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fainzilber et al., US 9614547 Multi-stage Decoder
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111