Prosecution Insights
Last updated: October 04, 2026
Application No. 18/813,219

METHOD OF MANUFACTURING CIRCUIT BOARD

Non-Final OA §102§103
Filed
Aug 23, 2024
Priority
Aug 25, 2023 — RE 10-2023-0111979
Examiner
TRAN, BINH X
Art Unit
Tech Center
Assignee
Haesung Ds Co. Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
762 granted / 933 resolved
+21.7% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
42 currently pending
Career history
962
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
40.6%
+0.6% vs TC avg
§102
20.5%
-19.5% vs TC avg
§112
29.9%
-10.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 933 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claims 1-4, 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon (KR 2015/0134699 A). As to claim 1, Kwon discloses a method of manufacturing a circuit board, the method comprising: preparing a first stack in which a first foil (20) and a second foil (10) are stacked, wherein a thickness of the second foil (20) is greater than a thickness of the first foil (10) (See paragraph 0024-0025, Fig 2); forming a first circuit pattern (21) by etching the first foil (20) (paragraph 0028, Fig 3); forming a second stack by arranging an insulating layer (40) and a third foil (30), the insulating layer covering the first circuit pattern (21) and the third foil (30) attached to the insulating layer (40) (See paragraph 0030 Fig 4); reducing the thickness of the second foil (10) and a thickness of the third foil (30) through a half- etching process (paragraph 0035, Fig 4); removing the second foil (10) of which the thickness has been reduced (Fig 6, paragraph 0036); and forming a second circuit pattern (31) by etching the third foil (30) (paragraph 0038, Fig 7). As to claim 2, Kwon discloses the thickness of the first foil (20) of the first stack is about 2 µm (See paragraph 0025; within applicant’s range “from about 2 µm to about 3 µm”). As to claim 3, Kwon discloses the thickness of the second foil (10) of the first stack is about 18 µm (See paragraph 0025, within applicant’s range “from about 12 µm to about 18 µm”). As to claim 4, Kwon discloses the first stack comprises a carrier (100) attached to the second foil (10) (paragraph 0024, Fig 2). As to claim 6, Kwon discloses before the removing of the second foil (10) of which the thickness has been reduced, forming a via hole (VH) electrically connecting the first circuit pattern (21) to the third foil (30) (See paragraph 0033-0038, Fig 5-6). As to claim 7, Kwon discloses after the removing of the second foil (10) of which the thickness has been reduced, when an etching resist pattern (5 or 50) is formed in the third foil to form the second circuit pattern (31) by etching, an etching resist layer (5 or 50) is formed on a surface, from which the second foil has been removed, to protect the first circuit pattern during etching (paragraph 0020, 0038-0041). As to claim 8, Kwon discloses after the forming of the second circuit pattern, arranging a solder resist layer (i.e. photo solder resist) covering a portion of the first circuit pattern and a portion of the second circuit pattern (paragraph 0020, Fig 1). Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon (KR 2015/0134699 A) as applied to claims 1-4, 6-8 above, and further in view of Ueda (JP 2002/141630 A). As to claim 5, Kwon fails to disclose the thickness of the third foil of the second stack is from about 12 µm to about 18 µm. However, Kwon clearly discloses forming a third foil (30) having some thickness value. Ueda teaches forming a foil comprises of copper having a thickness of 3 to 35 µm, including example of 18 μm (See paragraph 0030, 0062, within applicant’s range from about 12 μm to about 18 μm). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kwon in view of Ueda by having the thickness of the third foil of the second stack is from about 12 µm to about 18 µm because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)). Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH X TRAN whose telephone number is (571)272-1469. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BINH X. TRAN Examiner Art Unit 1713 /BINH X TRAN/ Primary Examiner, Art Unit 1713
Read full office action

Prosecution Timeline

Aug 23, 2024
Application Filed
Aug 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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METHOD FOR FILLING A GAP IN A THREE-DIMENSIONAL STRUCTURE ON A SEMICONDUCTOR SUBSTRATE
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+12.0%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 933 resolved cases by this examiner. Grant probability derived from career allowance rate.

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