DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because Figure 5 fails to show IR as described in the specification, paragraph [0062], line 2 and line 6. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0059], the memory portion “180” (line 2) and the memory array “18” (lines 2 and 4) are not shown in Fig.4.
The term “the main programming bitline WL, MBL_P” in paragraph [0067], line 4 and paragraph [0068], line 7 is confusing because “WL” is used for the word line (paragraph [0037], line 2.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maejima (JP 2021072313 A).
Regarding claims 1 and 8, Maejima discloses a memory device and a method, comprising:
a memory array (Figs. 1 and 2, 10) comprising memory cells arranged in a set of memory portions (10a and 10b) and addressable via pairs of row and column values, wherein each memory portion in the set of memory portions comprises at least one sector (BLK0 … BLK8) of memory cells arranged in rows and columns;
a set of sense amplifier circuits (SAUb<0> …SAUb<m-1>) comprising sense amplifier circuits coupled to and interposed between adjacent memory portions in the set of memory portions of the memory array;
a control logic circuit (Fig. 1, 2) coupled to the memory array and configured to:
provide at least one address signal indicative of a pair of row and column values to localize at least one addressed memory cell in the memory array (Each memory cell is associated with, for example, one bit line (column) and one word line (row)); and
issue read or write access requests towards the at least one addressed memory cell in the memory array (The command register 11 holds the command CMD received by the semiconductor storage device 1 from the memory controller 2. The command CMD includes, for example, an instruction for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like);
a first set of access devices (Figs. 3 and 25, ST1 and Fig. 27, BSWa, BSWb) coupled to the control logic circuit, to the memory cells in the memory array, and to the set of sense amplifier circuits, wherein the first set of access devices are configured to be made conductive to couple a respective first addressed memory cell in a respective memory portion of the set of memory portions of the memory array to a respective sense amplifier circuit in the set of sense amplifier circuits in response to a read access request issued by the control logic circuit (The sense amplifier sets SASa and SASb are associated with the memory cell array 10a and 10b, respectively. The sense amplifier set SASa includes a sense amplifier unit SAUa <0> to SAUa <m-1>. The sense amplifier set SASb includes a sense amplifier unit SAUb <0> to SAUb <m-1>. Each sense amplifier unit SAU is connected to at least one bit line BL. For example, the sense amplifier units SAUa <0> to SAUa <m-1> are connected to the bit lines BLa0 to BLa (m-1), respectively. The sense amplifier units SAUb <0> to SAUb <m-1> are connected to bit lines BLb0 to BLb (m-1), respectively.); and
a second set of access devices (Fig. 33, BSW1, BSW2, BLS) coupled to the control logic circuit, to the memory cells in the memory array, and to a main programming bitline (GBL), wherein the second set of access devices are configured to be made conductive to couple a respective second addressed memory cell in the respective memory portion of the set of memory portions of the memory array to the main programming bitline in response to a write access request issued by the control logic circuit.
Regarding claims 2 and 9, Maejima discloses the memory device of claim 1 and the method of claim 8, wherein the first set of access devices comprises:
a first subset of access devices (Fig, 3, ST1) coupled to the memory portion in the set of memory portions of the addressed memory cell, and to a local bitline portion; and
a second subset of access devices (Fig. 27, BSWa, BSWb) coupled to the local bitline portion and to a sense amplifier circuit in the set of sense amplifier circuits;
wherein, in response to the control logic circuit issuing a read signal:
first access devices in the first subset of access devices are configured to be made conductive to couple the addressed memory cell to the local bitline portion as a result; and
second access devices in the second subset of access devices are configured to be made conductive to provide a current flow path from the local bitline portion to the sense amplifier circuit, with a read electric current flowing from the addressed memory cell to the sense amplifier circuit as a result.
Regarding claims 3 and 10, Maejima discloses the memory device of claim 2 and the method of claim 9, wherein the second set of access devices comprises:
a third subset of access devices (Fig. 33, BSW1, BSW2) coupled to the memory portion in the set of memory portions of the addressed memory cell and to the main programming bitline (GBL); and
a fourth subset of access devices (Fig. 33, BSW1, BSW2) coupled to the main programming bitline; wherein, in response to the control logic circuit issuing a write signal:
third access devices in the third subset of access devices are configured to be made conductive, coupling the addressed memory cell to the main programming bitline to receive a programming electric current as a result; and
fourth access devices in the fourth subset of access devices are configured to be made conductive to provide a second current flow path, with a feedback electric current flowing from the addressed memory cell to the main programming bitline as a result.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Maejima et al..
Regarding claim 7, Maejima does not disclose that the memory cells in the memory array are phase change memories. However, the use of phase change memory cells or NAND type memory cells are well-known in the art to provide a non-volatile memory device. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Maejima by using a phase change memory array to provide a non-volatile memory device.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Maejima in view of Zhu et al. (US 2024/0379140, hereinafter “Zhu”).
Regarding claim 14, Maejima discloses a system, comprising:
a memory device comprising:
a memory array comprising memory cells arranged in a set of memory portions and addressable via pairs of row and column values, wherein each memory portion in the set of memory portions comprises at least one sector of memory cells arranged in rows and columns;
a set of sense amplifier circuits comprising sense amplifier circuits coupled to and interposed between adjacent memory portions in the set of memory portions of the memory array;
a control logic circuit coupled to the memory array and configured to:
provide at least one address signal indicative of a pair of row and column values to localize at least one addressed memory cell in the memory array; and
issue read or write access requests towards the at least one addressed memory cell in the memory array;
a first set of access devices coupled to the control logic circuit, to the memory cells in the memory array, and to the set of sense amplifier circuits, wherein the first set of access devices are configured to be made conductive to couple a respective first addressed memory cell in a respective memory portion of the set of memory portions of the memory array to a respective sense amplifier circuit in the set of sense amplifier circuits in response to a read access request issued by the control logic circuit; and
a second set of access devices coupled to the control logic circuit, to the memory cells in the memory array, and to a main programming bitline, wherein the second set of access devices are configured to be made conductive to couple a respective second addressed memory cell in the respective memory portion of the set of memory portions of the memory array to the main programming bitline in response to a write access request issued by the control logic circuit (see the rejection of claim 1); and
Maejima does not disclose a digital-to-analog converter circuit configured to produce a programming electric current provided to the main programming bitline.
However, Zhu discloses the use of a current-mode digital-to-analog to provide a current to the bit line (paragraph [0012]. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a digital-to-analog circuit of Zhu to produce a programming electric current provided to the bit line via the global bit line of Maejima.
Regarding claim 15, the combination of Maejima and Zhu does not disclose the the digital-to-analog converter circuit configured to produce the programming electric current provided to the main programming bitline via a program driver circuit coupled therebetween. However, the use od a program or write driver to transfer data to program a memory cell to store data is well-known in the art. It would have been obvious to one having ordinary skill in the art to use a program or write driver to transfer data to a bit line via a global bit line to store data in the memory cell.
Regarding claim 16, Maejima discloses the system of claim 14, wherein the first set of access devices comprises: a first subset of access devices coupled to the memory portion in the set of memory portions of the addressed memory cell, and to a local bitline portion; and a second subset of access devices coupled to the local bitline portion and to a sense amplifier circuit in the set of sense amplifier circuits; wherein, in response to the control logic circuit issuing a read signal: first access devices in the first subset of access devices are configured to be made conductive to couple the addressed memory cell to the local bitline portion as a result; and second access devices in the second subset of access devices are configured to be made conductive to provide a current flow path from the local bitline portion to the sense amplifier circuit, with a read electric current flowing from the addressed memory cell to the sense amplifier circuit as a result (see the rejection of claim 2).
Regarding claim 17, Maejima discloses the system of claim 16, wherein the second set of access devices comprises: a third subset of access devices coupled to the memory portion in the set of memory portions of the addressed memory cell and to the main programming bitline; and a fourth subset of access devices coupled to the main programming bitline; wherein, in response to the control logic circuit issuing a write signal: third access devices in the third subset of access devices are configured to be made conductive, coupling the addressed memory cell to the main programming bitline to receive the programming electric current as a result; and fourth access devices in the fourth subset of access devices are configured to be made conductive to provide a second current flow path, with a feedback electric current flowing from the addressed memory cell to the main programming bitline as a result (see the rejection of claim 3).
Allowable Subject Matter
Claims 4-6, 11-13 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 4, 11 and 18, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the program driver circuit is configured to receive the feedback electric current from the addressed memory cell in the set of memory portions of the memory array in response to the fourth access devices in the fourth subset of access devices being made conductive.” in combination with the other limitations thereof as is recited in the claim.
Regarding claims 5, 12 and 19. the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “fourth access devices in the fourth subset of access devices are configured to be made conductive to provide a current flow path, with a feedback electric current flowing from the addressed memory cell to the main programming bitline as a result.” in combination with the other limitations thereof as is recited in the claim.
Regarding claims 6, 13 and 20, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the program driver circuit is configured to receive the feedback electric current from the addressed memory cell in the set of memory portions of the memory array in response to the fourth access devices in the fourth subset of access devices being made conductive.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827