DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/23/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 1, 7, and 15-18 are objected to because of the following informalities:
Claim 1, lines 3-4: “the epitaxial layer being of the first conductivity type” should read --- the epitaxial layer being of a first conductivity type ---
Claim 1, lines 8-9: “being of the second conductivity type opposite to the first conductivity type” should read --- being of a second conductivity type opposite to the first conductivity type ---
Claim 7, lines 1-2: “wherein the at least two inversion protection layers has” should read --- “wherein at least two inversion protection layers have …” ---
Claim 15, lines 1-2: “A power device comprising a semiconductor device in accordance with claim 1” should read --- “A power device comprising the semiconductor device in accordance with claim 1 …”---
Claim 16, lines 1-2: “A power device comprising a semiconductor device in accordance with claim 1” should read --- “A power device comprising the semiconductor device in accordance with claim 1 …”---
Claim 17, lines 1-2: “A power device comprising a semiconductor device in accordance with claim 2” should read --- “A power device comprising the semiconductor device in accordance with claim 2 …” ---
Claim 18, lines 1-2: “A power device comprising a semiconductor device in accordance with claim 3” should read --- “A power device comprising the semiconductor device in accordance with claim 3 …” ---
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9, 11-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimochi (U.S. PG Pub No US2015/0035006A1).
Regarding claim 1, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106], comprising:
a semiconductor body (20 with 23) [0106] (formed of doped silicon semiconductor [0106]) comprising a semiconductor substrate (20) fig. 2 [0106] (doped silicon semiconductor [0106]) and an epitaxial layer (23) fig. 2 [0106] formed on the semiconductor substrate (20), the epitaxial layer (23) being of a first conductivity type (n-type) [0106], and an active area (12) fig. 2 [0106] and a termination area (10 with 11) fig. 2 [0106] (area where active area 12 terminates) adjacent (nearby) the active area (12) are arranged in [0106] the epitaxial layer (see also fig. 1 perspective);
wherein the termination area (10 with 11) comprises:
a plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]), said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) being of a second conductivity type (p-type) [0106-0107] opposite to the first conductivity type (n-type), each of said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) enclosing, observed from a top view [see fig. 1, 0105] of the semiconductor device (1), the active area (12);
one or more second regions (individual trenches 39) fig. 2 [0118-0120], wherein said one or more second regions (individual trenches 39) fig. 2 [0118-0120] are comprised in (laterally) between said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]), respectively, wherein said one or more second regions (individual trenches 39) fig. 2 [0118-0120] extend further (at maximum depth) into the epitaxial layer (5) than said plurality of spaced apart first regions (26) (bottom of 40 of 39 below bottom of 26), and wherein said one or more second regions comprise an insulation material (45) fig. 2 [0126] for insulating said plurality of spaced apart first regions (26, laterally separated by 45) from one another [0126].
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Annotated fig. 2 of Yoshimochi
Regarding claim 2, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. Yoshimochi also teaches wherein (bottommost surface of) said one or more second regions (individual trenches 39) fig. 2 [0118-0120] extend further into the epitaxial layer (23) fig. 2 [0106] than (level of 1/4th a thickness of 26) said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) by at least 150% (because the level of 1/4th a thickness of 26 extends into 23 by less than 1/4th of a depth of a the bottommost surface of 39, as defined in annotated fig. 2 of Yoshimochi above – the bottommost surface of 39 extends into 23 by a factor greater than 400% of 1/4th a thickness of 26, which is greater than 150% - as indicated by the lines defined in annotated fig. 2 of Yoshimochi above).
Regarding claim 3, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. Yoshimochi also teaches wherein said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) are floating (electrically isolated from other circuitry by trenches [0134]).
Regarding claim 4, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. Yoshimochi also teaches wherein each of said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) are uniformly (p-) doped (characterized as p-type throughout [0106-0107]).
Regarding claim 5, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. Yoshimochi also teaches further comprising:
at least one inversion protection layer (44) fig. 2 [0125] ([0125] by being more heavily doped than surrounding epitaxial layer 23) provided at a bottom side of said one or more second regions (individual trenches 39) fig. 2 [0118-0120], respectively, wherein said inversion protection layer (44) is of the first conductivity type (n-type [0125]), wherein said inversion protection layer (44) has a (n) doping concentration that is higher [0125] than a doping concentration (n-) [0106] of the epitaxial layer (23) [0106].
Regarding claim 9, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. Yoshimochi also teaches wherein said insulation material (45) fig. 2 [0128] is any of: Thermal Oxide (silicon oxide) [0128].
With respect to the underlined “thermal” limitation above, [0128] of Yoshimochi does not explicitly disclose whether the oxide is produced by a ‘thermal oxidation’ process. However, in the context of product claim 9, the “thermal” detail is considered as a product-by-process details which does not impart a unique structure into the finished product. Therefore, for the purposes of Examination, Examiner has considered the limitation(s) “thermal oxide” in claim 9 as “oxide”. (See MPEP 2113, I).
Regarding claim 11, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. Yoshimochi also teaches wherein the semiconductor device (1) comprises any of: MOSFET (14) fig. 2 [0108].
Regarding claim 12, Yoshimochi teaches a method of manufacturing [see figs. 3A-3L, 0137-0138] a semiconductor device (1) fig. 2 [0105-0106] in accordance with claim 1. Yoshimochi also teaches
wherein the method [0137] comprises the steps of:
providing said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]), said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) being of the second conductivity type (p-type) [0106-0107] opposite to the first conductivity type (n-type) [0106], each of said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) enclosing, observed from a top view [see fig. 1] of the semiconductor device (1), the active area (12);
providing said one or more second regions (individual trenches 39) fig. 2 [0118-0120], wherein said second one or more regions (individual trenches 39) are comprised in between said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]), respectively, wherein said one or more second regions (individual trenches 39) extend further (at maximum depth) into the epitaxial layer (23) fig. 2 [0106] than said plurality of spaced apart first regions (26), and wherein said one or more second regions comprise an insulation material (45) fig. 2 [0126] for insulating said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) from one another.
at least one inversion protection layer (44) fig. 2 [0125] ([0125] by being more heavily doped than surrounding epitaxial layer 23) provided at a bottom side of said one or more second regions (individual trenches 39) fig. 2 [0118-0120], respectively, wherein said inversion protection layer (44) is of the first conductivity type (n-type [0125]), wherein said inversion protection layer (44) has a (n) doping concentration that is higher [0125] than a doping concentration (n-) [0106] of the epitaxial layer (23) [0106].
Regarding claim 13, Yoshimochi teaches a method of manufacturing [see figs. 3A-3L, 0137-0138] a semiconductor device (1) fig. 2 [0105-0106] in accordance with claim 9. Yoshimochi also teaches
wherein each of said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) are uniformly (p-) doped (characterized as p-type throughout [0106-0107]).
Regarding claim 14, Yoshimochi teaches a method of manufacturing [see figs. 3A-3L, 0137-0138] a semiconductor device (1) fig. 2 [0105-0106] in accordance with claim 9. Yoshimochi also teaches
further comprising the step of:
providing at least one inversion protection layer (44) fig. 2 [0125] (able to prevent inversion of the epitaxial layer [0125]) at a bottom side of said one or more second regions (individual trenches 39) fig. 2 [0118-0120], respectively, wherein said inversion protection layer (44) is of the first (n-type) [0125] conductivity type, wherein said inversion protection layer (44) has a doping concentration that is higher [0125] than a doping concentration (n-) [0106] of the epitaxial layer (23) [0106].
Regarding claims 15 and 16, Yoshimochi teaches a power device (14) fig. 1 [0101, 0160-0161] (MOSFET) (may be used for high-power device applications [0159]) comprising (portions of) the semiconductor device (1) fig. 2 [0105-0106] in accordance with claim 1.
Regarding claim 17, Yoshimochi teaches a power device (14) fig. 1 [0101, 0160-0161] (MOSFET) (may be used for high-power device applications [0159]) comprising (portions of) the semiconductor device (1) fig. 2 [0105-0106] in accordance with claim 2.
Regarding claim 18, Yoshimochi teaches a power device (14) fig. 1 [0101, 0160-0161] (MOSFET) (may be used for high-power device applications [0159]) comprising (portions of) the semiconductor device (1) fig. 2 [0105-0106] in accordance with claim 3.
Claims 1 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimochi (U.S. PG Pub No US2015/0035006A1).
Regarding claim 1, Yoshimochi teaches a semiconductor device (1) fig. 5A [0105-0106, 0168] (refer to fig. 5A – reference characters from semiconductor device 1 of fig. 2 [0106] also apply to semiconductor device 1 of fig. 5A [0168]), comprising:
a semiconductor body (20 with 23) fig. 5A [0106, 0168] (formed of doped silicon semiconductor [0106]) comprising a semiconductor substrate (20) [0106] (doped silicon semiconductor [0106]) and an epitaxial layer (23) [0106] formed on the semiconductor substrate (20), the epitaxial layer (23) being of a first conductivity type (n-type) [0106], and an active area (12) [0106] and a termination area (10 with 11) [0106] (area where active area 12 terminates) adjacent (nearby) the active area (12) are arranged in [0106] the epitaxial layer (see also fig. 1 perspective);
wherein the termination area (10 with 11) comprises:
a plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]), said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) being of a second conductivity type (p-type) [0106-0107] opposite to the first conductivity type (n-type), each of said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) enclosing, observed from a top view [see fig. 1, 0105] of the semiconductor device (1), the active area (12);
one or more second regions (individual trenches 39) fig. 5A [0118-0120, 0168], wherein said one or more second regions (individual trenches 39) [0118-0120] are comprised in (laterally) between said plurality of spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]), respectively, wherein said one or more second regions (individual trenches 39) [0118-0120] extend further (at maximum depth) into the epitaxial layer (5) than said plurality of spaced apart first regions (26) (bottom of 40 of 39 below bottom of 26), and wherein said one or more second regions comprise an insulation material (45) [0126] for insulating said plurality of spaced apart first regions (26, laterally separated by 45) from one another [0126] (refer to cross-sectional view of fig. 5A).
Regarding claim 6, Yoshimochi teaches a semiconductor device (1) fig. 5A [0168] of claim 1. Yoshimochi also teaches further comprising at least two inversion protection layers (44, 60) fig. 5A [0135, 0168] ([0125, 0168] by being more heavily doped than surrounding epitaxial layer 23), and wherein doping concentrations (total/net concentration of n-type dopants per single inversion protection layer 44, 60) of said at least two inversion protection layers (44, 60) increase away from the active area (12) fig. 2 [0106] (there is a greater total concentration/amount of n-type dopants in 44 [0125] away from active area 12 because of its noticeably greater size than 60 [0168] in active area 12, and both 44 and 60 are assumed to have an equivalent “n” level of high-impurity dopant density per unit area [0125, 0168]).
Regarding claim 7, Yoshimochi teaches a semiconductor device (1) fig. 5A [0168] of claim 1. Yoshimochi also teaches wherein at least two inversion protection layers (44, 60) fig. 5A [0135, 0168] ([0125, 0168] by being more heavily doped than surrounding epitaxial layer 23) have a doping concentration (total/net concentration of n-type dopants per single inversion protection layer 44, 60) that increases by increasing lateral distances from the active area (12) fig. 2 [0106] (there is a greater total concentration/amount of n-type dopants in 44 [0125] at a greater lateral distance away from active area 12 because of its noticeably greater size than 60 [0168] in active area 12, and both 44 and 60 are assumed to have an equivalent “n” level of high-impurity dopant density per unit area [0125, 0168]).
.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshimochi (U.S. PG Pub No US2015/0035006A1), as applied in claim 1 above, in view of Challa (U.S. PG Pub No US2006/0214222A1).
Regarding claim 8, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. However, Yoshimochi does not explicitly disclose wherein at least one first region (individual regions of 26 defined laterally between adjacent trenches 39 [0118-0120]) of said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [see fig. 2, 0118-0120]) has a top side having a higher doping concentration than a bottom side (26 assumed to have uniform p- concentration throughout [0106].
Challa teaches a semiconductor device (200) fig. 2A [0113-0115] wherein at least one first region (individual regions of 204 with 218 material [0113] defined laterally between adjacent trenches 220 [0113]) of said plurality of laterally spaced apart first regions (individual regions of 204 with 218 defined laterally between adjacent trenches 220) has a top side (218 region) having a higher (p+) [0113] doping concentration than a bottom side (204 region) [0113] (p- region).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of Yoshimochi such that the upper portion p-doped material region [0113] surrounding the trenches [0113] is formed to have a relatively higher dopant concentration than a lower portion of the p-doped material region [0113] in order to, along with other features [0110-0114], lower transistor resistance [0110, 0114] and improve device capacitance properties [0114-0115], as taught by Challa.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshimochi (U.S. PG Pub No US2015/0035006A1).
Regarding claim 10, Yoshimochi teaches a semiconductor device (1) fig. 2 [0105-0106] of claim 1. However, the embodiment of fig. 2 of Yoshimochi does not explicitly disclose wherein spacings between said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [see fig. 2, 0118-0120]) increase in a lateral direction away from the active area (12) fig. 2 [0106] (shown with uniform spacings).
The embodiment of fig. 10 of Yoshimochi (66) fig. 10 [0177] teaches wherein spacings between (right sidewalls of) said plurality of laterally spaced apart first regions (individual regions of 26 defined laterally between adjacent trenches 39 [see fig. 10, 0118-0120]) increase in a lateral direction away from the active area (12) fig. 10 [0106] (pitches P2, P2’, P2’’… [0177] laterally increase from nearer 12 to further away from 12 [0177] such that respective right sidewalls of regions 26 between trenches 39 are progressively spaced further apart).
Therefore, it would have been obvious to someone of ordinary of ordinary skill in the art before the effective filing date of the claimed invention to have modified the isolation trenches of the embodiment of fig. 2 of Yoshimochi by the embodiment of fig. 10 of Yoshimochi such that the isolation trenches have a progressively increasing spacing pattern away from the active area [0177] in order to selectively control the relative isolation of particular trenches from one another across the device [0030, 0159-0160, 0177, 0182-0188], as taught by Yoshimochi.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature semiconductor devices with active areas surrounded by termination areas, and trench structures in doped layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 10/02/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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