Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
2. Claims 1-39 have been examined in this application. This communication is the first action on the merits.
Drawings
3. The drawing filed on 8/23/24 is acceptable for examination proceedings.
Claim Objections
4. Claim 2-21, 24-31, and 33-39 are objected to because of the following informalities: For this all claim the claim should include comma (,) before the word “wherein” at Ln. 1.
For example:
Claim 2. The system of claim 1, wherein…
Claim 24. The tool of claim 23, wherein…
Claim 33. The system of claim 32, wherein…
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
5. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: processing chambers configured to process the semiconductor substrates according to a recipe, the instructions are configured to in claim 1;
the instructions are configured to in claim 2, 5-17, 21-22, 32-39;
the tool is configured to access in claim 13;
a first robot configured to input, processing chambers configured to process, a second robot configured to transfer, a controller configured to predict in claim 23;
the controller is configured to in claim 25-27;
a first plurality of neural networks configured to, a second plurality of neural networks configured to in claim 28;
trained model is configured to in claim 30;
a first robot configured to, a second robot configured to in claim 31;
the instructions are configured to, a first plurality of neural networks configured to, a second plurality of neural networks configured to, the first and second robots are respectively configured to in claim 37.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
6. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
7. Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12072689. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed “A system for processing semiconductor substrates” of instant application is anticipated by “A system for processing semiconductor substrates” of US Patent. 12072689.
Claim 1 of this instant application
Claim 1 of the Patent:12072689
A system for processing semiconductor substrates in a tool comprising a plurality of processing chambers configured to process the semiconductor substrates according to a recipe, the system comprising: a processor; and non-transitory memory storing instructions for execution by the processor,
A system for processing semiconductor substrates in a tool comprising a plurality of processing chambers configured to process the semiconductor substrates according to a recipe, the system comprising: a processor; and non-transitory memory storing instructions for execution by the processor,
wherein the instructions are configured to: receive first data from the tool regarding processing of the semiconductor substrates in the plurality of processing chambers according to the recipe;
wherein the instructions are configured to: receive first data from the tool regarding processing of the semiconductor substrates in the plurality of processing chambers according to the recipe;
receive second data regarding a configuration of the tool and the recipe;
receive second data regarding a configuration of the tool and the recipe;
simulate, using the second data, a plurality of processing scenarios and scheduling parameters for the plurality of processing scenarios for processing the semiconductor substrates in the plurality of processing chambers according to the recipe;
simulate, using the second data, a plurality of processing scenarios and scheduling parameters for the plurality of processing scenarios for processing the semiconductor substrates in the plurality of processing chambers according to the recipe;
simulate the processing of the semiconductor substrates in the plurality of processing chambers according to the recipe using the plurality of processing scenarios and the scheduling parameters for the plurality of processing scenarios;
simulate the processing of the semiconductor substrates in the plurality of processing chambers according to the recipe using the plurality of processing scenarios and the scheduling parameters for the plurality of processing scenarios;
and train a model using the first data and data generated by the simulation to predict optimum scheduling parameters for processing the semiconductor substrates in the plurality of processing chambers according to the recipe.
train a model using the first data and data generated by the simulation to predict optimum scheduling parameters for processing the semiconductor substrates in the plurality of processing chambers according to the recipe; receive inputs from the tool regarding processing of one of the semiconductor substrates in the plurality of processing chambers according to the recipe; predict based on the inputs, using the model, optimum scheduling parameters for processing the one of the semiconductor substrates in the plurality of processing chambers according to the recipe; and schedule operations of the tool based on the optimum scheduling parameters for processing the one of the semiconductor substrates in the plurality of processing chambers according to the recipe.
8. Claim 2 is also rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12072689. Although the claims at issue are not identical, they are not patentably distinct from each other.
9. Claim 3-22 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2-21 of U.S. Patent No. 12072689, respectively. Although the claims at issue are not identical, they are not patentably distinct from each other.
10. Claim 23 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 41 of U.S. Patent No. 12072689. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed “A tool for processing semiconductor substrates” of instant application is anticipated by “A tool for processing semiconductor substrates” of US Patent. 12072689.
Claim 23 of this instant application
Claim 41 of the Patent:12072689
A tool for processing semiconductor substrates comprising: a first robot configured to input the semiconductor substrates into the tool for processing the semiconductor substrates in the tool;
A tool for processing semiconductor substrates comprising: a first robot configured to input the semiconductor substrates into the tool for processing the semiconductor substrates in the tool;
a plurality of processing chambers configured to process the semiconductor substrates in the tool according to a recipe;
a plurality of processing chambers configured to process the semiconductor substrates in the tool according to a recipe;
a second robot configured to transfer the semiconductor substrates between the plurality of processing chambers according to the recipe;
a second robot configured to transfer the semiconductor substrates between the plurality of processing chambers according to the recipe;
and a controller configured to predict, using a model trained by simulating the tool and the recipe, one or more of: processing times for processing the semiconductor substrates in the plurality of processing chambers; transfer times for the second robot for transferring the semiconductor substrates between the plurality of processing chambers; a route to transfer the semiconductor substrates between the plurality of processing chambers based on the processing times and the transfer times; and a time when the first robot is to schedule additional semiconductor substrates for processing in the tool based on the processing times and the transfer times.
and a controller configured to predict, using a model trained by simulating the tool and the recipe: processing times for processing the semiconductor substrates in the plurality of processing chambers; transfer times for the second robot for transferring the semiconductor substrates between the plurality of processing chambers; a route to transfer the semiconductor substrates between the plurality of processing chambers based on the processing times and the transfer times; and a time when the first robot is to schedule additional semiconductor substrates for processing in the tool based on the processing times and the transfer times,
wherein processing the semiconductor substrates according to the predicted route and processing the additional semiconductor substrates according to the predicted time optimizes wait times for the semiconductor substrates along the predicted route and optimizes throughput of the tool.
11. Claim 24 is also rejected on the ground of nonstatutory double patenting as being unpatentable over claim 41 of U.S. Patent No. 12072689. Although the claims at issue are not identical, they are not patentably distinct from each other.
12. Claim 25-31 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claim 42-48 of U.S. Patent No. 12072689, respectively. Although the claims at issue are not identical, they are not patentably distinct from each other.
13. Claim 32 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 49 of U.S. Patent No. 12072689. Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed “A system for optimizing throughput and wait times during processing semiconductor substrates in a semiconductor processing tool” of instant application is anticipated by “A system for optimizing throughput and wait times during processing semiconductor substrates in a semiconductor processing tool” of US Patent. 12072689.
Claim 32 of this instant application
Claim 49 of the Patent:12072689
A system for optimizing throughput and wait times during processing semiconductor substrates in a semiconductor processing tool, the system comprising: a processor; and non-transitory memory storing instructions for execution by the processor,
A system for optimizing throughput and wait times during processing semiconductor substrates in a semiconductor processing tool, the system comprising: a processor; and non-transitory memory storing instructions for execution by the processor,
wherein the instructions are configured to: simulate, based on a configuration of the semiconductor processing tool and a recipe to be performed on the semiconductor substrates in the semiconductor processing tool, a plurality of routes for routing the semiconductor substrates between a plurality of processing chambers of the semiconductor processing tool;
wherein the instructions are configured to: simulate, based on a configuration of the semiconductor processing tool and a recipe to be performed on the semiconductor substrates in the semiconductor processing tool, a plurality of routes for routing the semiconductor substrates between a plurality of processing chambers of the semiconductor processing tool;
simulate processing of the semiconductor substrates in the semiconductor processing tool according to the recipe along the plurality of routes;
simulate processing of the semiconductor substrates in the semiconductor processing tool according to the recipe along the plurality of routes;
simulate, based on the processing of the semiconductor substrates, a plurality of timing schedules for subsequently processing additional semiconductor substrates in the semiconductor processing tool;
simulate, based on the processing of the semiconductor substrates, a plurality of timing schedules for subsequently processing additional semiconductor substrates in the semiconductor processing tool;
simulate processing of the additional semiconductor substrates according to the plurality of timing schedules; and train a model based on data generated by the simulations.
simulate processing of the additional semiconductor substrates according to the plurality of timing schedules; train a model based on data generated by the simulations;
predict, using the model on the semiconductor processing tool, an optimum route to transfer the semiconductor substrates between the plurality of processing chambers when processing the semiconductor substrates in the semiconductor processing tool according to the recipe; predict, using the model on the semiconductor processing tool, an optimum time to schedule the additional semiconductor substrates for processing in the semiconductor processing tool; process, in the semiconductor processing tool, the semiconductor substrates according to the optimum route to optimize wait times for the semiconductor substrates along the optimum route; and process, in the semiconductor processing tool, the additional semiconductor substrates at the optimum time to optimize throughput of the semiconductor processing tool.
14. Claim 33 is also rejected on the ground of nonstatutory double patenting as being unpatentable over claim 49 of U.S. Patent No. 12072689. Although the claims at issue are not identical, they are not patentably distinct from each other.
15. Claim 34-39 are also rejected on the ground of nonstatutory double patenting as being unpatentable over claim 50-55 of U.S. Patent No. 12072689, respectively. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
16. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
17. Claim 23, 27, and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (Pub: 2003/0162392) in view of Watson (Pub: 2011/0147348).
18. Regarding claim 23, Wang teaches a tool for processing semiconductor substrates comprising: a first robot configured to input the semiconductor substrates into the tool for processing the semiconductor substrates in the tool (e.g., As shown in FIG. 1, the mainframe transfer robot 242 includes two robot arms 2402, corresponding to the number of processing cells 240 per processing station 218. Each robot arm 2402 includes an end effector 2404 for holding a wafer during a wafer transfer) 9Para. [0023], Fig. 1);
a plurality of processing chambers configured to process the semiconductor substrates in the tool according to a recipe (e.g., The electroplating system platform 200 preferably includes two RTA chambers 211 disposed on opposing sides of the loading station 210, corresponding to the symmetric design of the loading station 210. However, the RTA chambers 211 could be connected to the mainframe 214, or otherwise positioned in the system or provided as a stand alone anneal system) (Para. [0025]);
a second robot configured to transfer the semiconductor substrates between the plurality of processing chambers according to the recipe (e.g., The loading station 210 preferably includes one or more substrate cassette receiving areas 224, one or more loading station transfer robots 228 and at least one substrate orientor 230. The number of substrate cassette receiving areas, loading station transfer robots 228 and substrate orientor included in the loading station 210 can be configured according to the desired throughput of the system. As shown in FIG. 1, the loading station 210 includes two substrate cassette receiving areas 224, two loading station transfer robots 228 and one substrate orientor 230.) (Para. [0024]).
Wang does not specifically teach and a controller configured to predict, using a model trained by simulating the tool and the recipe, one or more of: processing times for processing the semiconductor substrates in the plurality of processing chambers; transfer times for the second robot for transferring the semiconductor substrates between the plurality of processing chambers; a route to transfer the semiconductor substrates between the plurality of processing chambers based on the processing times and the transfer times; and a time when the first robot is to schedule additional semiconductor substrates for processing in the tool based on the processing times and the transfer times.
Watson teaches and a controller configured to predict, using a model trained by simulating the tool and the recipe, one or more of: processing times for processing the semiconductor substrates in the plurality of processing chambers (e.g., Once both default recipe 400 and the work to be performed is input, a wafer throughput simulation can be performed in step 26 by simulation part 12a. Wafer throughput simulation is a software modeling technique known in the art to evaluate processing time based on particular settings of various system constraints for a given link processing system. By changing the parameters of interest here, the effects on processing time of the changes could be assessed using such a simulation. The simulation performed in step 26 would provide a processing time for default recipe 400 given the specified work to be performed for a wafer 240. The parameters of the simulation and the resulting processing time can be displayed on display 20, but this is not required. After step 26, adjustment of parameters by parameter adjusting part 12b begins in step 28 with the adjustment of a first parameter and continues to step 30 for a new simulation using the altered parameter with the other values of default recipe 400 unchanged. This new simulation in step 30 results in a new processing time associated with the altered parameter. This process repeats until the desired adjustments to the first parameters are all simulated to obtain respective processing times in response to the query of step 32. Then, optionally, a query next occurs in step 34 to assess whether additional parameters should be analyzed) (Para. [0053]-[0054]); transfer times for the second robot for transferring the semiconductor substrates between the plurality of processing chambers; a route to transfer the semiconductor substrates between the plurality of processing chambers based on the processing times and the transfer times; and a time when the first robot is to schedule additional semiconductor substrates for processing in the tool based on the processing times and the transfer times (Limitation includes “one or more”, hence citation to the above limitation is not required due to nature of the claim).
Because Watson is also directed to processing a plurality of semiconductor parts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Wand and Watson before him/her, to modify the teachings of Wang to include the processing time prediction teaching of Watson in order to select the parameter values that result in the lowest overall processing time (Para. [0056]).
19. Regarding claim 27, the combination of Wang and Watson teaches the tool of claim 23 wherein Watson further teaches the controller is configured to adjust the model in response to any changes to the recipe, the tool, or both (e.g., The parameters of the simulation and the resulting processing time can be displayed on display 20, but this is not required. After step 26, adjustment of parameters by parameter adjusting part 12b begins in step 28 with the adjustment of a first parameter and continues to step 30 for a new simulation using the altered parameter with the other values of default recipe 400 unchanged. This new simulation in step 30 results in a new processing time associated with the altered parameter. This process repeats until the desired adjustments to the first parameters are all simulated to obtain respective processing times in response to the query of step 32. Then, optionally, a query next occurs in step 34 to assess whether additional parameters should be analyzed) (Para. [0054]).
20. Regarding claim 29, the combination of Wang and Watson teaches the tool of claim 23 wherein Watson further teaches wherein the model is further trained by simulating configurations of a plurality of tools and a plurality of recipes (e.g., The simulation performed in step 26 would provide a processing time for default recipe 400 given the specified work to be performed for a wafer 240. The parameters of the simulation and the resulting processing time can be displayed on display 20, but this is not required. After step 26, adjustment of parameters by parameter adjusting part 12b begins in step 28 with the adjustment of a first parameter and continues to step 30 for a new simulation using the altered parameter with the other values of default recipe 400 unchanged. This new simulation in step 30 results in a new processing time associated with the altered parameter. This process repeats until the desired adjustments to the first parameters are all simulated to obtain respective processing times in response to the query of step 32. Then, optionally, a query next occurs in step 34 to assess whether additional parameters should be analyzed.
If there is another parameter to assess, that parameter is adjusted in step 36, and the simulation is performed with the altered parameter in step 38 to obtain a new processing time. This process repeats until the desired adjustments to this next parameter are all simulated to obtain respective processing times in response to the query of step 40. Then, optionally, the query in step 34 is repeated to assess whether additional parameters should be analyzed. The effects on processing each of the parameters can be analyzed according to this process by group of wafers, or on a wafer by wafer basis. The parameters can also be modified to simulate the performance of a subset of a wafer as described in an embodiment hereinafter.
When all of the parameters are simulated, as indicated by a negative response to the query in step 34, an altered recipe can be output by recipe determination part 12c in step 42. For example, recipe determination part 12c could select the parameter values that result in the lowest overall processing time. The altered recipe could then be supplied to output connection 18) (Refer to Para. [0054]-[0056]).
21. Regarding claim 30, the combination of Wang and Watson teaches the tool of claim 23 wherein Watson further teaches wherein the further trained model is configured to output a recommendation for a tool configuration in response to receiving recipe information as input (e.g., The simulation performed in step 26 would provide a processing time for default recipe 400 given the specified work to be performed for a wafer 240. The parameters of the simulation and the resulting processing time can be displayed on display 20, but this is not required. After step 26, adjustment of parameters by parameter adjusting part 12b begins in step 28 with the adjustment of a first parameter and continues to step 30 for a new simulation using the altered parameter with the other values of default recipe 400 unchanged. This new simulation in step 30 results in a new processing time associated with the altered parameter. This process repeats until the desired adjustments to the first parameters are all simulated to obtain respective processing times in response to the query of step 32. Then, optionally, a query next occurs in step 34 to assess whether additional parameters should be analyzed.
If there is another parameter to assess, that parameter is adjusted in step 36, and the simulation is performed with the altered parameter in step 38 to obtain a new processing time. This process repeats until the desired adjustments to this next parameter are all simulated to obtain respective processing times in response to the query of step 40. Then, optionally, the query in step 34 is repeated to assess whether additional parameters should be analyzed. The effects on processing each of the parameters can be analyzed according to this process by group of wafers, or on a wafer by wafer basis. The parameters can also be modified to simulate the performance of a subset of a wafer as described in an embodiment hereinafter.
When all of the parameters are simulated, as indicated by a negative response to the query in step 34, an altered recipe can be output by recipe determination part 12c in step 42. For example, recipe determination part 12c could select the parameter values that result in the lowest overall processing time. The altered recipe could then be supplied to output connection 18) (Refer to Para. [0054]-[0056]).
Allowable Subject Matter
In regard to independent claim 1, and 32, the claimed subject matter are allowable over the prior art once the claim objection and non-statutory double patent rejection is overcome.
Claim 24, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and when claim objection and non-statutory double patent rejection is overcome
Claim 25-26, and 31 are also objected due to their direct/indirect dependency over the claim 24.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Smayling (Pub: 2009/0023230) disclose a methods and apparatus for depositing an anti-reflection coating on a substrate to aid in fabrication of devices on the substrate. For example, use of the present invention may reduce and/or minimize reflectance of a film stack, improving photolithography resolution and reducing standing wave formation. The present invention uses information determined from a metrology or other tool to develop or select a processing recipe for a substrate. The substrate is then transported to a processing chamber that has been adapted to execute the recipe developed for the substrate. In this manner, data derived from performing metrology on the substrate is fed forward to the processing system from the metrology tool so that, for example, an anti-reflective coating specific to the substrate may be applied to the substrate according to a recipe selected or determined based on measured characteristics of the specific substrate (Para. [0010]).
Hosokawa (Pub: 2006/0184275) disclose a scalar type robot, and to a simulation device which simulates a path of the moving robot itself and a moving sheet like object, when the robot transfers the sheet like object, and relates to the device which generates programs teaching a transferring operation to the robot (Para. [0004]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIGNESHKUMAR C PATEL whose telephone number is (571)270-0698. The examiner can normally be reached Monday - Friday, 7:00 AM - 5:00 PM.
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/JIGNESHKUMAR C PATEL/Primary Examiner, Art Unit 2116
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