DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 23, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
[0010] In accordance with an aspect of the disclosure, a programming method for programming a memory device including a plurality of cell strings, each of which includes a plurality of memory cells coupled in series between a string select transistor and a ground select transistor, includes: generating a precharge voltage, a program voltage, a pass voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage, and wherein a voltage level of the pass voltage is set to a voltage level configured to active the plurality of memory cells regardless of program states of the plurality of memory cells; performing a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state, wherein the program operation is performed using a plurality of program loops, based on a voltage increment of the program voltage, and wherein each program loop of the plurality of program loops includes a precharge duration and a program execution duration; providing the precharge voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistor included in a plurality of unselected cell strings from among the plurality of cell strings, during the precharge duration; and providing the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors, during the program execution duration.
[0045] Next, two pages of data, for example second page data and third page data, [[is]] are simultaneously stored in the memory cells of the selected word line (i.e each memory cell stores a bit of each of two pages). As shown in FIG. 3B, memory cells belonging to the threshold voltage distribution corresponding to the erase state E are programmed to have threshold voltages belonging to threshold voltage distributions respectively corresponding to program states P1’ to P3’, according to data to be programmed. The memory cells belonging to the threshold voltage distribution corresponding to the program state Q1 of FIG. 3A are programmed to have threshold voltages belonging to threshold voltage distributions respectively corresponding to program states P4’ to P7’, according to data to be programmed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 and 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14: Stating “providing an activation voltage to the plurality of unselected string select transistors” is contradicting since an activation voltage would activate the transistor and thus, by definition, also select the string. It may be the case that Applicant intended to claim either “providing a deactivation voltage to the plurality of unselected string select transistors” or “providing an activation voltage to the string select transistor of the selected cell string”.
Regarding claim 19: Stating “providing an activation voltage to the plurality of unselected string select transistors” is contradicting since an activation voltage would activate the transistor and thus, by definition, also select the string. It may be the case that Applicant intended to claim either “providing a deactivation voltage to the plurality of unselected string select transistors” or “providing an activation voltage to the string select transistor of the selected cell string”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7, 8, 11, 12, 14, 15, 17, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. (US 2024/0161834) in view of Nam et al. (US 9,508,441).
Regarding claim 1: Heo teaches a memory device comprising:
a memory cell array (110 in FIG. 1, which has a block BLK1 in FIG. 2) comprising a plurality of cell strings (ST in FIG. 2 or ST1-ST4 in FIG. 3), wherein each cell string comprises a plurality of memory cells (MC in FIG. 3) which are coupled in series between a string select transistor (DST) and a ground select transistor (SST);
a voltage generator (120 in FIG. 1; [0039-0044]) configured to generate a precharge voltage (1Vpre and/or 2Vpre and/or Von and/or Vpass of FIG. 17; each is a level of precharge voltage), a program voltage (Vpgm), and a negative voltage (Vneg), wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage (each is illustrated in FIG. 17 as being higher than 0V), and a voltage level of the negative voltage is lower than the voltage level of the ground voltage (as illustrated in FIG. 17); and
a control logic circuit (180 of FIG. 1; [0049-0050]) configured to control a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state, wherein the program operation is performed using a plurality of program loops (each loop includes S41 and S42 of FIG. 4), based on a voltage increment of the program voltage (see S44; [0065]), and wherein each program loop from among the plurality of program loops comprises a precharge duration and a program execution duration (S41 and S42 of FIG. 4; PRECHARGE and PROGRAM VOLTAGE APPLY durations in FIG. 17),
wherein the control logic circuit is further configured to provide the negative voltage to a plurality of unselected string select transistors (see Vneg is applied to Unsel_DSL in FIG. 17 during PRECHARGE duration) and a plurality of unselected ground select transistors (see Vneg is applied to Unsel_SSL in FIG. 5 during PRECHARGE duration) included in a plurality of unselected cell strings from among the plurality of cell strings.
Heo does not specifically teach providing the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors during the program execution duration.
Nam (lines 51-62 of column 7) states “According to the present exemplary embodiment, the row decoder 140 may apply a negative level voltage to a non-selected string selection line and/or non-selected ground selection line in at least a portion of the program section”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Nam into the device and/or method of Heo in a manner such that the control logic circuit would be configured to provide the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors during at least a portion the program execution duration. The motivation to do so would have been to continue to reduce leakage current via the string selection transistor and/or the ground selection transistor during at least a portion of the program execution duration as exemplified by Nam.
Regarding claim 2: Heo as modified above teaches the memory device of claim 1, wherein the control logic circuit is further configured to provide the precharge voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors (Von is applied to Unsel_DSL and Unsel_SSL in FIG. 17 of Heo).
Regarding claim 3: Heo teaches the memory device of claim 2, wherein the control logic circuit is further configured to provide the precharge voltage to a common source line coupled to a plurality of ground select transistors included in the plurality of cell strings, during the precharge duration and the program execution duration (see 1Vpre and 2Vpre in FIG. 17 of Helo).
Regarding claim 7: Heo as modified above taches the memory device of claim 1, wherein the control logic circuit is further configured to provide the ground voltage to a selected word line coupled to the selected memory cell and to a plurality of unselected word lines coupled to a plurality of unselected memory cells, during the precharge duration (see 0V applied to Sel_WL during PRECHARGE in FIG. 17 of Heo).
Regarding claim 8: Heo as modified above teaches the memory device of claim 7, wherein the control logic circuit is further configured to provide the program voltage to the selected word line and to provide a pass voltage to the plurality of unselected word lines, during the program execution duration, and wherein a voltage level of the pass voltage is configured to activate the plurality of memory cells regardless of program states of the plurality of memory cells, and wherein the pass voltage is generated by the voltage generator (FIG. 17 of Heo and see “to turn on memory cells” as stated in [0041])).
Regarding claim 11: Heo (FIG. 4 and FIG. 17) teaches a programming method for programming a memory device including a plurality of cell strings (ST in FIG. 2, ST1-ST4 in FIG. 3), each of which includes a plurality of memory cells (MC) are [being] coupled in series between a string select transistor (DST) and a ground select transistor (SST), the method comprising:
generating a precharge voltage (1Vpre or Von or Vpass of FIG. 17; [0049-0050]), a program voltage (Vpgm), a pass voltage (Vpass) and a negative voltage (Vneg), wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage (each is illustrated in FIG. 17 as being higher than 0V), and a voltage level of the negative voltage is lower than the voltage level of the ground voltage (as illustrated in FIG. 17), and wherein a voltage level of the pass voltage is set to a voltage level configured to active [activate] the plurality of memory cells regardless of program states of the plurality of memory cells (see “to turn on memory cells” as stated in [0041]);
performing a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state (FIG. 4 and FIG. 17), wherein the program operation is performed using a plurality of program loops (each loop includes S41 and S42 of FIG. 4), based on a voltage increment of the program voltage (see S44; [0065]), and wherein each program loop from among the plurality of program loops comprises a precharge duration and a program execution duration (S41 and S42 of FIG. 4; PRECHARGE and PROGRAM VOLTAGE APPLY durations in FIG. 17);
providing the precharge voltage to a plurality of unselected string select transistors (Von is applied to unsel_DSL in FIG. 17) and a plurality of unselected ground select transistor [transistors] (Von is applied to unsel_SSL in FIG. 17) included in a plurality of unselected cell strings from among the plurality of cell strings, during the precharge duration (PRECHARGE duration); and
providing the negative voltage to the plurality of unselected string select transistors (see Vneg is applied to Unsel_DSL in FIG. 17 during PRECHARGE duration) and the plurality of unselected ground select transistors (see Vneg is applied to Unsel_SSL in FIG. 17 during PRECHARGE duration).
Heo does not specifically teach providing the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors during the program execution duration.
Nam (lines 51-62 of column 7) states “According to the present exemplary embodiment, the row decoder 140 may apply a negative level voltage to a non-selected string selection line and/or non-selected ground selection line in at least a portion of the program section”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Nam into the device and/or method of Heo in a manner such that the control logic circuit would be configured to provide the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors during at least a portion the program execution duration. The motivation to do so would have been to continue to reduce leakage current via the string selection transistor and/or the ground selection transistor during at least a portion of the program execution duration as exemplified by Nam.
Regarding claim 12: Heo teaches the method of claim 11, further comprising: providing the precharge voltage to a common source line coupled to a plurality of ground select transistors included in the plurality of cell strings during the precharge duration and the program execution duration (see 1Vpre and 2Vpre in FIG. 17 of Helo).
Regarding claim 14: In so far as definite Heo teaches the method of claim 11, further comprising:
providing a bit line voltage (Vinh) to a plurality of unselected bit lines coupled to the plurality of unselected cell strings, during the precharge duration and the program execution duration; and
providing an activation voltage to the plurality of unselected string select transistors, during the precharge duration and the program execution duration (Von is applied to Sel_DSL lines and Vneg/0V is applied to Unsel_DSL lines).
Regarding claim 15: Heo as modified above teaches the method of claim 11, further comprising:
providing the ground voltage to a selected word line (Sel_WL in FIG. 17 of Heo) coupled to the selected memory cell and to a plurality of unselected word lines (Unsel_WL in FIG. 17 of Heo) coupled to a plurality of memory cells, during the precharge duration;
providing the program voltage (Vpgm in FIG. 17 of Heo) to the selected word line, during the program execution duration; and
providing the pass voltage (Vpass in FIG. 17 of Heo) to the plurality of unselected word lines, during the program execution duration.
Regarding claim 17: Heo teaches a programming method of a memory device including a plurality of cell strings (ST in FIG. 2 or ST1-ST4 in FIG. 3), each of which includes a plurality of memory cells (MC in FIG. 3) are [being] coupled in series between a string select transistor (DST) and a ground select transistor (SST), the method comprising:
generating a precharge voltage (1Vpre or Von or Vpass of FIG. 17; [0049-0050]), a program voltage (Vpgm), and a negative voltage (Vneg), wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage (as illustrated in FIG. 17), and a voltage level of the negative voltage is lower than the voltage level of the ground voltage (as illustrated in FIG. 17);
performing a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state (FIG. 4 and FIG. 17), wherein the program operation is performed using a plurality of program loops (each loop includes S41 and S42 of FIG. 4), based on a voltage increment of the program voltage (see S44; [0065]), and wherein each program loop from among the plurality of program loops comprises a precharge duration (VERIFY duration in FIG. 17) and a program execution duration (PROGRAM VOLTAGE APPLY duration in FIG. 17);
providing the ground voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistors included in unselected cell strings from among the plurality of cell strings, during the precharge duration (0V is applied to Unsel_DSL and Unsel_WWL during VERIFY); and
providing the negative voltage to the plurality of unselected string select transistors (see Vneg is applied to Unsel_DSL in FIG. 17 during PRECHARGE duration) and the plurality of unselected ground select transistors (see Vneg is applied to Unsel_SSL in FIG. 17 during PRECHARGE duration).
Heo does not specifically teach providing the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors during the program execution duration.
Nam (lines 51-62 of column 7) states “According to the present exemplary embodiment, the row decoder 140 may apply a negative level voltage to a non-selected string selection line and/or non-selected ground selection line in at least a portion of the program section”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Nam into the device and/or method of Heo in a manner such that the control logic circuit would be configured to provide the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors during at least a portion the program execution duration. The motivation to do so would have been to continue to reduce leakage current via the string selection transistor and/or the ground selection transistor during at least a portion of the program execution duration as exemplified by Nam.
Regarding claim 19: In so far as definite Heo as modified above teaches the method of claim 17, further comprising:
providing the ground voltage to a bit line coupled to the selected cell string during the precharge duration and the program execution duration (see 0V applied to Sel_BL during VERIFY and PROGRAM VOLTAGE APPLY durations in FIG. 17 of Heo);
providing a bit line voltage to a plurality of unselected bit lines coupled to the plurality of unselected cell strings, during the precharge duration and the program execution duration (Vinh and/or 2Vpre in FIG. 17 of Heo); and
providing an activation voltage to the plurality of unselected string select transistors, during the precharge duration and the program execution duration (0V is applied to Unsel_DSL and Von is applied to Sel_DSL in FIG. 17 of Heo in VERIFY and PROGRAM VOLTAGE APPLY).
Regarding claim 20: Heo as modified above teaches the method of claim 17, further comprising:
providing the ground voltage to a selected word line coupled to the selected memory cell and a plurality of unselected word lines coupled to a plurality of unselected memory cells, during the precharge duration (see VERIFY duration in FIG. 17 of Heo, wherein 0V is applied to selected and unselected WL);
providing the program voltage to the selected word line, during the program execution duration (see Vpgm applied to Sel_WL in FIG. 17 of Heo); and
providing a pass voltage to the plurality of unselected word lines, during the program execution duration (see Vpass applied to Unsel_WL in FIG. 17 of Heo).
Claim(s) 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. (US 2024/0161834) as modified by Nam et al. (US 9,508,441), and further in view of Kim et al. (2023/0112849).
Regarding claim 9: Heo as modified above does not specifically teach the memory device of claim 1, wherein the control logic circuit is further configured to program first data, second data, and third data according to a two-step programming process, during the program operation, wherein the two-step programming process comprises a first step program in which memory cells having threshold voltages included in a first threshold voltage distribution corresponding to an erase state are programmed to have threshold voltages included in a second threshold voltage distribution corresponding to a first program state, according to the first data, and wherein the two-step programming process further comprises a second step program in which the memory cells having threshold voltages included in the first threshold voltage distribution are programmed to have threshold voltages included in one from among a third threshold voltage distribution corresponding to a second program state, a fourth threshold voltage distribution corresponding to a third program state, and a fifth threshold voltage distribution corresponding to a fourth program state according to the second data and the third data, and memory cells including threshold voltages included the second threshold voltage distribution are programmed to have threshold voltages included in one from among a sixth threshold voltage distribution corresponding to a fifth program state, a seventh threshold voltage distribution corresponding to a sixth program state, an eighth threshold voltage distribution corresponding to a seventh program state, and a ninth threshold voltage distribution corresponding to an eighth program state according to the second data and the third data.
Kim ([0071-0075]; FIG. 5A-C) teaches such a two-step programming process, which is identical to Applicants two-step programming process illustrated in Applicants’ FIGs. 3A-C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kim into the device and/or method of Heo as modified above in a manner such that the control logic circuit would be configured to program by programming first data, second data, and third data according to a two-step programming process, during the program operation, wherein the two-step programming process would compris a first step program in which memory cells having threshold voltages included in a first threshold voltage distribution corresponding to an erase state are programmed to have threshold voltages included in a second threshold voltage distribution corresponding to a first program state, according to the first data, and wherein the two-step programming process would further comprise a second step program in which the memory cells having threshold voltages included in the first threshold voltage distribution are programmed to have threshold voltages included in one from among a third threshold voltage distribution corresponding to a second program state, a fourth threshold voltage distribution corresponding to a third program state, and a fifth threshold voltage distribution corresponding to a fourth program state according to the second data and the third data, and memory cells including threshold voltages included the second threshold voltage distribution are programmed to have threshold voltages included in one from among a sixth threshold voltage distribution corresponding to a fifth program state, a seventh threshold voltage distribution corresponding to a sixth program state, an eighth threshold voltage distribution corresponding to a seventh program state, and a ninth threshold voltage distribution corresponding to an eighth program state according to the second data and the third data. The motivation to do so would have been to use a 2-step programming method already known at the time to be suitable for programming multi-bit memory cells as exemplified by Kim.
Regarding claim 16: Heo as modified above does not specifically teach the method of claim 11, wherein the performing the program operation comprises programming first data to third data according to a two-step programming process, and wherein the method further comprises: programming, by a first step program, memory cells belonging to a threshold voltage distribution corresponding to an erase state to have threshold voltages belonging to threshold voltage distributions corresponding to a first program state according to the first data to be programmed; programming, by a second step program, the memory cells belonging to the threshold voltage distribution corresponding to the erase state to have threshold voltages belonging to threshold voltage distributions corresponding respectively to a second program state to a fourth program state according to the second data and third data to be programmed; and programming, by the second step program, memory cells belonging to the threshold voltage distribution corresponding to the first program state to have threshold voltages belonging to threshold voltage distributions corresponding respectively to a fifth program state to an eighth program state according to the second data and third data to be programmed.
Kim ([0071-0075]; FIG. 5A-C) teaches such a two-step programming process, which is identical to Applicants two-step programming process illustrated in Applicants’ FIGs. 3A-C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kim into the device and/or method of Heo as modified above in a manner such that the control logic circuit would be configured to program by programming first data, second data, and third data according to a two-step programming process, during the program operation, wherein the two-step programming process would compris a first step program in which memory cells having threshold voltages included in a first threshold voltage distribution corresponding to an erase state are programmed to have threshold voltages included in a second threshold voltage distribution corresponding to a first program state, according to the first data, and wherein the two-step programming process would further comprise a second step program in which the memory cells having threshold voltages included in the first threshold voltage distribution are programmed to have threshold voltages included in one from among a third threshold voltage distribution corresponding to a second program state, a fourth threshold voltage distribution corresponding to a third program state, and a fifth threshold voltage distribution corresponding to a fourth program state according to the second data and the third data, and memory cells including threshold voltages included the second threshold voltage distribution are programmed to have threshold voltages included in one from among a sixth threshold voltage distribution corresponding to a fifth program state, a seventh threshold voltage distribution corresponding to a sixth program state, an eighth threshold voltage distribution corresponding to a seventh program state, and a ninth threshold voltage distribution corresponding to an eighth program state according to the second data and the third data. The motivation to do so would have been to use a 2-step programming method already known at the time to be suitable for programming multi-bit memory cells as exemplified by Kim.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. (US 2024/0161834) as modified by Nam et al. (US 9,508,441), and further in view of Cho et al. (2023/0253044).
Regarding claim 10: Heo as modified above does not specifically teach the memory device of claim 1, further comprising: a first chip comprising a peripheral circuit region comprising the control logic circuit, wherein the peripheral circuit region is on a first surface of a first substrate of the first chip; and a second chip comprising three-dimensional arrays comprising the plurality of memory cells of the memory cell array, wherein the three-dimensional arrays are on a first surface of a second substrate of the second chip, and wherein the second chip is vertically stacked on the first chip, and the first surface of the first substrate of the first chip is bonded to the first surface of the second substrate of the second chip.
Cho (FIG. 18; [0037, 0133, 0134]) teaches a memory device comprising: a first chip comprising a peripheral circuit region comprising the control logic circuit, wherein the peripheral circuit region is on a first surface of a first substrate of the first chip; and a second chip comprising three-dimensional arrays comprising the plurality of memory cells of the memory cell array, wherein the three-dimensional arrays are on a first surface of a second substrate of the second chip, and wherein the second chip is vertically stacked on the first chip, and the first surface of the first substrate of the first chip is bonded to the first surface of the second substrate of the second chip. Note that FIG. 18 is identical to Applicant’s FIG. 15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Cho into the device and/or method of Heo as modified above in a manner such that teach the memory device of claim 1, would further comprise: a first chip comprising a peripheral circuit region comprising the control logic circuit, wherein the peripheral circuit region is on a first surface of a first substrate of the first chip; and a second chip comprising three-dimensional arrays comprising the plurality of memory cells of the memory cell array, wherein the three-dimensional arrays are on a first surface of a second substrate of the second chip, and wherein the second chip is vertically stacked on the first chip, and the first surface of the first substrate of the first chip is bonded to the first surface of the second substrate of the second chip. The motivation to do so would have been to include the memory device of Heo as modified above into a chip-to-chip memory device structure already known in the art at the time of invention to be suitable as a memory device structure, wherein a horizontal area of the memory device may be effectively reduced, and a degree of integration of the memory device may be improved, as exemplified by Cho.
Allowable Subject Matter
Claims 4-6, 13, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the control logic circuit is further configured to provide the precharge voltage to a selected bit line coupled to the selected cell string during the precharge duration [reason] in combination with the other limitations thereof as is recited in the claim. Claims 5-6 depend on claim 4.
Regarding claim 13: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of providing the precharge voltage to a selected bit line coupled to the selected cell string during the precharge duration in combination with the other limitations thereof as is recited in the claim.
Regarding claim 18: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of providing the ground voltage to a common source line coupled to a plurality of ground select transistors included in the plurality of cell strings, during the precharge duration and the program execution duration in combination with the other limitations thereof as is recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827