DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12113445 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12113445 B2 anticipate the claims of the immediate application.
Regarding claim 1, U.S. Patent No. 12113445 B2 teaches a method of sensing a negative half-cycle in an AC input voltage at an input of a power converter (Claim 1; Col. 37 Line 62-63), the method comprising: determining that a first voltage at the input of the power converter is less than or equal to a first threshold (Claim 1; Col. 37 Line 61); turning on a high-side switch of the power converter for a first time period (Claim 1; Col. 37 Lines 64-65); measuring, during the first time period, a second voltage at the input of the power converter (Claim 1; Col. 37 Lines 66-67); in response to measuring that the second voltage is not less than a second threshold, turning off the high-side switch and repeating, after a time delay, the steps of turning on the high-side switch and measuring the second voltage (Claim 1; Col. 38 Lines 1-3; This limitation says less than a first threshold which is NOT a second threshold thus meeting the claim limitation set); and in response to measuring that the second voltage is less than the second threshold, maintaining the high-side switch in an ON state for a second time period (Claim 1; Col. 38 Lines 4-6).
Regarding claim 2, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 1 and further teaches wherein the second threshold is a negative value (Claim 4).
Regarding claim 3, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 1 and further teaches wherein measuring that the second voltage is not less than the second threshold comprises measuring that the second voltage is less than a third threshold (Claims 1+2).
Regarding claim 4, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 3 and further teaches wherein the third threshold corresponds to a forward voltage drop of a diode corresponding to a low-side switch (Claim 2).
Regarding claim 5, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 1 and further teaches wherein the first threshold is one selected from the group of approximately 3 V and approximately 0 V (Claims 1+3).
Regarding claim 6, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 1 and further teaches wherein the second time period is longer than the first time period (Claim 5).
Regarding claim 7, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 1 and further teaches turning on a low-side switch; measuring, at a first time, a third voltage at the input of the power converter; and if the third voltage is positive, determining that the first time corresponds to a positive half-cycle of the AC input voltage (Claim 1).
Regarding claim 8, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 7 and further teaches wherein the low-side switch and the high-side switch are operated as mutually exclusive switches (Claim 8).
Regarding claim 9, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 1 and further teaches prior to turning on the high-side switch, measuring a DC bus voltage (Claim 9).
Regarding claim 10, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 9 and further teaches wherein measuring the second voltage comprises computing a fourth voltage equal to the second voltage minus the DC bus voltage (Claim 10).
Regarding claim 11, U.S. Patent No. 12113445 B2 teaches a method of forming guard bands at a zero crossing of an AC input signal (Claim 11; Col. 38 Lines 31-32), the method comprising: turning on a high-side switch for a first time period (Claim 11; Col. 38 Line 40); measuring a first voltage corresponding to the AC input signal (Claim 11; Col. 38 Lines 41-42); computing a second voltage using the first voltage (Claim 11; Col. 38 Line 43); determining that the second voltage is less than a first threshold (Claim 11; Col. 38 Lines 44-45); turning on the high-side switch for a second time period (Claim 11; Col. 38 Line 46); measuring a third voltage corresponding to the AC input signal (Claim 11; Col. 38 Lines 47-48); computing a fourth voltage using the third voltage (Claim 11; Col. 38 Line 49); determining that the fourth voltage is greater than a second threshold (Claim 11; Col. 38 Lines 50-51); turning off the high-side switch (Claim 11; Col. 38 Line 52); and turning on a low-side switch (Claim 11; Col. 38 Line 53).
Regarding claim 12, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 11 and further teaches measuring, after turning on the low-side switch (Claim 11; Col. 38 Line 33), a fifth voltage corresponding to the AC input signal (Claim 11; Col. 38 Lines 34-35); determining that the fifth voltage is less than or equal to a third threshold (Claim 11; Col. 38 Lines 36-37), wherein the third threshold corresponds to a forward voltage drop of a diode corresponding to the low-side switch (Claim 12); turning off the low-side switch (Claim 11; Col. 38 Line 38); waiting a first predetermined time (Claim 11; Col. 38 Line 39); and turning on the high-side switch for the first time period (Claim 11; Col. 38 Line 40).
Regarding claim 13, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 11 and further teaches measuring a DC bus voltage, wherein computing the second voltage comprises subtracting the DC bus voltage from the first voltage (Claim 13).
Regarding claim 14, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 11 and further teaches wherein the first threshold is a negative value (Claim 14).
Regarding claim 15, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 11 and further teaches wherein the second threshold is a negative value (Claim 15).
Regarding claim 16, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 11 and further teaches waiting a second predetermined time before turning on the low-side switch (Claim 16).
Regarding claim 17, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 11 and further teaches measuring a sixth voltage corresponding to the AC input signal; and determining that the sixth voltage is greater than zero before turning on the low-side switch (Claim 17).
Regarding claim 18, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 17 and further teaches determining that the sixth voltage is greater than a forward voltage drop of a diode corresponding to the low-side switch before turning on the low-side switch (Claim 18).
Regarding claim 19, U.S. Patent No. 12113445 B2 teaches a method of sensing a negative half-cycle in an AC input signal at an input of a power converter (Claim 19), the method comprising: turning on a high-side switch for a first time period (Claim 19; Col. 40 Line 4); measuring, during the first time period, a first voltage corresponding to the AC input signal (Claim 19; Col. 40 Lines 5-6); if the first voltage is less than a first threshold, turning off the high-side switch and repeating the steps of turning on the high-side switch and measuring the first voltage after a second time period (Claim 19; Col. 40 Lines 7-10); and if the first voltage is less than a second threshold, maintaining the high-side switch in an ON state for a remainder of the negative half-cycle (Claim 19; Col. 40 Lines 11-12).
Regarding claim 20, U.S. Patent No. 12113445 B2 teaches all the limitations of claim 19 and further teaches measuring, during a positive half-cycle in the AC input signal, a second voltage corresponding to the AC input signal (Claim 19; Col. 38 Line 11-12), wherein the second voltage is measured through a diode of a low-side switch (Claim 19; Col. 38 Lines 16-18); determining that the second voltage is less than or equal to approximately zero (Claim 20); waiting a second time period; and turning on the high-side switch for the first time period (Claim 19; Col. 40 Line 3).
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended or have a terminal disclaimer filed to overcome the double patenting rejection, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests in response to measuring that the second voltage is not less than a second threshold, turning off the high-side switch and repeating, after a time delay, the steps of turning on the high-side switch and measuring the second voltage; and in response to measuring that the second voltage is less than the second threshold, maintaining the high-side switch in an ON state for a second time period. Claims 2-10 depend upon claim 1.
Regarding claim 11, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests turning on the high-side switch for a second time period; measuring a third voltage corresponding to the AC input signal; computing a fourth voltage using the third voltage; determining that the fourth voltage is greater than a second threshold; turning off the high-side switch; and turning on a low-side switch. Claims 12-18 depend upon claim 11.
Regarding claim 19, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests if the first voltage is less than a first threshold, turning off the high-side switch and repeating the steps of turning on the high-side switch and measuring the first voltage after a second time period; and if the first voltage is less than a second threshold, maintaining the high-side switch in an ON state for a remainder of the negative half-cycle. Claim 20 is dependent upon claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chin (US 2023/0198381) teaches a power factor correction circuit and power converter. Chin is the closest prior art reference that could be located in the search conducted by the Examiner. Chin teaches a totem pole PFC circuit (Figure 6 Component 2) within a power converter (Figure 6), wherein the power converter further comprises: a controller (Figure 6 Component 5), wherein the controller employs a method for controlling the PFC circuit, wherein the method comprises: method of detecting zero crossings in an AC input voltage at an input of a power converter, measuring, at a first time, a first voltage at the input of the power converter (Figure 10 Components 52 and 53 measure the input of the power converter); if the first voltage is positive: determining that the first time corresponds to a positive half-cycle of the AC input voltage (Figure 10 Components 6 and 7 based on the reading can determine if the voltage is positive or negative); and if an overvoltage compared to a first threshold is detected to turn off the switch in the PFC circuit and repeat the steps after a delay (Figure 10 Components 74 and Delay 1). Chin further teaches other embodiments that include comparing the voltage to a second threshold value, however, Chin does not teach determining if the first voltage is equal to approximately zero: a) determining that the first time corresponds to a negative half-cycle of the AC input voltage; b) turning on a high-side switch of the power converter for a first time period; and c) measuring, during the first time period, a second voltage at the input of the power converter; if the second voltage is less than a first threshold, turning off the high-side switch and repeating b) and c) after a time delay; and if the second voltage is less than a second threshold, maintaining the high-side switch in an ON state for a second time period.
Chalermboon (US 8934273) teaches a switching power supply including power factor correction circuit with polarity determination control. Chalermboon teaches a method (Figure 1; Figure 2; Figure 4) of measuring an AC input voltage at an input of a power converter (Figure 1 Components VSL+VSN; Figure 4 Components S105+S110), the method comprising: measuring a DC bus voltage corresponding to the power converter (Figure 1 Component 8); during a positive AC half-cycle of the AC input voltage: measuring a first voltage at the input of the power converter (Figure 4 Components S104-S106); during a negative AC half-cycle of the AC input voltage: turning on a high-side switch (Figure 2 shows a switch is activated in the negative half cycle of the AC input voltage); measuring a second voltage at the input of the power converter (Figure 4 Components S110-S111); computing a third voltage equal to a subtraction between two voltage values of the input voltage (Figure 4 Component S111) and providing the computed voltage during the negative half cycle (Figure 2 Component VSLO shows that a computed voltage with an offset value is outputted during the negative half cycle of the AC input voltage).
Matsuura (US 2019/0319528) teaches a switching power supply includes a power converter with an inductor and first and second switches that converts a voltage Vac to a voltage Vdc, a detector with a winding that detects zero timing of an inductor current, and a driving signal generator that switches on the second switch based on the zero timing and then switches on the first switch. Matsuura was the closest secondary reference that could be located wherein an on-time period was determined based on a difference between the DC bus voltage and the AC input voltage (Abstract).
Lee (US 2018/0054118) teaches a zero-voltage switch mode power converter. Lee teaches a DC-DC converter comprising a control scheme that employs zero voltage switching (Figure 3), wherein the zero voltage switching control is employed through a variable delay circuit based on the voltage parameters in the feedback network.
Lu (US 2013/0163295) teaches a power supply converter (Figure 3) with a pre-regulator wherein the controller for the pre-regulator switch is controlled based on measuring the rectified AC voltage and comparing it to a first and second threshold voltage.
Lin (US 2016/0241132) teaches a control device and method of totem-pole bridgeless PFC soft switching within a power converter. Lin teaches a power converter (Figure 3), comprising: a voltage detecting module (Figure 3 Component Voltage Detecting Module) that determines when the PFC inductor reverses thus indicating a polarity change and using a signal processing module to generate control signals for the switches based on the voltage detecting module.
Ohashi (US 11411508) teaches a power conversion device includes: a voltage conversion circuit that converts an AC voltage input into a DC voltage by PWM control and outputs the DC voltage; an input voltage detection circuit that detects the AC voltage input to the voltage conversion circuit and outputs a detection signal; an input current detection circuit that detects an AC current input to the voltage conversion circuit and outputs a detection signal; an output voltage detection circuit that detects the DC voltage output from the voltage conversion circuit and outputs a detection signal; and a control circuit that corrects a phase of a PWM signal for the PWM control based on the detection signal from the input voltage detection circuit, the detection signal from the input current detection circuit, and the detection signal from the output voltage detection circuit, and outputs the PWM signal corrected to the voltage conversion circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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