Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Claims 1-11 are pending.
Action on merits of claims 1-11 as follows.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on August 23rd and February 24th, 2025 have been considered by the examiner.
Drawings
The drawings filed on 08/23/2024 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 respectively of US Patent No. 11,557,644. This is a provisional double patenting rejection because the patentably indistinct claims have not in fact been patented.
The subject matter claimed in the instant application is fully disclosed in the referenced copending application and would be covered by any patent granted on that copending application since the referenced copending application and the instant application are claiming common subject matter, as follows: Although the claims at issue are not identical, they are not patentably distinct from each other because they are the same concept.
Furthermore, there is no apparent reason why applicant would be prevented from presenting claims corresponding to those of the instant application in the other copending application. See In re Schneller, 397 F.2d 350, 158 USPQ 210 (CCPA 1968). See also MPEP § 804.
To be more specific below is a table with the respective claims of the instant application and the US Patent claims:
Instant Claims (18/814361)
US 11,557,644
Claim 1: A display device, comprising: a transparent display panel including a display region and a non-display region adjacent to the display region, the display region including a light-emitting region and a transmissive region;
a first VSS voltage line on a first side of the display region;
a second VSS voltage line on a second side of the display region having at least a portion of the display region positioned between the first VSS voltage line and the second VSS voltage line;
a gate in panel (GIP) circuit region disposed in at least region outside of the display region; and
at least one VSS voltage connection line extending across the display region electrically connecting the first VSS voltage line and the second VSS voltage line to each other.
Claim 9: A transparent display panel including a display region and a non-display region adjacent to the display region, the transparent display panel comprising:
the display region includes at least one light-emitting region and at least one transmissive region;
a first voltage source (VSS) voltage line; and
a second VSS voltage line disposed in parallel in the non-display region, and extended in the same direction while the display region is between the first VSS voltage line and the second VSS voltage line; and
the driving thin-film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer; and
at least one VSS voltage connection line electrically connecting the first VSS voltage line and the second VSS voltage line to each other, wherein the plurality of VSS voltage connection line overlaps with the display region.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of US Patent No. 11,557,644, hereinafter as PAT ‘644, in view of Shin (US 2016/0260383, hereinafter Shin ‘383).
Regarding Claims 1, PAT ‘644 is shown to teach all the features of the claim with the exception of explicitly the features: “a gate in panel (GIP) circuit region disposed in at least one region outside of the display region”.
Shin ‘383 teaches a gate in panel (GIP) circuit region disposed in at least one region outside of the display region (see Fig. 1, (120); [0029]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify PAT ‘644 by having a gate in panel (GIP) circuit region disposed in at least one side region outside of the display region in order to provide the gate signals to gate lines for operate the pixels of the display device (see para. [0031]) as suggested by Shin ‘383.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over An (US 2017/0365217, hereinafter as An ‘217) in view of Xi (US 2015/0279271, hereinafter Xi ‘271) and further in view of Shin (US 2016/0260383, hereinafter Shin ‘383).
Regarding Claim 1, An ‘217 teaches a display device, comprising: a transparent display panel including a display region (DA; [0049]) and a non-display region (NDA; [0049]) adjacent to the display region, the display region including a light-emitting region;
a first VSS voltage line (VW2a; [0049] and [0067]) on a first side of the display region;
a second VSS voltage line (VW2b; [0049] and [0067]) on a second side of the display region, having at least a portion of the display region positioned between the first VSS voltage line and the second VSS voltage line (see Fig. 1); and
at least one VSS voltage connection line (AW; [0049]) extending across a portion of the display region electrically connecting the first VSS voltage line and the second VSS voltage line to each other (see Fig. 1).
Thus, An ‘217 is shown to teach all the features of the claim with the exception of explicitly the features: “the display region including a transmissive region; a gate in panel (GIP) circuit region disposed in at least one region outside of the display region”.
Xi ‘271 teaches the display region including a transmissive region (Fig. 1, (120); [0025]);
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify PAT ‘644 by having the display region including a transmissive region in order to improve the blur issue for the background image due to the data lines and the power being overly concentrated at specific positions of the display device (see para. [0010]) as suggested by Xi ‘271.
Thus, An ‘217 and Xi ‘271 are shown to teach all the features of the claim with the exception of explicitly the features: “a gate in panel (GIP) circuit region (SL) disposed in at least one region outside of the display region”.
Shin ‘383 teaches a gate in panel (GIP) circuit region disposed in at least one region outside of the display region (see Fig. 1, (120); [0029]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify PAT ‘644 by having a gate in panel (GIP) circuit region disposed in at least one side region outside of the display region in order to provide the gate signals to gate lines for operate the pixels of the display device (see para. [0031]) as suggested by Shin ‘383.
Regarding Claim 6, An ‘217 teaches the first VSS voltage line (VW2a) and the second VSS voltage line (VW2b) are parallel to each other and positioned on opposite sides of the display region (see Fig. 1).
Regarding Claim 7, An ‘217 teaches the light-emitting region includes a driving thin-film transistor (Fig. 3, (TFT); [0086]), wherein the driving thin-film transistor includes a gate electrode (GE), a source electrode (SE), a drain electrode (DE), and an active layer CR).
Further, it has been held to be within the general skill of a worker in the art to have the first VSS voltage line, the second VSS voltage line, the source electrode, and the drain electrode are made of the same material and constitute the same layer on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding Claim 8, An ‘217 teaches the at least one VSS voltage connection line includes a plurality of VSS voltage connection lines (see Fig. 1).
Further, it has been held to be within the general skill of a worker in the art to have a plurality of VSS voltage connection lines on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding Claim 9, An ‘217 teaches the at least one VSS voltage connection line includes a first VSS voltage connection line and a second VSS voltage connection line to provide a plurality of VSS voltage connection lines that extend across the display (see Fig. 1).
Further, it has been held to be within the general skill of a worker in the art to have the first VSS voltage connection line, the source electrode, and the drain electrode are made of the same material and constitute the same layer, and wherein the second VSS voltage connection line and the gate electrode are made of the same material and constitute the same layer on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding Claim 10, An ‘217 teaches the gate in panel (GIP) circuit region (GDa and GDb; [0142]) includes a transparent region (see Figs. 9 and 10; [0014] and [0157]).
Regarding Claim 11, An ‘217 teaches the non-display region includes the transparent region (see para. [0014] and [0157]).
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Li et al. (US 2021/0013289 A1)
Zeng (US 2019/0157377 A1)
Ahn (US 2014/0239823 A1)
Gu et al. (US 2014/0368416 A1)
Ono et al. (US 2014/0299867 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
Prosecution Insights