DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/814,428 filed on 08/23/2024. Claims 1-20 are pending in the office action.
Claim Objections
Claims 15-16 are objected to because of the following informalities:
As per claim 15: line 1, replaces “claim 1” with -- claim 13 --.
As per claim 16: line 1, replaces “claim 1” with -- claim 13 --.
Appropriate correction is required.
Double Patenting
Claim 1 and 13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 11 of copending Application No. 18/814,432 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the current application is a broader scope of claimed invention. Hence, the claim language is slightly different.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention using the co-pending application to achieve similar result of the current claimed invention without undue experiment.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current Application 18/814,428
As per claim 1: A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
generating, based on a first mask layout, a simulated wafer image comprising predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC; identifying a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC, wherein the first and second IC components are related components in the IC; and
based on the cross-sectional overlap, modifying the first mask layout to generate a modified second mask layout for the first layer.
Co-Pending Appl.18/814,432
As per claim 1: A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
based on an initial mask layout for a first layer of the design layout, generating a simulated wafer image comprising shapes representing IC components of the first layer, the first layer comprising a first IC component that overlaps with a second IC component on a second layer of the design layout;
identifying, in the simulated wafer image, a more critical first region and a less critical second region of a first shape of the first IC component that both overlap with a second shape of the second IC component, wherein the more critical first region is more important to ensuring overlap of the first IC component shape with the second IC component shape than the less critical second region; and
to improve overlap between the first and second shapes, using different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout to produce a mask to use to manufacture the IC.
Claims 13 is similar rejected as above with respect to claim 11 of co-pending application 18/814,432.
Claim 1 and 13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 12 of copending Application No. 18/814,426 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the current application is a broader scope of claimed invention. Hence, the claim language is slightly different.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention using the co-pending application to achieve similar result of the current claimed invention without undue experiment.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current Application 18/814,428
As per claim 1: A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
generating, based on a first mask layout, a simulated wafer image comprising predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC;
identifying a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC, wherein the first and second IC components are related components in the IC; and
based on the cross-sectional overlap, modifying the first mask layout to generate a modified second mask layout for the first layer.
Co-Pending Appl.18/814,426
As per claim 1. A method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components, the method comprising:
receiving a mask layout comprising a set of mask images corresponding to a first layer of components of the IC that is adjacent to at least a second layer of components;
generating a first wafer image comprising representations of IC components that are predicted to be manufactured for the first layer based on the received set of mask images corresponding to the first layer; and
based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image for the second layer, modifying at least one mask image in the set of mask images for the first layer.
Claims 13 is similar rejected as above with respect to claim 12 of co-pending application 18/814,426.
Claim 1 and 13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 11 of copending Application No. 18/814,430 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the current application is a broader scope of claimed invention. Hence, the claim language is slightly different.
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention using the co-pending application to achieve similar result of the current claimed invention without undue experiment.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current Application 18/814,428
As per claim 1: A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
generating, based on a first mask layout, a simulated wafer image comprising predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC;
identifying a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC, wherein the first and second IC components are related components in the IC; and
based on the cross-sectional overlap, modifying the first mask layout to generate a modified second mask layout for the first layer.
Co-Pending Appl.18/814,430
1. A method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
based on an initial mask layout for a first layer of a design layout, generating a simulated wafer image comprising shapes representing IC components of the first layer, the first layer comprising a first IC component that has a relationship with a second IC component on a second layer of the design layout;
identifying, in the simulated wafer image, (i) a first set of regions of a first shape of the first IC component that overlap with a second shape of the second IC component and (ii) a second set of regions of the first IC component shape that do not overlap with the second IC component shape; and
to improve overlap between the first shape’s first set of regions and the second shape, modifying the initial mask layout to produce a modified mask layout to produce a mask to use to manufacture the IC.
Claims 13 is similar rejected as above with respect to claim 11 of co-pending application 18/814,430.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1 and 13, recited “modify the first mask layout to generate a modified second mask layout for the first layer” which is unclear the reason why to modify the first mask layout”. Hence, it is indefinite.
Examiner’s remarks: for the broadest interpretation light from the application’s specification, when the constraint is violated, then modify the first mask layout to generate a modified second mask layout for the first layer.
As per claims 2-12 and 14-20 are also rejected because are depended directly or indirectly from claims 1 and 13, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9-10, and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mukherjee et al., (U.S. Pub. 20070220476).
As per claims 1 and 13: Mukherjee discloses a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
generating, based on a first mask layout, a simulated wafer image comprising predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC (‘476, par. [0016], providing a plurality of mask shapes corresponding to a plurality of layers; providing lithographica model for said plurality of layers (included first layer), said models describing process according to which wafer image are transferred form said mask shape to wafer, fig. 4, target poly line shape S1 and simulated wafer image W1 as layer 2 (i.e., first layer), par. [0044] [0045]);
identifying a cross-sectional overlap (i.e., overlay) between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC, wherein the first and second IC components are related components in the IC (‘476, fig. 2-3, cross-section of layers 1-3 and shapes are overlay, par. [0016], determining simulated wafer images resulting from transferring said plurality of mask shapes in accordance with said models; evaluating said simulated wafer images relative to other of said simulated wafer images; fig. 4, par. [0045] and par. [0048], fig. 6A, first shape (poly line shape) S1/ simulated wafer images W1 in layer 2 (i.e., first layer) and second shape (contact shape) S2/ contact image shape W2 in layer 3, (i.e., second layer)); and
based on the cross-sectional overlap, modifying the first mask layout to generate a modified second mask layout for the first layer (‘476, par. [0016], modifying said mask layout to correct said violations, fig. 7, 813-815, fig. 10B, fragment F_11, F_12, and F_13).
As per claims 2 and 14: Mukherjee discloses wherein identifying the cross-sectional overlap comprises assigning a score to a multi-layer interface formed by the first and second shapes based on the identified overlap (‘476, par. [0004], a score of metal and via layers).
As per claims 3 and 15: Mukherjee discloses wherein modifying the first mask layout comprises modifying at least one shape in the first mask layout to increase (i.e., expanded) a size of the cross-sectional overlap between the first and second shapes (‘476, fig. 10B, fragment F_11, F_12, and F_13, see par. [0045]).
As per claims 4 and 16: Mukherjee discloses wherein generating the simulated wafer image comprises generating a plurality of simulated wafer images, each respective simulated wafer image comprising respective predicted manufactured shapes representing IC components that are to be manufactured on the first layer of the IC based on the received mask layout accounting for a respective set of manufacturing process variations (‘475, fig. 6A, plurality of simulated wafer images W1 and W2 are corresponding to plurality of shapes S1 and S2, respectively and also see fig. 10A-12 for process variation as the spacing distance of mask layout).
As per claim 9: Mukherjee discloses wherein identifying the cross-sectional overlap between the first shape and the second shape comprises identifying a plurality of cross-sectional overlaps between a first plurality of shapes representing a first plurality of IC components in the simulated wafer image and a second plurality of shapes representing a second plurality of IC components in the wafer image for the second layer (‘475, fig. 4, plurality of cross-sectionals e.g., R1, R2, and R3, and fig. 6A, as example for second shape).
As per claim 10: Mukherjee discloses wherein cross-sectional overlaps are identified between each respective shape in the first plurality of shapes and a respective shape in the second plurality of shapes with which the respective shape in the first plurality of shapes forms a multi-layer component (‘475, fig. 2-3 and fig. 6A).
Allowable Subject Matter
Claims 5-8, 11-12, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach the follow limitations, comprise:
As per claims 5 and 17: wherein the sets of manufacturing process variations comprise (i) wafer misalignment variations that result in misalignment between the first and second layers and (ii) manufactured size variations that result in the first and second shapes having different sizes.
As per claim 11: further comprising identifying a cross-sectional overlap between a third shape of a third IC component in the simulated wafer image and a fourth shape of a fourth IC component in a wafer image for a third layer of the IC, wherein: the third and fourth IC components are related components in the IC; and optimizing the mask layout for the first layer comprises optimizing the mask layout based on (i) the identified overlap between the first and second shapes and (ii) the identified overlap between the third and fourth shapes.
As per claim 12: further comprising identifying a cross-sectional overlap between the first shape and a third shape of a third IC component in a wafer image for a third layer of the IC, wherein: the first and third IC components are related components in the IC; and optimizing the mask layout for the first layer comprises optimizing the mask layout based on (i) the identified overlap between the first and second shapes and (ii) the identified overlap between the first and third shapes.
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/Primary Examiner, Art Unit 2851