Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 11-15, 9-10, 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Mukherjee et al. [US 2007/0220476 A1].
Taking claim 1 as exemplary of claims 1 and 11 [FIG. 13], a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC), the method comprising:
based on an initial mask layout for a first layer of a design layout [0051 design inputs, all relevant layers], generating a simulated wafer image comprising shapes representing IC components of the first layer [0051 each layer is associated with corresponding models for simulation], the first layer comprising a first IC component that has a relationship with a second IC component on a second layer of the design layout [FIG. 2 and 0041 relationship, 0053 initial set of simulated images];
identifying, in the simulated wafer image [0008, 0010], (i) a first set of regions of a first shape of the first IC component that overlap with a second shape of the second IC component [0047 constraints that ensure functionality among multiple layers are obeyed, 0048 overlaying of shapes, constraints ensure proper functioning of shapes among interacting layers] and (ii) a second set of regions of the first IC component shape that do not overlap with the second IC component shape [0041 in a real mask there can be millions of shapes, 0043 constraints are relaxed or eliminated for shapes that do not violate the overlap constraints]; and
to improve overlap between the first shape’s first set of regions and the second shape [0055 if constraints are violated], modifying the initial mask layout to produce a modified mask layout [0016 modifying said mask layout to correct violations, 0055 modified] to produce a mask to use to manufacture the IC [0056].
Taking claim 2 as exemplary of claims 2 and 12, wherein the first layer is a metal layer comprising a set of interconnect wire segments and the first IC component is a particular interconnect wire segment [0004 metal interconnects, 0008 for proper functioning it is important that each layer overlaps in the proper region and satisfy certain tolerance criteria, that contact layers and metal layers overlap properly and have sufficient overlap regions].
Taking claim 3 as exemplary of claims 3 and 13, wherein the first set of regions comprises at least one region of the particular interconnect wire segment that forms a multi-layer component with a via in a dielectric layer adjacent to the metal layer [0004 via, FIGS. 6A-B, 0048 ensure proper functioning of shapes among interacting layers, need not be limited to sequential interactions, 0049].
Taking claim 4 as exemplary of claims 4 and 14, wherein the first set of regions comprises at least one region of the particular interconnect wire segment that forms a multi-layer component with a contact in a dielectric layer adjacent to the metal layer [0048 ensure proper functioning of shapes among interacting layers, need not be limited to sequential interactions, 0049].
Taking claim 5 as exemplary of claims 5 and 15, wherein the second set of regions comprises a region of the particular interconnect wire segment that does not overlap with any vias in any adjacent dielectric layers [0004, 0041, 0043, following from (ii) in claim 1 above there are regions comprising shapes that do not overlap thus improving the overlap necessary for proper functioning to satisfy tolerance criteria].
Taking claim 9 as exemplary of claims 9 and 19, further comprising, for each respective IC component of a plurality of IC components of the first layer that have relationships with respective IC components on respective additional layers: identifying, in the simulated wafer image, (i) a respective first set of regions of a respective shape of the respective IC component that overlap with a respective shape of at least one IC component in at least one additional layer with which the respective IC component has a relationship and (ii) a respective second set of regions of the respective IC component shape that do not overlap with the respective shape of the IC component with which the respective IC component has a relationship [following from claim 1 citations, 0041 several layers, 0051 some of these additional layers may be used in the simulation due to their influence, 0054 iteration, 0057 several iterations].
Taking claim 10 as exemplary of claims 10 and 20, wherein the modification of the initial mask layout improves overlap between each respective IC component’s first set of regions and the shape of the IC component with which the respective IC component has a relationship [0055-0057 will converge after several iterations].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. [US 2007/0220476 A1] in view of Hamouda [US 2018/0247008 A1].
Taking claim 6 as exemplary of claims 6 and 16, wherein modifying the initial mask layout comprises:
identifying (i) differences between the simulated wafer image and a target wafer image for the first layer [0054 comparing, compared] and (ii) interaction of each region in the first set of regions with shapes representing IC components in additional layers of the design layout [0055 constraints are violated, FIG. 2 and 0041 relationship]; and
modifying the mask layout to reach an extrema [0016 modifying said mask layout to correct violations, 0055 modified, converges].
However, Mukherjee et al. do not teach an objective function.
Hamouda teaches an objective function [0071 model-based judgement provides a more accurate decision and correction].
Considering that both references teach model-based OPC including EPE (see Mukherjee et al. above, Hamouda [0060-0061, 0069-0070]), combining the references would result in identifying an objective function that accounts for (i) differences between the simulated wafer image and a target wafer image for the first layer and (ii) interaction of each region in the first set of regions with shapes representing IC components in additional layers of the design layout; and modifying the mask layout to reach an extrema of the objective function. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because an objective function can be used to improve manufacturing yield and beneficially impact device performance and reliability [0071].
Taking claim 7 as exemplary of claims 7 and 17, wherein the objective function (i) assigns a cost to each region in the first set of regions based on the overlap of the region with a shape representing an IC component in an additional layer of the design layout and (ii) assigns costs to regions based on differences between the region in the simulated wafer image and the target image [from the combination, including the at-risk regions identified in Hamouda 0057, 0067-0068, although the term “cost” is not explicitly stated it is understood that such is determined by an objective function].
Taking claim 8 as exemplary of claims 8 and 18, wherein each region is one of a plurality of evaluation points along a boundary of the representation of the first IC component, wherein the evaluation points in the first set of regions are weighted more heavily in the objective function than the evaluation points in the second set of regions [from the combination and what is known as model-based OPC, Mukherjee et al. 0044 multiple points, 0045 evaluation point].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See, for example, Pang et al. [“TrueMask ILT MWCO”] (entire document); Tel et al. [US 2021/0149312 A1] (entire document, particularly paragraph [0217]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851