Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tian et al. (US 2004/0209423, hereinafter Tian) in view of JP (JP 4132824, hereinafter JP).
With respect to claim 1, Tian discloses a capacitor (Fig. 2k) comprising:
a first electrode (116);
a second electrode (128); and
a dielectric layer (122) positioned between the first electrode and the second
electrode and including at least one embedded doping level (para 0026-0027; doped dielectric layer) and at least one interface doping level (para 0027 – doped interface).
Tian does not explicitly disclose that the dielectric layer is a stack.
In an analogous art, JP discloses that the dielectric layer is a stack (Para 0045 – alternate layers of HfO and Al2O).Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian’s device by having JP’s disclosure in order to improve the storage capacity of the capacitor.
With respect to claim 2, Tian discloses: wherein at least one the embedded doping level is positioned in at least one of the dielectric layer (para 0026-0027) and the seed layers, and wherein the interface doping level is positioned at least one of the direct contact interfaces (para 0027- doped interface).
Tian does not explicitly disclose wherein the dielectric layer stack includes:
a plurality of hafnium oxide layers; a plurality of seed layers; and a plurality of direct contact interfaces that are in direct contact with the hafnium oxide layers and the seed layers, and wherein the dielectric layer comprise of hafnium oxide layer.
In an analogous art, JP discloses wherein the dielectric layer stack includes:
a plurality of hafnium oxide layers (Para 0045 – HfO); a plurality of seed layers (Para 0045 - alternate layers of HfO and Al2O repeat – according applicant’s specs para 0081-0083 – seed layer can comprise of Al2O); and a plurality of direct contact interfaces that are in direct contact with the hafnium oxide layers and the seed layers (Para 0011; 0016; 0026-0027; 0045; and 0050 -layers in contact with 18 & 20)
and wherein the dielectric layer comprise of hafnium oxide layer (para 0045). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian’s device by having JP’s disclosure in order to improve the storage capacity of the capacitor.
With respect to claim 3, Tian/JP discloses the capacitor of claim 2.
Tian does not explicitly disclose wherein at least one the embedded doping level
of the dielectric layer stack include strontium (Sr), lanthanum (La), gadolinium (Gd),
aluminum (Al), silicon (Si), yttrium (Y), zirconium (Zr), niobium (Nb), bismuth (Bi),
germanium (Ge), dysprosium (Dy), titanium (Ti), cerium (Ce), magnesium (Mg), nitrogen
(N), tantalum (Ta), beryllium (Be), calcium (Ca), barium (Ba), indium (In), gallium (Ga),
tin (Sn), lead (Pb), vanadium, or combinations thereof.
In an analogous art, JP discloses wherein at least one the embedded doping level of the dielectric layer stack include aluminum (Al) (Para 0042). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian’s device by having JP’s disclosure in order to improve the storage capacity of the capacitor.
With respect to claim 4, Tian/JP discloses the capacitor of claim 2.
Tian does not explicitly disclose wherein at last one the interface doping level of
the dielectric layer stack include strontium (Sr), lanthanum (La), gadolinium (Gd),
aluminum (Al), silicon (Si), yttrium (Y), zirconium (Zr), niobium (Nb), bismuth (Bi),
germanium (Ge), dysprosium (Dy), titanium (Ti), cerium (Ce), magnesium (Mg), nitrogen
(N), tantalum (Ta), beryllium (Be), calcium (Ca), barium (Ba), indium (In), gallium (Ga),
tin (Sn), lead (Ph), vanadium, or combinations thereof.
In an analogous art, JP discloses wherein at last one the interface doping level of
the dielectric layer stack includes aluminum (Al) (Para 0042). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian’s device by having JP’s disclosure in order to improve the storage capacity of the capacitor.
With respect to claim 5, Tian/JP discloses the capacitor of claim 1.
Tian discloses wherein in the dielectric layer stack, the embedded doping level and the interface doping level include the same dopants or different dopants (Para 0027).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tian/JP in view of Moon et al. (US 2019/0013391, hereinafter Moon).
With respect to claim 10, Tian/JP discloses the capacitor of claim 1.
Tian/JP does not explicitly disclose wherein the dielectric layer stack includes:
a zirconium oxide-based seed layer over the first electrode; a first hafnium oxide layer between the first electrode and the zirconium oxide- based seed layer; and a second hafnium oxide layer between the second electrode and the zirconium oxide-based seed layer, wherein at least one the embedded doping level is positioned in at least one of the first and second hafnium oxide layers and the zirconium oxide-based seed layer.
In an analogous art, JP discloses wherein the dielectric layer stack includes:
a seed layer over the first electrode (Para 0045 – according to applicant’s specs para 0080-0081 – seed layer can comprise of Aluminum oxide); a first hafnium oxide layer between the first electrode and the seed layer (Para 0045); and a second hafnium oxide layer between the second electrode and the seed layer (Para 0045 – HfO and Al2O alternately arranged and repeated), wherein at least one the embedded doping level is positioned in at least one of the first and second hafnium oxide layers and the seed layer (Para 0042 ; and 0055).Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian’s device by having JP’s disclosure in order to improve the storage capacity of the capacitor.
Tian/JP does not explicitly disclose that the seed layer is zirconium oxide-based.
In an analogous art, Moon discloses that the seed layer is zirconium oxide-based (Para 0005 and 0042). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Tian/JP’s device by having Moon’s disclosure in order to improve the insulting properties of a semiconductor device.
Allowable Subject Matter
Claims 6-9, 11-13 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 6, none of the prior art on record disclose or render obvious the claimed limitations including “a plurality of hafnium oxide layers; a doped seed layer having an embedded doping layer; a plurality of undoped seed layers; a plurality of first direct contact interfaces with which the hafnium oxide layers and the undoped seed layers are in direct contact; and a plurality of second direct contact interfaces with which the hafnium oxide layers and the doped seed layer are in direct contact, wherein at least one the embedded doping level is positioned in at least one of the hafnium oxide layers, the doped seed layer and the doped seed layer, and 20 wherein at least one the interface doping level is positioned at least one of the first direct contact interfaces” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 7-9 have been objected because of their dependency on claim 6.
With respect to claim 11, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the dielectric layer stack includes: a first zirconium oxide layer on the first electrode; a zirconium oxide-based seed layer over the first zirconium oxide layer; a second zirconium oxide layer over the zirconium oxide-based seed layer; a first hafnium oxide layer between the first zirconium oxide layer and the 25 zirconium oxide-based seed layer; and a second hafnium oxide layer between the zirconium oxide-based seed layer and the second zirconium oxide layer, wherein at least one the embedded doping level is positioned in at least one of the first and second hafnium oxide layers, the first zirconium oxide layer, the zirconium oxide-based seed layer and the second zirconium oxide layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 12, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the dielectric layer stack includes:
a first zirconium oxide layer on the first electrode; a zirconium oxide-based seed layer over the first zirconium oxide layer; a second zirconium oxide layer over the zirconium oxide-based seed layer; a first hafnium oxide layer between the first zirconium oxide layer and the zirconium oxide-based seed layer; and a second hafnium oxide layer between the zirconium oxide-based seed layer and the second zirconium oxide layer, wherein at least one the embedded doping level is positioned in at least one of the first and second hafnium oxide layers, the first zirconium oxide layer, the zirconium oxide-based seed layer and the second zirconium oxide layer, and at least one the interface doping level is positioned at an interface between the first zirconium oxide layer and the first hafnium oxide layer and an interface between the second hafnium oxide layer and the second zirconium oxide layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 13, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the dielectric layer stack includes:
a hafnium oxide-based dielectric layer including a plurality of tetragonal hafnium oxide layers and a plurality of tetragonal zirconium oxide layers; a leakage blocking layer between the hafnium oxide-based dielectric layer and the second electrode; and an interface control layer between the leakage blocking layer and the second electrode, wherein at least one the embedded doping level is positioned in at least one of the tetragonal hafnium oxide layers and the tetragonal zirconium oxide layers, and at least one the interface doping level is positioned at interfaces between the tetragonal zirconium oxide layers and the tetragonal hafnium oxide layers” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Prosecution Insights