DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2013/0221519) in view of Lewandowski et al. (US 2020/0259064).
Regarding claim 1, Hwang et al. disclose, as shown in Figures, a device comprising:
one or more solder interconnects (170a, 180a) that couple at least one chip (100) to an interposer chip (11); and
one or more solder pillars (170b,180b) between the at least one chip (100) and the interposer chip (11) that are in parallel with the one or more solder interconnects.
Hwang et al. does not disclose the one or more solder interconnects and the one or more solder pillars are one or more injection-molded solder interconnects and one or more injection-molded solder pillars, respectively, and the at least one chip is qubit chip. It is noted that the term “injection-molded” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). However, Lewandowski et al. discloses injection-molded soldering coupling a qubit chip (310, 510, 604) to an interposer (306, 506, 602). Note Figures and [0059] of Lewandowski et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the chip of Hwang et a. being a qubit chip, such as taught by Lewandowski et al. in order to process the multi-complicated tasks faster.
Regarding claim 2, Hwang et al. and Lewandowski et al. disclose the one or more solder pillars maintain a uniform gap between the at least one qubit chip and the interposer chip ([0059] and Figures).
Regarding claim 12, Hwang et al. disclose, as shown in Figures, an apparatus comprising:
at least one chip (100) coupled to an interposer (11) via one or more solder bumps (170a, 180a) at one or more first locations on the interposer;
one or more solder backstops (pillars 170b,180b are function as backstops) at one or more second locations on the interposer that maintain a uniform separation between the at least one chip (100) and the interposer (11).
Hwang et al. does not disclose the one or more solder bumps and the one or more solder backstops are one or more injection-molded solder bumps and one or more injection-molded solder backstops, respectively, and the at least one chip is qubit chip. It is noted that the term “injection-molded” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). However, Lewandowski et al. discloses injection-molded soldering coupling a qubit chip (310, 510, 604) to an interposer (306, 506, 602). Note Figures and [0059] of Lewandowski et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the chip of Hwang et a. being a qubit chip, such as taught by Lewandowski et al. in order to process the multi-complicated tasks faster.
Claim(s) 3-11 and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2013/0221519) in view of Lewandowski et al. (US 2020/0259064) and further in view of Barwicz et al. (US 2019/0162902).
Regarding claim 3, Hwang et al. and Lewandowski et al. disclose the claimed invention including the device as explained in the above rejection. Hwang et al. and Lewandowski et al. do not disclose a melting point of the one or more solder pillars is higher than a melting point of the one or more solder interconnects. However, Barwicz et al. discloses a device having a melting point of one or more solder pillars (130) is higher than a melting point of one or more solder interconnects (140). Note Figures and [0023]-[0024] of Barwicz et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Hwang et al. and Lewandowski et al. having a melting point of the one or more solder pillars being higher than a melting point of the one or more solder interconnects, such as taught by Barwicz et al. in order to significantly reduce the cracking risk of the solder interconnects and to greatly improve the reliability of the package structure.
Regarding claim 4, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars having the same composition (SnAgCu, etc., [0023]-[0024]) as the claimed invention, therefore, it is inherent that the one or more solder pillars are superconductors.
Regarding claim 5, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars having the same composition (SnAgCu, etc., [0023]-[0024]) as the claimed invention, therefore, it is inherent that a yield strength of the one or more solder pillars is between 3,000 pounds per square inch and 15,000 pounds per square inch.
Regarding claim 6, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars having the same composition (SnAgCu, etc., [0023]-[0024]) as the claimed invention, therefore, it is inherent that a yield strength of the one or more solder pillars is between 3,000 pounds per square inch and 15,000 pounds per square inch, and is higher than a yield strength of the one or more solder interconnects.
Regarding claim 7, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars are binary tin alloys, tertiary tin alloys, or quaternary tin alloys ([0023]-[0024]).
Regarding claim 8, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars support the at least one qubit chip in a direct thermalization packaging scheme in a chip stacking packaging scheme.
Regarding claim 9, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars support the at least one qubit chip in a direct thermalization packaging scheme in an area array socket packaging scheme.
Regarding claim 10, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars are located in corners of the interposer chip (Figures).
Regarding claim 11, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder pillars are formed in a continuous loop along a perimeter of the interposer chip (Figures).
Regarding claim 13, Hwang et al. and Lewandowski et al. disclose the claimed invention including the device as explained in the above rejection. Hwang et al. and Lewandowski et al. do not disclose the one or more solder backstops are superconductors that have a yield strength between 3,000 pounds per square inch and 15,000 pounds per square inch. However, Barwicz et al. disclose one or more solders (130) having the same composition (SnAgCu, etc., [0023]-[0024]) as the claimed invention, therefore, it is inherent that the one or more solder backstops are superconductors and having a yield strength between 3,000 pounds per square inch and 15,000 pounds per square inch. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the one or more solder backstops of Hwang et al. and Lewandowski et al. being superconductors that have a yield strength as claimed, such as taught by Barwicz et al. in order to significantly reduce the cracking risk of the solder interconnects, to further improve the uniform separation between the at least one quantum chip and the interposer, and to greatly improve the reliability of the package structure.
Regarding claim 14, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder backstops are binary tin alloys ([0023]-[0024]).
Regarding claim 15, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder backstops are tertiary tin alloys ([0023]-[0024]).
Regarding claim 16, Hwang et al., Lewandowski et al. and Barwicz et al. disclose the one or more solder backstops are binary tin alloys, tertiary tin alloys, etc. ([0023]-[0024]). Hwang et al., Lewandowski et al. and Barwicz et al. do not disclose the one or more solder backstops are quaternary tin alloys ([0023]-[0024]). However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the one or more solder backstops of Hwang et al. and Lewandowski et al. having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 17, Hwang et al. and Lewandowski et al. disclose the claimed invention including the device as explained in the above rejection. Hwang et al. and Lewandowski et al. do not disclose a melting point of the one or more solder backstops is higher than a melting point of the one or more solder bumps. However, Barwicz et al. discloses a device having a melting point of one or more solder backstoprs (130) being higher than a melting point of one or more solder bumps (140). Note Figures and [0023]-[0024] of Barwicz et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Hwang et al. and Lewandowski et al. having a melting point of the one or more solder backstops is greater than a melting point of the one or more solder bumps, such as taught by Barwicz et al. in order to significantly reduce the cracking risk of the solder interconnects and to greatly improve the reliability of the package structure.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
