DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,100,471. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the later clearly dominate the claims of the instant application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,961,585. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the later clearly dominate the claims of the instant application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10,978,117. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the later clearly dominate the claims of the instant application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11, 13, 14, 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims are replete with antecedent and other 112 issues. The Examiner has noted many below, but given the scope of deficiencies Applicant should consider full language of the claims for similar errors.
Claim 1 recites “a first state” and “a second state” without making clear as to what is in the first and second states.
Claim 5 recites “the first CA input circuit” and “the second CA input circuit” which lack antecedent basis.
Claim 13 recites “a first memory device with a control signal asserted”. It is not clear what structural distinguishment is implied for a device to have a signal asserted.
Claim 14 directs “memory device…oriented” but gives no reference as to how or by what features the orientation is based.
Claim 18 recites “a memory controller operably…” which appears text was removed inadvertently.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 6, 7, 10-14, 16 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vergis (US 2017/0255404).
Regarding claim 1, Vergis discloses a memory device, comprising: an interface region (see Figure 4) including: a first input circuit (CA0 for example) configured to generate a first output (see Figure 5, XOR outputs); a second input circuit (CA1 circuit)configured to generate a second output (See Figure 5, XOR outputs from CA1); and a swap circuit (mux 530) positioned between the first input circuit and the second input circuit (muxes are electrically connected between the respective even/odd CA’s), the swap circuit configured to select the first output (CA0 for a first internal signal (CA0_internal) responsive to a first state (Mirror low), and select the second output (CA1) for the first internal signal responsive to a second, different state (high).
Regarding claim 4, Vergis discloses the memory device of claim 1, the interface regions further comprising a third input circuit, a fourth input circuit, a fifth input circuit, and a sixth input circuit, wherein the six input circuits correspond to six input signals (CA2, CA3, etc).
Regarding claim 6, Vergis discloses the memory device of claim 1, wherein the swap circuit is further configured to: select the second output (CA1 output for example) for a second internal signal (CA1_internal) responsive to the first state (non mirror); and select the first output (CA0 output) for the second internal signal responsive to the second, different state (mirror).
Regarding claim 7, Vergis discloses the memory device of claim 1, wherein the interface region is configured in a layout arrangement such that: a first pair of input circuits is adjacently arranged in a mirror relationship in a first direction; and at least one additional pair of input circuits is adjacently arranged in the mirror relationship and arranged in a second direction relative to the first pair of input circuits (see Figure 4, CA0, CA1, etc. in mirrored arrangement and adjacent other CA circuits).
Regarding claim 10, Vergis discloses the memory device of claim 1, wherein the interface region is configured in a layout arrangement such that eight input circuits are adjacently arranged in a two-by-four matrix (see Figure 4, CA’s).
Regarding claim 11, Vergis discloses the memory device of claim 1, wherein the interface region is configured in a layout arrangement such: a first pair of input circuits is adjacently arranged in a mirror relationship in a first direction; a second pair of input circuits is adjacently arranged in the mirror relationship in the first direction; and a third pair of input circuits is adjacently arranged in the mirror relationship in the first direction; wherein the second pair of input circuits is arranged adjacent to the first pair of input circuits in a second direction such that the mirror relationships align, and the third pair of input circuits is arranged adjacent to the first pair of input circuits in the first direction (see Figure 4).
Regarding claim 12, Vergis discloses a memory system, comprising: a number of memory devices (see Figures 1 and 2), each memory device of the number of memory devices comprising: an interface region including: a first input circuit including a first swap circuit for selecting a first output as a first internal signal; and a second input circuit including a second swap circuit positioned between the first input circuit and the second input circuit, the second swap circuit for selecting a second output as a second internal signal (see rejection of claim 1 above).
Regarding claim 13, Vergis discloses the memory system of claim 12, wherein the number of memory devices comprise one or more pairs of memory devices and each pair includes: a first memory device (310) with a control signal asserted; and a second memory device (320) with the control signal negated.
Regarding claim 14, Vergis discloses the memory system of claim 13, wherein for each pair: the first memory device is oriented in a first direction in the memory system; and the second memory device is oriented in a second, different direction in the memory system (there is no reference point describe so “oriented” is arbitrary).
Regarding claim 16, Vergis discloses the memory system of claim 12, wherein the interface region is configured in a layout arrangement such that: a first pair of input circuits is adjacently arranged in a mirror relationship in a first direction; and at least one additional pair of input circuits is adjacently arranged in the mirror relationship and arranged in a second direction relative to the first pair of input circuits (see Figure 4 and rejections above).
Regarding claim 18, Vergis discloses a system, comprising: a memory controller (see Figurd 1) operably one or more memory devices operably coupled to the memory controller, each memory device of the one or more memory devices comprising: an interface region including: a first input circuit to generate a first output; a second input circuit to generate a second output; and a swap circuit positioned between the first input circuit and the second input circuit, the swap circuit to select the first output for a first internal signal responsive to a control signal being in first state, and select the second output for the first internal signal responsive to the control signal being in a second, different state (see rejection of claim 1 above).
Regarding claim 19, Vergis discloses the system of claim 18, wherein the one or more memory devices comprise one or more pairs of memory devices and each pair includes: a first memory device oriented in a first direction; and a second memory device oriented in a second direction (there is no reference point describe so “oriented” is arbitrary).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 , 3, 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vergis in view of Ooishi (US 6,636,110).
Regarding claims 2, 3, 15 and 20, Vergis discloses memory device of claim 1, wherein each of the first CA input circuit and the second CA input circuit includes a buffer circuit (see Figure 5), but fails to teach a latch circuit configured for capturing a state of its corresponding CA input signal responsive to a clock signal.
However, a latch circuit capturing input signals responsive to a clock signals were known in the art at time of filing for use in configuring signal delay for synching purposes (see Ooishi, Figure 10A for example, latch 41).
Therefore, it would have been obvious to those having ordinary skill at the time of filing to provide such a latch in order to sync with clock signals.
Claim(s) 5, 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vergis.
Regarding claim 5, 8 and 17, Vergis discloses the memory device of claim 1, but fails to teach a clock buffer circuit adjacent to at least one of the first CA input circuit or the second CA input circuit. However, clock buffer circuits are well known in the art of memory devices for handling the external clock signal. Furthermore, placing such a buffer circuit very near (adjacent) to the other inputs would have been obvious to one having ordinary skill in the art to conserve area by placing pins adjacent each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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