DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1 and 8.
b. Pending: 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8, 10, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khan US Patent 5687114 (hereinafter Khan).
Regarding independent claim 8, Khan teaches a method, comprising:
determining more than one bit of information stored in a memory cell, wherein the determining comprises:
reading an output of a read port (cell connecting to READ data line 210 in figure 6) of the memory cell (figure 2A/2B, para(58), “…voltage read back from the memory cell…”), wherein the read port has an impedance that varies (para(11), “…a voltage corresponding to the amount of charge stored in the selected memory cell is compared to a reference voltage…”, para(23), “…the amount of current passing through the cell 35 is compared against a set number of currents… current-mode reading could be used in the present invention, reading of memory cells in the voltage-mode is preferred…”) in accordance with, and is indicative of, a data value stored therein, and wherein the data value is one of at least three different data values that the memory cell is capable of storing (abstract, “…amount of charge stored in a memory cell corresponds the multiple bits in a memory cell…”, figure 10 teaches multiple discrete levels, figure 12A shows 4 bits); and
determining is performed by a binary search (Abstract, “…compared against a binary search sequence of reference voltages…”, figure 12A/12B).
Regarding claim 10, Khan teaches The method of claim 8, wherein the memory cell is a non-volatile memory cell (para(4), “…nonvolatile memory array 1…”)
Regarding claim 17, Khan teaches the method of claim 8, wherein the memory cell corresponds to a memory cell of a plurality of memory cells (figure 3 shows memory block0-block3); the binary search to determine the information stored in the plurality of memory cells performed depends on the respective value in each of the plurality of memory cells (abstract, “…During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell…”)
Regarding claim 18, Khan teaches the method of claim 17, wherein the binary search to determine the information stored in the plurality of memory cells requires a logarithmic base two of possible different data values stored in the memory cells (if there are N levels, binary search requires log2(N) comparison, e.g., figure 12A teaches 16 data levels needing 4 comparisons).
Regarding claim 19, Khan teaches the method of claim 8, wherein the binary search is performed by applying a variable reference coupled to the read port of the memory cell (figure 2A teaches reference current 34 is fed into sense amplifier, figure 11 teaches selectable reference ladders, references are selectable and changed per comparison step).
Regarding claim 20, Khan teaches the method of claim 19, wherein the variable reference is a variable reference bias current (figure 2A teaches reference current 34 is used for sensing, figure 2B shows bias current (37) applied at sense node).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over IKEDA PG PUB 20150255157 (hereinafter IKEDA), in view of KUROKAWA PG PUB 20170317085 (hereinafter KUROKAWA).
Regarding independent claim 1, IKEDA teaches a memory cell (figure 3 of IKEDA), comprising:
a data node (FN31 in figure 3B of IKEDA, [0055] of IKEDA, “…a node FN31…”);
a first transistor (MW1 in figure 3B of IKEDA, [0056] of IKEDA, “…A gate of the transistor MW1 is electrically connected to the wiring WWL, one of a source and a drain of the transistor MW1 is electrically connected to the wiring BL, and the other is electrically connected to the node FN31…”);
a second transistor (MR2 in in figure 3B of IKEDA, [0055] of IKEDA, “…a transistor MR1…”);
a third transistor (MR1 in in figure 3B of IKEDA);
a write port (write BL indicated in [0061] of IKEDA, “…In the memory cells … 32, the wiring BL is used as a bit line for writing and reading, but a bit line for writing and a bit line for reading may be separately provided. In such a case, when the wiring BL is used as the bit line for writing, a line used as the bit line for reading is provided to… be electrically connected to the transistor MR2 in the memory cell 32…”) for writing data to be stored in the memory cell; and
a read port (reading BL indicated in [0061] of IKEDA, “…In the memory cells … 32, the wiring BL is used as a bit line for writing and reading, but a bit line for writing and a bit line for reading may be separately provided. In such a case, when the wiring BL is used as the bit line for writing, a line used as the bit line for reading is provided to… be electrically connected to the transistor MR2 in the memory cell 32…”) having a variable impedance that varies in accordance with a data value stored therein ([0056] of IKEDA, “…gate of the transistor MR1 is electrically connected to the node FN31… transistor MR1 amplifies electric charge accumulated in the node FN31 and outputs it as drain current…”, [0057] of IKEDA, “…drain current flowing through the transistor MR1 increases or decreases the potential of the wiring BL…”, stored data at FN31 controls MR1 conduction, therefore, impedance seen at BL varies with stored data).
wherein the second transistor (MR2 in in figure 3B of IKEDA) and third transistor (MR1 in in figure 3B of IKEDA) are coupled in series between the read port (reading BL indicated in [0061] of IKEDA) and a fixed reference (SL in figure 3B of IKEDA, SL is a bias line, not controlled by FN31, and provides a reference potential for current flow); and
the first transistor (MW1 in figure 3B of IKEDA) is coupled between the write port (write BL indicated in [0061] of IKEDA) and the data node (FN31 in figure 3B of IKEDA).
But IKEDA does not teach wherein the data value is one of at least three different data values that the memory cell is capable of storing.
However, Kurokawa teaches multi-level data storage ([0067]-[0069], “…an analog potential can be held at the node N and thus the memory cell MC can be used as an analog memory…the first data can be stored.. potential corresponding to the second data… the third data is supplied to the memory cell MC…”). Kurokawa teaches in figure 3A and [0065]-[0068] that N[i,j] stores a potential corresponding to data, teaches in [0067]-[0069] that output data varies with stored potential ([0068], “…a current corresponding to the potential of the node N flows through the transistor Tr2…”)
It would have been obvious to modify the memory cell of IKEDA to incorporate the analog/multi-level storage and readout technique of Kurokawa in order to enable storage of multiple bits per cell and to perform current-based computation or sensing, thereby improving data density and functionality.
Regarding claim 2, the combination of IKEDA and Kurokawa teaches the memory cell of claim 1, wherein: the write port is coupled with a write bit line (write BL indicated in [0061] of IKEDA, “…In the memory cells … 32, the wiring BL is used as a bit line for writing and reading, but a bit line for writing and a bit line for reading may be separately provided. In such a case, when the wiring BL is used as the bit line for writing, a line used as the bit line for reading is provided to… be electrically connected to the transistor MR2 in the memory cell 32…”); and
the read port (reading BL indicated in [0061] of IKEDA, “…In the memory cells … 32, the wiring BL is used as a bit line for writing and reading, but a bit line for writing and a bit line for reading may be separately provided. In such a case, when the wiring BL is used as the bit line for writing, a line used as the bit line for reading is provided to… be electrically connected to the transistor MR2 in the memory cell 32…”) is coupled with a read bit line.
Regarding claim 4, the combination of IKEDA and Kurokawa teaches the memory cell of claim 2, wherein: the write bit line and the read bit line are orthogonal to each other (arranging the write bit line and the read bit line are orthogonal to each other is just a design choice one can have).
Claims 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khan US Patent 5687114 (hereinafter Khan), in view of Wik US Patent 5841695 (hereinafter Wik).
Regarding claim 9, Khan teaches the method of claim 8, but does not teach wherein the memory cell is a volatile memory cell.
However, Wik teaches in para(12) that “Module 116 determines a digital representation of the sensed first, second and third charges”, teaches in figure 2 a 3T DRAM memory cell, and teaches in para(22) that “sense the third charge by detecting a current through the second transistor”.
Wik teaches memory cells storing charge on capacitors require periodic refresh and are volatile. It would have been obvious to modify the memory cell of Khan to include volatile memory cell taught by Wik, to achieve known advantages such as faster access inherent to DRAM cells.
Regarding claim 11, the combination of Khan and Wik teaches the method of claim 8, wherein the memory cell is a 3T DRAM memory cell (figure 2 of Wik).
Claims 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khan US Patent 5687114 (hereinafter Khan), in view of KUROKAWA PG PUB 20170317085 (hereinafter KUROKAWA).
Regarding claim 12, Khan teaches the method of claim 8, but does not teach wherein the output of the read port is configured to perform a function operation.
However, KUROKAWA teaches in [0059] that “the memory cell MC has a function of supplying a signal corresponding to the product of the first data and the second data to the wiring BX”, teaches in [0062] that “the amount of the current output from the wiring BX corresponds to the result of product-sum operation performed on the basis of the first data and the second data”. Therefore, Kurokawa performs computation (multiple + SUM) on stored data and output results as current.
Kurokawa’s memory cell outputs a current (wiring BX) corresponding to the computed result ([0062]), which constitutes the output of the memory cell read operation. Therefore,, the output of the read port is configured to perform a function operation.It would have been obvious to modify Khan to include Kurokawa’s computation at the read output in order to enable in-memory processing, reduce data movement and improve computational efficiency.
Regarding claim 13, the combination of Khan and Kurokawa teaches the method of claim 12, wherein the function operation is an arithmetic operation (Kurokawa teaches in [0059] multiplication, “…product of the first data and the second data....”)
Regarding claim 14, the combination of Khan and Kurokawa teaches the method of claim 12, wherein the function operation is a logical operation ([0183]-[0185] of Kurokawa, “…A neural network 300 is a hierarchical neural network including a plurality of layers...”, [0189] of Kurokawa, “…A step function, …or the like can be used as the output function…”, Kurokawa teaches use of a step function, which outputs discrete values based on a threshold. Such step function can be binary search behavior and interpreted as logical operation under BRI).
Regarding claim 15, the combination of Khan and Kurokawa teaches the method of claim 12, wherein the function operation is a logistic operation ([0189] of Kurokawa, “…A step function, a linear ramp function, a sigmoid function, or the like can be used as the output function…” sigmoid function has been interpreted as logistic function).
Regarding claim 16, the combination of Khan and Kurokawa teaches the method of claim 12, wherein the function operation is an activation operation ([0189] of Kurokawa, “…output function of the neuron circuit…”)
Allowable Subject Matter
Claims 3, 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is IKEDA (US 20150255157 Al).
IKEDA discloses a semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.
Regarding claim 3 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: further comprising: a fourth transistor; and a second read port; wherein the fourth transistor and the second transistor are coupled in series to the second read port.
Regarding claim 6 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: further comprising: the fourth transistor; and a second write port; wherein the fourth transistor is coupled between the second write port and the data node.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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