Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification submitted 8/26/2024 has been accepted by the examiner.
Drawings
The drawings submitted on 8/26/2024 have been accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted up to this point have been considered by the examiner.
Claim Objections
Claim 3 is objected to because of the following informalities:
The examiner finds the language of claim 3 confusing and proposed the following revision: “wherein each of the plurality of contact plugs corresponds to a conductive layer for local lines, which is disposed at the uppermost portion, among a subset of the plurality of conductive layers for local lines penetrated by the contact plug, and…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nam (US # 20190013237) in view of Park (US # 20190279999).
Regarding Claim 1, Nam (US # 20190013237) teaches a semiconductor memory device (see Fig. 5 and corresponding text) comprising:
an electrode structure (ST) on a semiconductor substrate (10)
a first interlayer insulating layer (insulation layer 11) formed over a semiconductor substrate (10) defined by a cell region (CAR) and a slimming region (CNR);
a stacked structure including a plurality of second interlayer insulating layers (ILD) and a plurality of conductive layers (ELa/ELb) for local lines (servings as WLs), which are alternately stacked on the substrate lines are stacked in a step structure in the slimming region (shown in Fig. 5 stepping down for each VIA plug); and
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a plurality of contact plugs (PLG2, PLG1) formed to penetrate the stacked structure in the slimming region (shown), one of the plurality of contact plugs corresponding to each of the conductive layers for local lines (shown; [0092]),
wherein each of the plurality of contact plugs includes a protrusion part (shown best in Fig. 6A; see protrusion of CP2) protruding horizontally (shown), the protrusion part protrudes toward a sidewall of one of the plurality of second interlayer insulating layers which is disposed over a corresponding conductive layer for local lines among the plurality of conductive layers for local lines (the protrusion extends laterally toward a sidewall of ILD), and the protrusion part is connected to an upper surface (contact between CP2 and an upper surface of ELb is shown in Fig. 6A) of the corresponding conductive layer for local lines (shown).
Although Nam discloses much of the claimed invention, it does not explicitly teach the device comprising a source line layer formed on the first interlayer insulating layer, on which the stacked structure is stacked.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
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For example, Park (US # 20190279999) is in the same or analogous field, and it teaches (see Fig. 10 and corresponding text) a device comprising a source line layer (CSL) formed on a first interlayer insulating layer (619), on which a stacked structure (640, 650) is stacked.
A person having ordinary skill in the art would have recognized that modifying the sub-stack structure of Nam with the MEM-over-PERI suggested by Park would be obvious. Specifically, the modification suggested by Park would be to employ a device comprising a source line layer formed on the first interlayer insulating layer, on which the stacked structure is stacked. The rationale for this obvious modification is that MEM-over-PERI (aka COP, cell-over-peri) provides reduced chip-size and increases integration density ([0122]).
Regarding Claim 2, Nam teaches the semiconductor memory device of claim 1, wherein the protrusion part of each of the plurality of contact plugs extends and protrudes to an end portion (the part in the staircase near the plug) of the corresponding conductive layer for local lines (shown in Figs. 5 and 6).
Regarding Claim 6, Park, as applied to claim 1, teaches the semiconductor memory device of claim 1, further comprising a peripheral circuit structure (portion of PER that corresponds to layers 617 and 613) disposed under the first interlayer insulating layer (619),
wherein the plurality of contact plugs are connected to a plurality of metal lines (680, 689) connected to the peripheral circuit structure ([0099, 123-124]).
Regarding Claim 7, Nam teaches the semiconductor memory device of claim 6, wherein the peripheral circuit structure comprises a row decoder ([0036-38]).
Regarding Claim 9, Park, as applied to claim 1, teaches the semiconductor memory device of claim 1, wherein the first interlayer insulating layer is penetrated by the plurality of contact plugs ([099-101, 123]) and portions of the first interlayer insulating layer which are penetrated by the plurality of contact plugs are spaced apart from the plurality of contact plugs (Nam [0090]).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Nam (US # 20190013237) in view of Park (US # 20190279999) and further in view of Fukuda (US # 20170256588).
Regarding Claim 3, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejections and/or claim objections above, Nam teaches the semiconductor memory device of claim 2, wherein each of the plurality of contact plugs corresponds to a conductive layer for local lines (shown), which is disposed at the uppermost portion (one plug per upmost line)
Although Nam discloses much of the claimed invention, it does not explicitly teach the device wherein each of the plurality of contact plugs corresponds to a conductive layer for local lines that also penetrates a subset of the plurality of conductive layers for local lines.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
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For example, Fukuda (US # 20170256588) is in the same or analogous field, and it teaches a device (see Figs. 3-5 and corresponding text) wherein each of a plurality of contact plugs (Z1) corresponds to an uppermost conductive layer (WL) for local lines that also penetrates a subset of the plurality of conductive layers for local lines (see Fig. 4).
A person having ordinary skill in the art would have recognized that modifying the penetration depth of Nam in view of Park with the plug configuration suggested by Fukuda would be obvious. Specifically, the modification suggested by Fukuda would be to employ a device wherein each of the plurality of contact plugs corresponds to a conductive layer for local lines that also penetrates a subset of the plurality of conductive layers for local lines. The rationale for this obvious modification is that an individually insulated plug provides reduction of short-circuiting ([0036]).
Regarding Claim 4, Fukuda, similar to the 103-combination explained for claim 3, teaches the semiconductor memory device of claim 1, further comprising insulating layers for spacers (109), which are formed on sidewalls of the plurality of contact plugs in regions in which the plurality of contact plugs and the plurality of conductive layers for local lines intersect each other. The rationale for this obvious spacer modification is that an individually insulated plug provides reduction of short-circuiting ([0036]).
Regarding Claim 5, Fukuda, as applied to claim 5, teaches the semiconductor memory device of claim 4, wherein the insulating layers for spacers separate the sidewalls of the plurality of contact plugs from the plurality of conductive layers for local lines (shown in Fig. 5 of Fukuda; see also [0036]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 11296021. Although the claims at issue are not identical, they are not patentably distinct from each other.
Similar claim language is not patentably distinct.
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 12100651. Although the claims at issue are not identical, they are not patentably distinct from each other.
Similar claim language is not patentably distinct.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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