DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of claim 9 “at least one type of work function metal (WFM) formed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The drawings (Figs. 2B and 18-19) show a gate dielectric layer (1802) (paragraph [0092]) directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets, and “at least one type of work function metal (WFM) formed directly on” the gate dielectric layer (1802). The specification does not include drawing wherein “at least one type of work function metal (WFM) formed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-17 are objected to because of the following informalities:
Claim 1 recites “the semiconductor material nanosheets” (lines 5-6, 10, 14, and 15) which should be replaced with “the plurality of semiconductor material nanosheets”, to avoid antecedent basis issue.
Claim 4 (claim 6) recites “the semiconductor material nanosheets” (lines 4-5 and 7-9) which should be replaced with “the plurality of semiconductor material nanosheets”, to avoid antecedent basis issue.
Claim 10 recites “the semiconductor material nanosheets” (line 11) which should be replaced with “the plurality of semiconductor material nanosheets”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “at least one type of work function metal (WFM) formed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets”. However, the specification does not describe an embodiment wherein “at least one type of work function metal (WFM) formed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets”. Specifically, Figs. 2B and 18-19 show that a gate dielectric layer (1802) (paragraph [0092]) is disposed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets (206), and “at least one type of work function metal (WFM) formed directly on” the gate dielectric layer (1802). Thus, it is unclear which particular embodiment applicant is referring to. The specification does not resolve ambiguity of the claim and that renders the claim indefinite.
For compact persecution, the limitations of claim 9 “at least one type of work function metal (WFM) formed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets” are interpreted as forming “at least one type of work function metal (WFM)” directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets covered with a gate dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0130955 to Cheng et al. (hereinafter Cheng) in view of Lin et al. (US 2023/001226, cited in IDS of 08/26/2024, hereinafter Lin).
With respect to claims 1-3, Cheng discloses a semiconductor device (e.g., fork-sheet transistors) (Cheng, Fig. 23, ¶0003, ¶0012-¶0039) including:
a pair of fork sheet transistors (e.g., multi-bridge-channel (MBC) or gate-all-around (GAA) transistors 302 and 304) (Cheng, Fig. 23, ¶0003, ¶0039), each including:
a plurality of vertically stacked, and spaced apart, semiconductor material nanosheets (e.g., 2080) (Cheng, Fig. 23, ¶0034, ¶0039); and
a gate all around (GAA) structure (e.g., 270-1 and 270-2) (Cheng, Fig. 23, ¶0038, ¶0039) formed on the semiconductor material nanosheets (2080);
a dielectric pillar (230) (Cheng, Fig. 23, ¶0022, ¶0034, ¶0039), composed of a first dielectric material (e.g., silicon oxide 226), and located between the pair of fork sheet transistors (e.g., 302 and 304);
first inner spacer portions (e.g., 224) (Cheng, Fig. 23, ¶0022, ¶0039), composed of a second dielectric material (e.g., SiN), located between the dielectric pillar (226) and inner edges of the semiconductor material nanosheets (2080) of each fork sheet transistor (302/304).
Further, Cheng does not specifically disclose second inner spacer portions, composed of the second dielectric material, located between each of the semiconductor material nanosheets, above the semiconductor material nanosheets and below the semiconductor material nanosheets (as claimed in claim 1); wherein the first dielectric material and the second dielectric material have a same composition (as claimed in claim 2); wherein the first dielectric material and the second dielectric material have different compositions (as claimed in claim 3).
However, Lin teaches forming a gate-all-around transistor (Lin, Figs. 1W, 1X, 1Y, 1Z, ¶0003, ¶0014-¶0073) comprising a plurality of semiconductor nanosheets (104) (Lin, Figs. 1W, 1Y, 1Z, ¶0019, ¶0067-¶0069) and a gate all around (GAA) structure (146/148) (Lin, Figs. 1W, 1Z, ¶0057-¶0063, ¶0072) formed on the semiconductor material nanosheets (104), a dielectric pillar (118/124) (Lin, Figs. 1W, 1Y, 1Z, ¶0032-¶0036, ¶0049, ¶0072), composed of a first dielectric material (e.g., 120/122, SiN/SiO2) (Lin, Figs. 1W, 1Y, 1Z, ¶0032), located between the left and right/middle sheet transistors, first inner spacer portions (134) (Lin, Figs. 1W, 1Y, ¶0045, ¶0048, ¶0070, ¶0073, claim 16), composed of a second dielectric material (e.g., SiN or SiCON), located between the dielectric pillar (118/124) and inner edges of the semiconductor material nanosheets (104) of each sheet transistor (e.g., the left and right/middle sheet transistors), and second inner spacer portions (136) (Lin, Figs. 1W, 1Y, ¶0047-¶0048, ¶0070, ¶0073, claim 15), composed of the second dielectric material (e.g., SiN or SiCON), located between each of the semiconductor material nanosheets (104), above the semiconductor material nanosheets (104) and below the semiconductor material nanosheet (104), wherein the first dielectric material (120, SiN) (Lin, Figs. 1W, 1Y, ¶0032, ¶0035, ¶0047, claims 15-16) and the second dielectric material (134/136, SiN) have a same composition, or wherein the first dielectric material (122, SiO2) and the second dielectric material (134/136, SiN) have different compositions, to provide robust gate-all-around transistors with better performance (Lin, Figs. 1W, 1Y, ¶0014, ¶0048, ¶0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Cheng by forming inner spacers including sheet inner spacers as second inner spacer portions located between the semiconductor material nanosheets as aught by Lin to have second inner spacer portions, composed of the second dielectric material, located between each of the semiconductor material nanosheets, above the semiconductor material nanosheets and below the semiconductor material nanosheets (as claimed in claim 1); wherein the first dielectric material and the second dielectric material have a same composition (as claimed in claim 2); wherein the first dielectric material and the second dielectric material have different compositions (as claimed in claim 3), in order to provide robust gate-all-around transistors with better performance (Lin, ¶0014, ¶0048, ¶0070).
Regarding claim 4, Cheng in view of Lin discloses the semiconductor device of Claim 1. Further, Cheng discloses the semiconductor device, wherein the first inner spacer portions (e.g., 224) (Cheng, Fig. 23, ¶0022, ¶0039) include: a first vertical inner spacer portion, extending in a vertical direction parallel to the dielectric pillar (230), and located between a first inner edge (e.g., the left edge) of the dielectric pillar (230) and inner edges of the semiconductor material nanosheets (2080) of one (e.g., 302) of the pair of fork sheet transistors (302/304); and a second vertical inner spacer portion, extending in the vertical direction, and located between a second inner edge (e.g., the right edge) of the dielectric pillar (230) and inner edges of the semiconductor material nanosheets (2080) of another (e.g., 304) of the pair of fork sheet transistors (302/304).
Regarding claim 5, Cheng in view of Lin discloses the semiconductor device of Claim 1. Further, Cheng discloses the semiconductor device, further including: a substrate (202) (Cheng, Fig. 23, ¶0015); and a shallow trench isolation (STI) layer (218) (Cheng, Fig. 23, ¶0020, ¶0021) deposited on the substrate (202), wherein the first inner spacer portions (224) extend, in a vertical direction, from the STI layer (218).
Regarding claim 6, Cheng in view of Lin discloses the semiconductor device of Claim 1. Further, Cheng does not specifically disclose that for each one of the fork sheet transistors, the second inner spacer portions, include: first horizontal spacer portions, extending in a horizontal direction perpendicular to the inner edges of the dielectric pillar, and located between each of the semiconductor material nanosheets; a second horizontal spacer portion, extending in the horizontal direction, and located above a top one of the semiconductor material nanosheets; and a third horizontal spacer portion, extending in the horizontal direction, and located below a bottom one of the semiconductor material nanosheets.
However, Lin teaches forming a gate-all-around transistor (Lin, Figs. 1W, 1X, 1Y, 1Z, ¶0003, ¶0014-¶0073) comprising second inner spacer portions (136) (Lin, Fig. 1Y, ¶0047-¶0048, ¶0070, ¶0073, claim 15), wherein the second inner spacer portions (136), include: first horizontal spacer portions (136), extending in a horizontal direction perpendicular to the inner edges of the dielectric pillar (118/124), and located between each of the semiconductor material nanosheets (104); a second horizontal spacer portion (e.g., a portion of the spacer 132), extending in the horizontal direction, and located above a top one (104) of the semiconductor material nanosheets; and a third horizontal spacer portion (136), extending in the horizontal direction, and located below a bottom one (104) of the semiconductor material nanosheets, to provide robust gate-all-around transistors with better performance (Lin, Figs. 1W, 1Y, ¶0014, ¶0048, ¶0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Cheng/Lin by forming inner spacers including sheet inner spacers as second inner spacer portions located between the semiconductor material nanosheets as aught by Lin, wherein gate-all-around transistors are configured as fork-sheet transistors as taught by Cheng to have the semiconductor device, wherein, for each one of the fork sheet transistors, the second inner spacer portions, include: first horizontal spacer portions, extending in a horizontal direction perpendicular to the inner edges of the dielectric pillar, and located between each of the semiconductor material nanosheets; a second horizontal spacer portion, extending in the horizontal direction, and located above a top one of the semiconductor material nanosheets; and a third horizontal spacer portion, extending in the horizontal direction, and located below a bottom one of the semiconductor material nanosheets, in order to provide robust gate-all-around transistors with better performance; and to configure the gate-all-around transistors as fork sheet transistors to reduce cell dimensions (Lin, ¶0014, ¶0048, ¶0070; Cheng, ¶0012).
Regarding claim 7, Cheng in view of Lin discloses the semiconductor device of Claim 1. Further, Cheng does not specifically disclose that one of the fork sheet transistors of the pair of fork sheet transistors is an NFET, and another of the fork sheet transistors of the pair of fork sheet transistors is a PFET. However, Cheng teaches forming p-well 202P (Cheng, Fig. 23, ¶0039) and the n-well 202N to arrange n-type transistors (302/304) and p-type transistors (306/308) as fork-sheet transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Cheng/Lin by forming n-type transistor and p-type transistor over the p-well and n-well as a pair of fork-sheet transistors as aught by Cheng to have the semiconductor device, wherein one of the fork sheet transistors of the pair of fork sheet transistors is an NFET, and another of the fork sheet transistors of the pair of fork sheet transistors is a PFET, in order to provide fork sheet transistors to reduce cell dimensions (Cheng, ¶0012, ¶0039).
Regarding claim 8, Cheng in view of Lin discloses the semiconductor device of Claim 1. Further, Cheng discloses the semiconductor device, wherein each of the forks sheet transistors (302/304) (Cheng, Fig. 23, ¶0039) is an NFET or each of the forks sheet transistors (306/308) is a PFET.
Regarding claim 9, Cheng in view of Lin discloses the semiconductor device of Claim 1. Further, Cheng discloses the semiconductor device, wherein the GAA structure (270-1/270-2) includes at least one type of work function metal (WFM) (Cheng, Fig. 23, ¶0035) formed directly on the plurality of vertically stacked, and spaced apart semiconductor material nanosheets (2080).
With respect to claims 10-12, Cheng discloses a semiconductor device (e.g., fork-sheet transistors) (Cheng, Fig. 23, ¶0003, ¶0012-¶0039) including:
a substrate (202) (Cheng, Fig. 23, ¶0015);
a pair of fork sheet transistors (e.g., multi-bridge-channel (MBC) or gate-all-around (GAA) transistors 302 and 304) (Cheng, Fig. 23, ¶0003, ¶0039), formed on the substrate (202), each fork sheet transistor including a semiconductor channel region which includes a plurality of vertically stacked, and spaced apart, semiconductor material nanosheets (2080) (Cheng, Fig. 23, ¶0034, ¶0039);
a dielectric pillar (230) (Cheng, Fig. 23, ¶0022, ¶0034, ¶0039), composed of a first dielectric material (e.g., silicon oxide 226), and located between the pair of fork sheet transistors (e.g., 302 and 304);
first inner spacer portions (e.g., 224) (Cheng, Fig. 23, ¶0022, ¶0039), composed of a second dielectric material (e.g., SiN), located between the dielectric pillar (226) and each semiconductor channel region (2080).
Further, Cheng does not specifically disclose second inner spacer portions, composed of the second dielectric material, located between each of the semiconductor material nanosheets, above each semiconductor channel region and below each semiconductor channel region (as claimed in claim 10); wherein the first dielectric material and the second dielectric material have a same composition (as claimed in claim 11); wherein the first dielectric material and the second dielectric material have different compositions (as claimed in claim 12).
However, Lin teaches forming a gate-all-around transistor (Lin, Figs. 1W, 1X, 1Y, 1Z, ¶0003, ¶0014-¶0073) comprising a plurality of semiconductor nanosheets (104) (Lin, Figs. 1W, 1Y, 1Z, ¶0019, ¶0067-¶0069) and a gate all around (GAA) structure (146/148) (Lin, Figs. 1W, 1Z, ¶0057-¶0063, ¶0072) formed on the semiconductor material nanosheets (104), a dielectric pillar (118/124) (Lin, Figs. 1W, 1Y, 1Z, ¶0032-¶0036, ¶0049, ¶0072), composed of a first dielectric material (e.g., 120/122, SiN/SiO2) (Lin, Figs. 1W, 1Y, 1Z, ¶0032), located between the left and right/middle sheet transistors, first inner spacer portions (134) (Lin, Figs. 1W, 1Y, ¶0045, ¶0048, ¶0070, ¶0073, claim 16), composed of a second dielectric material (e.g., SiN or SiCON), located between the dielectric pillar (118/124) and inner edges of the semiconductor material nanosheets (104) of each sheet transistor (e.g., the left and right/middle sheet transistors), and second inner spacer portions (136/132) (Lin, Figs. 1W, 1Y, ¶0041, ¶0047-¶0048, ¶0070, ¶0073, claim 15), composed of the second dielectric material (e.g., SiN or SiCON), located between each of the semiconductor material nanosheets (104), above each semiconductor channel region (e.g., 132, above the stack) and below each semiconductor channel region (e.g., the bottom spacer 136 below the stack 104), wherein the first dielectric material (120, SiN or SiCON) (Lin, Figs. 1W, 1Y, ¶0032, ¶0035, ¶0047, claims 15-16) and the second dielectric material (132/134/136, SiN or SiCON) have a same composition, or wherein the first dielectric material (122, SiO2) and the second dielectric material (132/134/136, SiN or SiCON) have different compositions, to provide robust gate-all-around transistors with better performance (Lin, Figs. 1W, 1Y, ¶0014, ¶0048, ¶0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Cheng by forming inner spacers including sheet inner spacers as second inner spacer portions located between the semiconductor material nanosheets as aught by Lin to have second inner spacer portions, composed of the second dielectric material, located between each of the semiconductor material nanosheets, above each semiconductor channel region and below each semiconductor channel region (as claimed in claim 10); wherein the first dielectric material and the second dielectric material have a same composition (as claimed in claim 11); wherein the first dielectric material and the second dielectric material have different compositions (as claimed in claim 12), in order to provide robust gate-all-around transistors with better performance (Lin, ¶0014, ¶0048, ¶0070).
Regarding claim 13, Cheng in view of Lin discloses the semiconductor device of Claim 10. Further, Cheng discloses the semiconductor device, wherein the first inner spacer portions (e.g., 224) (Cheng, Fig. 23, ¶0022, ¶0039) include: a first vertical inner spacer portion, extending in a vertical direction parallel to the dielectric pillar (230), and located between a first inner edge (e.g., the left edge) of the dielectric pillar (230) and an inner edge of the semiconductor channel region (e.g., the stack 2080) of one (e.g., 302) of the pair of fork sheet transistors (302/304); and a second vertical inner spacer portion, extending in the vertical direction, and located between a second inner edge (e.g., the right edge) of the dielectric pillar (230) and an inner edge of the semiconductor channel region (e.g., the stack 2080) of another (e.g., 304) of the pair of fork sheet transistors (302/304).
Regarding claim 14, Cheng in view of Lin discloses the semiconductor device of Claim 10. Further, Cheng discloses the semiconductor device, further comprising: a shallow trench isolation (STI) layer (218) (Cheng, Fig. 23, ¶0020, ¶0021) deposited on the substrate (202), wherein the first inner spacer portions (224) extend, in a vertical direction, from the STI layer (218).
Regarding claim 15, Cheng in view of Lin discloses the semiconductor device of Claim 10. Further, Cheng does not specifically disclose that one of the fork sheet transistors of the pair of fork sheet transistors is an NFET, and another of the fork sheet transistors of the pair of fork sheet transistors is a PFET. However, Cheng teaches forming p-well 202P (Cheng, Fig. 23, ¶0039) and the n-well 202N to arrange n-type transistors (302/304) and p-type transistors (306/308) as fork-sheet transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Cheng/Lin by forming n-type transistor and p-type transistor over the p-well and n-well as a pair of fork-sheet transistors as aught by Cheng to have the semiconductor device, wherein one of the fork sheet transistors of the pair of fork sheet transistors is an NFET, and another of the fork sheet transistors of the pair of fork sheet transistors is a PFET, in order to provide fork sheet transistors to reduce cell dimensions (Cheng, ¶0012, ¶0039).
Regarding claim 16, Cheng in view of Lin discloses the semiconductor device of Claim 10. Further, Cheng discloses the semiconductor device, wherein each of the forks sheet transistors (302/304) (Cheng, Fig. 23, ¶0039) is an NFET or each of the forks sheet transistors (306/308) is a PFET.
Regarding claim 17, Cheng in view of Lin discloses the semiconductor device of Claim 10. Further, Cheng discloses the semiconductor device, wherein each fork sheet transistor further includes a gate all around (GAA) structure (e.g., 270-1 and 270-2) (Cheng, Fig. 23, ¶0038, ¶0039) which surrounds the plurality of vertically stacked, and spaced apart semiconductor material nanosheets (2080).
With respect to claims 18-20, Cheng discloses a fork-sheet transistor (e.g., 302-308) (Cheng, Fig. 23, ¶0003, ¶0012-¶0039) including:
a source region (260N/260P) (Cheng, Figs. 22-23, ¶0031);
a drain region (260N/260P) (Cheng, Figs. 22-23, ¶0031);
a semiconductor channel region including a plurality of semiconductor material nanosheets (2080) (Cheng, Figs. 22-23, ¶0034, ¶0039), separated from each other, and stacked vertically between the source region (260N/260P) and the drain region (260N/260P); and
a gate all around (GAA) structure (e.g., 270-1 and 270-2) (Cheng, Fig. 23, ¶0038, ¶0039) formed on the plurality of semiconductor material nanosheets (2080),
wherein first inner spacer portions (e.g., 224) (Cheng, Fig. 23, ¶0022, ¶0039), composed of a first dielectric material (e.g., SiN), are located between an edge of the semiconductor channel region and a dielectric pillar (230) (Cheng, Fig. 23, ¶0022, ¶0034, ¶0039), the dielectric pillar (230) being composed of a second dielectric material (226, SiO2) and located adjacent the semiconductor channel region.
Further, Cheng does not specifically disclose second inner spacer portions, composed of the second dielectric material, located between each of the plurality of semiconductor material nanosheets, above the semiconductor channel region and below the semiconductor channel region (as claimed in claim 18); wherein the first dielectric material and the second dielectric material have a same composition (as claimed in claim 19); wherein the first dielectric material and the second dielectric material have different compositions (as claimed in claim 20).
However, Lin teaches forming a gate-all-around transistor (Lin, Figs. 1W, 1X, 1Y, 1Z, ¶0003, ¶0014-¶0073) comprising a plurality of semiconductor nanosheets (104) (Lin, Figs. 1W, 1Y, 1Z, ¶0019, ¶0067-¶0069) and a gate all around (GAA) structure (146/148) (Lin, Figs. 1W, 1Z, ¶0057-¶0063, ¶0072) formed on the semiconductor material nanosheets (104), a dielectric pillar (118/124) (Lin, Figs. 1W, 1Y, 1Z, ¶0032-¶0036, ¶0049, ¶0072), composed of a second dielectric material (e.g., 120/122, SiN/SiO2) (Lin, Figs. 1W, 1Y, 1Z, ¶0032), located between the left and right/middle sheet transistors, first inner spacer portions (134) (Lin, Figs. 1W, 1Y, ¶0045, ¶0048, ¶0070, ¶0073, claim 16), composed of a first dielectric material (e.g., SiN or SiCON), located between the dielectric pillar (118/124) and inner edges of the semiconductor material nanosheets (104) of each sheet transistor (e.g., the left and right/middle sheet transistors), and second inner spacer portions (132/136) (Lin, Figs. 1W, 1Y, ¶0047-¶0048, ¶0070, ¶0073, claim 15), composed of the second dielectric material (e.g., SiN or SiCON), located between each of the semiconductor material nanosheets (104), above the semiconductor channel region (e.g., stack of 104) and below the semiconductor channel region (e.g., stack of 104), wherein the first dielectric material (132/134/136, SiN) (Lin, Figs. 1W, 1Y, ¶0032, ¶0035, ¶0047, claims 15-16) and the second dielectric material (120, SiN) have a same composition, or wherein the first dielectric material (132/134/136, SiN) and the second dielectric material (122, SiO2) have different compositions, to provide robust gate-all-around transistors with better performance (Lin, Figs. 1W, 1Y, ¶0014, ¶0048, ¶0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Cheng by forming inner spacers including sheet inner spacers as second inner spacer portions located between the semiconductor material nanosheets as aught by Lin to have second inner spacer portions, composed of the second dielectric material, located between each of the plurality of semiconductor material nanosheets, above the semiconductor channel region and below the semiconductor channel region (as claimed in claim 18); wherein the first dielectric material and the second dielectric material have a same composition (as claimed in claim 19); wherein the first dielectric material and the second dielectric material have different compositions (as claimed in claim 20), in order to provide robust gate-all-around transistors with better performance (Lin, ¶0014, ¶0048, ¶0070).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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