Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites “… a gate dielectric film surrounding the gate line and separating the at least one nanosheet from the gate line…”. It is unclear what structure relationship is intended by the gate dielectric film “surrounding the gate line”. The specification instead describes gate dielectric film 152 as being disposed between gate line 160 and the nanosheet and describes the gate dielectric film and gate line together as surrounding the nanosheet. Thus, it is unclear whether the claim requires the gate dielectric film itself to surround the gate line, as literally recited, or requires the gate line to surround the nanosheet with the gate dielectric film interposed between the gate line and nanosheet. For the purpose of examination, this limitation is interpretated as requiring the gate line to surround the at least one nanosheet, with the gate dielectric film disposed between the gate line and the nanosheet and electrically separating the nanosheet from the gate line, consistent with the structure described in the specification.
Claims 18-20 inherit the indefiniteness of claim 17 for being dependent on claim 17, hence rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6, 9, 10, 12, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1).
Re: Independent Claim 1, Liu discloses an integrated circuit device comprising:
a plurality of device isolation films extending lengthwise in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction (Liu teaches, in Figs. 23A-23E and also ¶ [0019], isolation features 230. Liu teaches fins 218 extending lengthwise in the X direction and isolation features 230, such as STI structures, formed by filling trenches between the fins with insulating material. Accordingly, the isolation features 230 formed in the trenches between the X-directed fins likewise extend along the X-direction and are laterally spaced from one another in the intersecting Y direction. Liu expressly teaches isolation features 230 isolate fins from each other);
a gap-fill insulating film located between the plurality of device isolation films (Liu teaches, in Fig. 24C and ¶ [0049], dielectric liner 274 and dielectric layer 276 filling backside trenches between retained isolation features 230);
a plurality of gate lines disposed above the gap-fill insulating film and extending lengthwise in the second horizontal direction (Liu, Fig. 23A-23E and ¶ [0048], forms gate stacks 240’ (including gate electrode 350) at the front side of the device and subsequently, from the backside, removes semiconductor layer 204 to form trenches 272 and fills trenches 272 with dielectric liner 274 and dielectric layer 276. Because Liu defines the Z direction as extending from the backside toward the frontside (¶ [0046]), gate stacks 240’ are disposed above the backside dielectric 274/276 in the final device structure);
a plurality of source/drain regions comprising a first source/drain region and a second source/drain region, each of the plurality of source/drain regions located between the plurality of gate lines (Liu teaches, in Fig. 17B-19B, and ¶ [0035], source/drain regions 260. Liu, in ¶ [0029], identifies one source/drain region and another source/drain region of the transistor and forms respective epitaxial S/D features 260 therein. The S/D features 260 are formed in the regions between adjacent gate stacks 240/240’. A selected S/D feature 260 adjoining to semiconductor layer 239 corresponds to the claimed first source/drain region, while another S/D feature 260 corresponds to the claimed second source/drain region);
a backside contact provided below the first source/drain region, the backside contact extending through the gap-fill insulating film and electrically connected to the first source/drain region (Liu teaches, in Fig. 26B, backside source/drain contact 282, formed through the backside dielectric 274/276 to source/drain feature 260).
Liu is silent regarding
a gate protective film provided below the first source/drain region and being in contact with an upper sidewall of the backside contact, wherein at least a portion of a sidewall of the gate protective film is surrounded by the gap-fill insulating film.
However, Wang teaches
a gate protective film provided below the first source/drain region and being in contact with an upper sidewall of the backside contact, wherein at least a portion of a sidewall of the gate protective film is surrounded by the gap-fill insulating film (Wang teaches, in Fig. 30A and ¶¶ [0108] – [0110], a dielectric via spacer 290’ associated with backside via 300 and source epitaxial structure 190S. Via spacer 290’ lines the sidewall of the backside-via opening, contacts the backside of source epitaxial structure 190S, and laterally surrounds/separates backside via 300 from backside dielectric layer 270. Thus, spacer 290’ is below the source/drain region, contacts an upper sidewall of the backside contact, and has an outer sidewall surrounded by the backside dielectric layer. Accordingly, Wang’s via spacer 290’ corresponds to the claimed gate protective film because it has the recited structural relationship. Further, Wang teaches that the spacer may comprise SiC, SiOC, or SiOCN, which are materials expressly recited for the gate protective film in the instant application).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Liu’s backside contact with Wang’s dielectric via spacer because Wang expressly teaches (Wang, ¶ [0088]) that the spacer provides etch selectivity and can protect the backside via opening from unintentionally expanded due to, for example, an etching process used in subsequent silicidation process, thereby maintaining the desired dimensions and isolation of the backside contact. Such modification would have been the predictable use of Wang’s known spacer technique in Liu’s analogous backside source/drain contact structure.
Re: Claim 2, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Wang further teaches
wherein the gate protective film comprises SiGe, SiGeC, SiO, SiC, SiOC, SiOCN, SiOH, GeC, or a combination thereof (Wang teaches, in ¶¶ [0088] and [0108], claimed gate protective film 290/290’ includes silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof).
Re: Claim 6, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Wang further teaches
wherein the gate protective film covers a portion of a lower surface of the first source/drain region, and the backside contact covers the other portion of the lower surface of the first source/drain region (Wang teaches that via spacer 290’ (corresponds to the claimed gate protective film) contacts the backside of source epitaxial structure 190S and laterally surrounds the remaining backside-contact region. Epitaxial regrowth layer 280’ and backside via 300 are formed in the remaining central portion of the backside opening. Thus, spacer 290’ covers a peripheral portion of the lower surface of 190S, while the backside-contact structure covers the remaining portion of 190S).
Re: Claim 9, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Liu further teaches
wherein the gap-fill insulating film comprises a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Liu teaches, in ¶ [0049], dielectric liner 274 comprise silicon nitride and dielectric layer 276 comprise silicon oxide).
Wang further teaches
the gap-fill insulating film surrounds a sidewall of the gate protective film (Wang, via spacer 290’ lining the backside-via opening and laterally separating/surrounding backside via 300 from backside dielectric layer 270. Thus, the outer sidewall of via spacer 290’, corresponding to the claimed gate protective film, is surrounded by backside via 300 from backside dielectric layer 270. Wang further teaches that backside dielectric layer 270 comprises silicon oxide).
Re: Claim 10, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Wang further teaches
wherein a portion of the backside contact, which overlaps the gate protective film in the first horizontal direction, has a horizontal width decreasing in a direction moving from a bottom to a top of the portion of the backside contact (Wang, Fig. 30B, spacer 290’ lines the sidewalls of the backside-via opening and the portion of backside via 300 located between/adjacent the spacer portion has tapered sidewalls such that its horizontal width decreases from the bottom towards the top (since Fig. 30B is the integrated circuit structure is flipped upside down as disclosed in Wang ¶ [0072])).
Re: Claim 12, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Liu further teaches
further comprising a gate dielectric film located between the plurality of source/drain regions and the plurality of gate lines (Liu teaches, in Fig. 19B, gate dielectric layer 349 of gate stacks 240’, disposed between the gate electrode 350 and semiconductor source-drain regions 260).
Wang further teaches
wherein the gate protective film is located between the gate dielectric film and the backside contact, and the backside contact is spaced apart from the gate dielectric film with the gate protective film therebetween (Wang teaches, in Fig. 30A, via spacer 290’, backside via 300, and gate dielectric layer 224; via spacer 290’ lines the sidewall of backside via 300, and the gate-facing portion of spacer 290’ is located between backside via 300 and the adjacent gate dielectric layer 224).
Re: Independent Claim 17, Liu discloses an integrated circuit device comprising:
a plurality of device isolation films extending lengthwise in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction (Liu teaches, in Figs. 23A-23E and also ¶ [0019], isolation features 230. Liu teaches fins 218 extending lengthwise in the X direction and isolation features 230, such as STI structures, formed by filling trenches between the fins with insulating material. Accordingly, the isolation features 230 formed in the trenches between the X-directed fins likewise extend along the X-direction and are laterally spaced from one another in the intersecting Y direction. Liu expressly teaches isolation features 230 isolate fins from each other);
a gap-fill insulating film located between two adjacent device isolation films among the plurality of device isolation films (Liu teaches, in Fig. 24C and ¶ [0049], dielectric liner 274 and dielectric layer 276 filling backside trenches between retained isolation features 230);
at least one nanosheet disposed above the gap-fill insulating film, spaced apart from an upper surface of the gap-fill insulating film in a vertical direction, and facing the upper surface of the gap-fill insulating film (Liu teaches, channel layers/nanosheets 215 and backside dielectric liner 274/dielectric layer 276. During backside processing, semiconductor layer 204 is removed from beneath the transistor structure to form backside trenches 272, which are subsequently filled with dielectric liner 274 and dielectric layer 276. Accordingly, in the completed structure, channel layer 215 are disposed vertically above and spaces apart from the upper/frontside surface of backside dielectric 274/276, with the lower-facing surface of the channel layers facing the upper surface of the backside dielectric, thereby satisfying the claimed nanosheet relationship);
a gate line surrounding the at least one nanosheet above the gap-fill insulating film and extending lengthwise in the second horizontal direction intersecting the first horizontal direction (Liu teaches, in Fig. 20C, after removal of the sacrificial semiconductor layers, gate dielectric 349 and gate electrode 350 are formed around the exposed channel layers 215, such that the functional gate stack 240’ surrounds the nanosheets in a gate-all-around configuration. Liu further teaches that gate stacks 240’ extend lengthwise in the Y-direction, which is perpendicular to the X-direction. Because backside dielectric 274/276 is formed beneath the transistor structure, gate stack 240’ is disposed above the mapped gap-fill insulating film);
a gate dielectric film surrounding the gate line and separating the at least one nanosheet from the gate line (Liu teaches, in Fig. 20C, gate dielectric layer 349 surrounds portions of gate electrode 350, and separating channel layers 215 and gate electrode 350);
a first source/drain region and a second source/drain region (Liu teaches, in Fig. 17B-19B, and ¶ [0035], respective source/drain regions 260. Liu, in ¶ [0029], identifies one source/drain region and another source/drain region of the transistor and forms respective epitaxial S/D features 260 therein. A selected S/D feature 260 adjoining to semiconductor layer 239 corresponds to the claimed first source/drain region, while another S/D feature 260 corresponds to the claimed second source/drain region) each disposed above the gap-fill insulating film (because backside dielectric 274/276 is formed beneath the transistor structure during backside processing, both source/drain features 260 are disposed above 274/276) and adjacent to the gate line (the S/D features 260 are formed adjacent gate stacks 240/240’) and in contact with the at least one nanosheet (Liu shows, in Fig. 30B, source/drain features 260 are in contact with the exposed end portions of channel layers 215);
a backside contact extending from a level of a lower surface of the gap-fill insulating film in the vertical direction to a lower surface of the first source/drain region (Liu, Fig. 31, backside source/drain contact 282 extending through backside dielectric 274/276 to a selected source/drain feature 260);
a source/drain contact provided above the second source/drain region and electrically connected to the second source/drain region (Liu, Fig. 31, frontside source/drain contact 275, with silicide 273, electrically connected to the source/drain feature 260), and
wherein the gap-fill insulating film comprises a silicon oxide film (Liu teaches, in ¶ [0049], dielectric layer 276 comprise silicon oxide).
Liu is silent regarding
the backside contact covering a portion of the lower surface of the first source/drain region;
a gate protective film located between the backside contact and the gap-fill insulating film and covering the other portion of the lower surface of the first source/drain region; and
the gate protective film comprises a silicon carbide film.
However, Wang teaches
the backside contact covering a portion of the lower surface of the first source/drain region (Wang teaches, in Fig. 30A, epitaxial regrowth layer 280’ and backside via 300 covering portion of source epitaxial structure 190S);
a gate protective film located between the backside contact and the gap-fill insulating film and covering the other portion of the lower surface of the first source/drain region (Wang teaches, in Fig. 30A, source epitaxial structure 190S, via spacer 290’, epitaxial regrowth layer 280’, backside via 300, and backside dielectric layer 270. Via spacer 290’ lines the backside-via opening, is positioned between the backside contact region 300 and backside dielectric layer 270, and contacts a peripheral portion of the backside/lower surface of source epitaxial structure 190S. The remaining central portion of the lower surface is occupied by epitaxial regrowth layer 280’ and backside via 300, which together form the conductive backside-contact path to source epitaxial structure 190S. Thus, the backside-contact structure 280’/300 covers a portion of the lower surface of the first source/drain region, while spacer 290’ covers the other portion); and
the gate protective film comprises a silicon carbide film (Wang, ¶ [0088] and ¶ [0108], via spacer 290’ comprise silicon carbide).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Liu’s backside contact structure with Wang’s SiC via spacer 290’ along peripheral portions of the lower surface of the selected source/drain region and forming the backside-contact structure 280’/300 on the remaining central portion. Wang teaches that this arrangement provides etch selectively and protects the backside-via opening from unintended enlargement during subsequent processing while maintaining electrical connection to the source/drain region. Applying Wang’s known backside-contact /spacer arrangement to Liu’s analogous backside source/drain contact would therefore have predictably maintained the desired contact dimensions and electrical isolation while providing reliable backside electrical connection to the selected source/drain region.
Re: Claim 20, Liu and Wang disclose all the limitations of claim 17 on which this claim depends.
Liu further teaches
wherein the gate protective film has a sidewall opposite the backside contact, and the sidewall of the gate protective film has a shape inclined diagonally between the first horizontal direction, the second horizontal direction, and the vertical direction (Wang teaches, in Fig. 30B and process explained in ¶ [0086] earlier, via spacer 290’ includes slant portions formed in slant sidewalls opposite of the backside-via 300 extend relative to the horizontal plane and the vertical direction and therefore have the claimed diagonally inclined shape between the first and second horizontal directions and the vertical direction).
Claim(s) 3 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1) further in view of Sarkar (US 20210233768 A1).
Re: Claim 3, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Both Liu and Wang are silent regarding
wherein the gate protective film comprises a silicon carbide film, and a carbon content in the gate protective film is about 3 at% to about 30 at%.
However, Sarkar teaches
wherein the gate protective film comprises a silicon carbide film, and a carbon content in the gate protective film is about 3 at% to about 30 at% (Sarkar teaches, in ¶ [0044], a silicon carbide liner having a carbon content of about 2 at% to about 30 at%, including ranges of about 5-30 at% and 10-30 at%, which overlap the claimed range of about 3-30 at%).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to employ Sarkar’s known SiC composition for Wang’s SiC protective spacer in order to obtain the high degree of conformality and a high resistance to etch chemistries used in subsequent process acts, as taught by Sarkar in ¶ [0044].
Re: Claim 18, Liu and Wang disclose all the limitations of claim 17 on which this claim depends.
Both Liu and Wang are silent regarding
wherein the gate protective film includes carbon in an amount of about 3 at% to about 25 at%.
However, Sarkar teaches
wherein the gate protective film includes carbon in an amount of about 3 at% to about 25 at% (Sarkar teaches, in ¶ [0044], a silicon carbide liner having a carbon content of about 2 at% to about 30 at%, including ranges of about 5-30 at% and 10-30 at%, which overlap the claimed range of about 3-25 at%).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to employ Sarkar’s known SiC composition for Wang’s SiC protective spacer in order to obtain the high degree of conformality and a high resistance to etch chemistries used in subsequent process acts, as taught by Sarkar in ¶ [0044].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1) further in view of Lu (US 20220328657 A1).
Re: Claim 4, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Both Liu and Wang are silent regarding
wherein each of the first source/drain region and the second source/drain region comprises: a first semiconductor film; and a second semiconductor film having a sidewall and a lower surface surrounded by the first semiconductor film, wherein each of the first semiconductor film and the second semiconductor film comprises a Si film or a SiGe film.
However, Lu teaches
wherein each of the first source/drain region and the second source/drain region comprises: a first semiconductor film; and a second semiconductor film having a sidewall and a lower surface surrounded by the first semiconductor film (Lu teaches, in Fig. 15 and its description, source/drain structures 190S/190D, first epitaxial layer 192 which corresponds to the claimed first semiconductor film, and second epitaxial layer 194 which corresponds to the claimed second semiconductor film. The second epitaxial layer 194 has lower surface and a portion of sidewall surrounded by first epitaxial layer 192), wherein each of the first semiconductor film and the second semiconductor film comprises a Si film or a SiGe film (Lu teaches, in ¶ [0056], 192 and 194 comprise SiGe).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Liu’s source/drain regions according to Lu’s multilayer epitaxial source/drain structure because Lu teaches that the different epitaxial layers and compositions can be selected to improve source/drain electrical characteristics, including reducing Schottky barrier and reducing contact resistance (Lu, ¶ [0054]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1) further in view of Lu (US 20220328657 A1) and further in view of Glass (US 20190157310 A1).
Re: Claim 5, Liu, Wang and Lu disclose all the limitations of claim 4 on which this claim depends.
Wang further teaches
wherein each of the first semiconductor film and the second semiconductor film comprises a SiGe film (Wang teaches, in ¶ [0057], first SiGe layer 192 and second SiGe layer 194), a ratio of Ge contained in the second semiconductor film is greater than the ratio of Ge contained in the first semiconductor film (Wang teaches, in ¶ [0057], SiGe layer 192 having about 10-20% Ge and second SiGe layer 194 having about 20-60%).
Liu, Wang and Lu are silent regarding
the gate protective film comprises a SiGe film, a ratio of Ge contained in the gate protective film is greater than a ratio of Ge contained in the first semiconductor film.
However, Glass teaches in ¶ [0043], in a backside-contact structure, a SiGe backside contact resistance reduction layer 226 formed on a SiGe source/drain 224, wherein layer 226 has a relatively increased percentage of Ge compared with source/drain region 224. Glass further teaches forming backside contact 290 in the remaining backside contact trench after formation of layer 226.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Glass’s higher-Ge SiGe backside-contact layer into Wang’s protective backside-contact structure because both references concern layer formed adjacent a backside contact to a source/drain region, and Glass teaches that increasing the Ge content of the SiGe layer relative to the SiGe source/drain region improves ohmic contact at the backside contact. Accordingly, the resulting structure would include a SiGe gate protective film having a Ge ratio greater than that of the first SiGe semiconductor film, while Wang teaches the second SiGe semiconductor film having a greater Ge ratio than the first SiGe semiconductor film.
8. Claim(s) 7, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1) further in view of Naskar (US 20220199797 A1).
Re: Claim 7, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Wang further teaches
wherein the gate protective film has a sidewall opposite the backside contact (Wang teaches, In Fig. 30A, via spacer 290’ having inner sidewall facing backside via 300 and an opposite outer sidewall facing away from the backside via).
Both Liu and Wang are silent regarding
the sidewall of the gate protective film has a convex shape protruding in a direction receding from the backside contact.
However, Naskar teaches
and the sidewall of the gate protective film has a convex shape protruding in a direction receding from the backside contact (Naskar teaches, in Fig. 1A, dielectric spacer having an outer sidewall 114B that is convex, where the convex sidewall protrudes outward from the spacer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the outer sidewall of Wang’s dielectric via spacer 290’ with the known convex spacer profile taught by Naskar in order to maintain the dielectric separation provided by the spacer. In the resulting structure, the outer sidewall of spacer 290’, opposite backside via 300, would protrude convexly in a direction receding from the backside contact.
Re: Claim 19, Liu and Wang disclose all the limitations of claim 17 on which this claim depends.
Wang further teaches
wherein the gate protective film has a sidewall opposite the backside contact (Wang teaches, In Fig. 30A, via spacer 290’ having inner sidewall facing backside via 300 and an opposite outer sidewall facing away from the backside via).
Both Liu and Wang are silent regarding
the sidewall of the gate protective film has a curved shape.
However, Naskar teaches
the sidewall of the gate protective film has a curved shape (Naskar teaches, in Fig. 1A, dielectric spacer having an outer sidewall 114B that is convex and curved).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the outer sidewall of Wang’s dielectric via spacer 290’ with the known convex spacer profile taught by Naskar in order to maintain the dielectric separation provided by the spacer. In the resulting structure, the outer sidewall of spacer 290’, opposite backside via 300, would protrude convexly in a direction receding from the backside contact.
9. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1) further in view of Huang (US 20080308899 A1).
Re: Claim 8, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Wang further teaches
wherein the gate protective film has a sidewall opposite the backside contact (Wang teaches, In Fig. 30A, via spacer 290’ having inner sidewall facing backside via 300 and an opposite outer sidewall facing away from the backside via).
Both Liu and Wang are silent regarding
the sidewall of the gate protective film has a pointed shape having a vertical thickness reducing in a direction receding from the backside contact.
However, Huang teaches
the sidewall of the gate protective film has a pointed shape having a vertical thickness reducing in a direction receding from the backside contact (Huang teaches, in Figs. 1 and 2, a dielectric triangular spacer 120/200 having right triangle geometry. Triangular spacer 200 includes an inclined side 210, a vertical side 220 abutting gate electrode 110b, and a horizontal side 230 disposed along substrate 100. Accordingly, spacer 200 has its greatest vertical thickness adjacent to bottom of gate electrode 110b and tapers along inclined side 210 to a pointed end as the lateral distance from gate electrode 110b increases).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the outer sidewall of Wang’s via spacer 290’ according to Huang’s known triangular spacer profile because Huang teaches that the triangular geometry improves filling of subsequently deposited insulating material and reduces void formation and associated leakage.
Claim(s) 11, 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20210376071 A1) in view of Wang (US 20210343639 A1) further in view of Chen (US 20220069116 A1).
Re: Claim 11, Liu and Wang disclose all the limitations of claim 1 on which this claim depends.
Liu further teaches
further comprising a gate dielectric film located between the plurality of source/drain regions and the plurality of gate lines (Liu teaches, in Fig. 19B, gate dielectric layer 349 of gate stacks 240’, disposed between the gate electrode 350 and semiconductor source-drain regions 260).
Both Liu and Wang are silent regarding
wherein the gate protective film covers a portion of the gate dielectric film, which is adjacent to the backside contact.
However, Chen teaches
wherein the gate protective film covers a portion of the gate dielectric film, which is adjacent to the backside contact (Chen teaches, in Fig. 22C, spacer liner 76 formed over gate dielectric layer 56 and backside source/drain contact 84 is formed. Thus, spacer liner 76 covers a portion of gate dielectric layer 56 adjacent to the backside contact region 84).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to extend Wang’s protective spacer 290’ over the adjacent gate dielectric as taught by Chen because Chen teaches using spacer liner 76 to provide dielectric protection during subsequent etching and processing, thereby maintaining dielectric isolation in the backside-contact region.
Re: Independent Claim 13, Liu discloses an integrated circuit device comprising:
a plurality of device isolation films extending lengthwise in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction (Liu teaches, in Figs. 23A-23E and also ¶ [0019], isolation features 230. Liu teaches fins 218 extending lengthwise in the X direction and isolation features 230, such as STI structures, formed by filling trenches between the fins with insulating material. Accordingly, the isolation features 230 formed in the trenches between the X-directed fins likewise extend along the X-direction and are laterally spaced from one another in the intersecting Y direction. Liu expressly teaches isolation features 230 isolate fins from each other);
a gap-fill insulating film located between the plurality of device isolation films (Liu teaches, in Fig. 24C and ¶ [0049], dielectric liner 274 and dielectric layer 276 filling backside trenches between retained isolation features 230);
a plurality of gate lines disposed above the gap-fill insulating film and extending lengthwise in the second horizontal direction (Liu, Fig. 23A-23E and ¶ [0048], forms gate stacks 240’ (including gate electrode 350) at the front side of the device and subsequently, from the backside, removes semiconductor layer 204 to form trenches 272 and fills trenches 272 with dielectric liner 274 and dielectric layer 276. Because Liu defines the Z direction as extending from the backside toward the frontside (¶ [0046]), gate stacks 240’ are disposed above the backside dielectric 274/276 in the final device structure);
a plurality of source/drain regions comprising a first source/drain region and a second source/drain region, each of the plurality of source/drain regions located between the plurality of gate lines (Liu teaches, in Fig. 17B-19B, and ¶ [0035], source/drain regions 260. Liu, in ¶ [0029], identifies one source/drain region and another source/drain region of the transistor and forms respective epitaxial S/D features 260 therein. The S/D features 260 are formed in the regions between adjacent gate stacks 240/240’. A selected S/D feature 260 adjoining to semiconductor layer 239 corresponds to the claimed first source/drain region, while another S/D feature 260 corresponds to the claimed second source/drain region);
a gate dielectric film located between the plurality of source/drain regions and the plurality of gate lines (Liu teaches, in Fig. 19B, gate dielectric layer 349 of gate stacks 240’, disposed between the gate electrode 350 and semiconductor source-drain regions 260).
Liu is silent regarding
a gate protective film covering a portion of a lower surface of the gate dielectric film adjacent to the first source/drain region;
a gap-fill gate protective film covering a portion of a lower surface of the gate dielectric film adjacent to the second source/drain region; and
wherein the gate protective film and the gap-fill gate protective film are arranged between the gap-fill insulating film and the plurality of source/drain regions.
However, Chen teaches
a gate protective film covering a portion of a lower surface of the gate dielectric film adjacent to the first source/drain region (Chen teaches, in Fig. 20C, spacer liner 76 formed over gate dielectric layer 56 adjacent to first source/drain features 50s);
a gap-fill gate protective film covering a portion of a lower surface of the gate dielectric film adjacent to the second source/drain region (Chen teaches, in Fig. 20A-20C, dielectric feature 77, comprising spacer liner 76 and refill dielectric layer 78, adjacent to second source/drain feature 50d and covering a portion of gate dielectric layer 56. Dielectric feature 77 extends from isolation layer 22 into the source/drain region and contacts second source/drain features 50d, thereby teaching the protective dielectric region and the source/drain region);
wherein the gate protective film and the gap-fill gate protective film are arranged between the gap-fill insulating film and the plurality of source/drain regions (Chen, spacer liner 76 is formed over isolation layer 22 and along the backside contact region adjacent source/drain feature 50s, while dielectric feature 77 includes a first portion in isolation layer 22 and a second portion extending from isolation layer 22 into the source drain space and contacting source/drain feature 50d. Thus, Chen teaches protective dielectric structures 77 interposed between the backside isolation/dielectric region 22 and the respective source/drain regions. When Chen’s protective dielectric arrangement is incorporated into Liu’s device, spacer liner 76 and dielectric feature 77 would likewise be positioned between Liu’s backside gap-fill insulating film 274/276 and corresponding source/drain features 260).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Liu’s device with Chen’s protective liner and gap-fill dielectric structures because Chen teaches that the additional dielectric material increases dielectric separation between the gate and source/drain region, thereby reducing undesired gate to source drain capacitive coupling.
Liu is further is silent regarding
a backside contact being in contact with the gate protective film and electrically connected to the first source/drain region.
However, Wang teaches
a backside contact being in contact with the gate protective film and electrically connected to the first source/drain region (Wang teaches, in Fig. 30A and ¶¶ [0108] – [0110], via spacer 290’, corresponding to the gate protective film, lining the sidewall of backside-via opening O5’ and contacting the backside of source epitaxial structure 190S. Epitaxial regrowth layer 280’ is formed within spacer 290’, and backside via 300 fills the remainder of the opening. Thus, backside via 300 is in contact with spacer 290’ among its sidewall and is electrically connected through the backside contact structure to source epitaxial structure 190S).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to employ Wang’s protective spacer/backside contact arrangement in the Liu-Chen device because Wang teaches that the via spacer confines and protects the backside contact region during fabrication, thereby maintaining the desired backside-contact geometry.
Re: Claim 14, Liu, Chen and Wang disclose all the limitations of claim 13 on which this claim depends.
Liu further teaches
wherein each of the gap-fill gate protective film comprises SiGe, SiGeC, SiO, SiC, SiOC, SiOCN, SiOH, GeC or a combination thereof Liu teaches, in ¶ [0049], dielectric liner 274 comprise silicon nitride and dielectric layer 276 comprise silicon oxide).
Wang further teaches
wherein each of the gate protective film comprises SiGe, SiGeC, SiO, SiC, SiOC, SiOCN, SiOH, GeC or a combination thereof (Wang teaches, in ¶¶ [0088] and [0108], claimed gate protective film 290/290’ includes silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof).
Re: Claim 15, Liu, Chen and Wang disclose all the limitations of claim 13 on which this claim depends.
Wang further teaches
wherein the gate protective film at least partially covers a lower surface of the first source/drain region (Wang teaches, in Fig. 30A, that via spacer 290’ (corresponds to the claimed gate protective film) contacts the backside of source epitaxial structure 190S. Thus, spacer 290’ covers a peripheral portion of the lower surface of 190S).
Chen further teaches
the gap-fill gate protective film completely covers a lower surface of the second source/drain region (Chen teaches, in Fig. 20A-20C, dielectric feature 77, comprising spacer liner 76 and refill dielectric layer 78, adjacent to second source/drain feature 50d and covering a portion of gate dielectric layer 56. Chen teaches, in ¶ [0104], after exposing/recessing the backside surface 50p of second source/drain features 50d, spacer liner 76 is conformally formed over the exposed source/drain feature 50d and refill dielectric layer 78 is deposited thereover to fill the remaining cavity. Thus, dielectric feature 77 extends across and covers the exposed backside/lower surface of source/drain feature 50d).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the protective dielectric structures of the Liu-Chen-Wang device according to the respective coverage arrangements taught by Wang and Chen because such arrangements provide dielectric isolation and protection at the backside source/drain regions while permitting electrical contact to the selected first source/drain region.
Re: Claim 16, Liu, Chen and Wang disclose all the limitations of claim 13 on which this claim depends.
Chen further teaches
wherein a sidewall of the gate protective film is surrounded by the gap-fill insulating film (Chen teaches, in Fig. 22A, spacer liner 76 formed along sidewalls 44s of backside-contact alignment feature 44 within isolation layer 22, such that an outward-facing sidewall of spacer liner 76 is surrounded by isolation dielectric 22).
Chen further teaches
wherein a sidewall and a lower surface of the gap-fill gate protective film are surrounded by the gap-fill insulating film (Chen teaches, in Fig. 22A, dielectric feature 77 includes a portion 77u formed within isolation layer 22, such that the sidewall and lower surface of the embedded portion of dielectric feature 77 are surrounded by isolation layer 22), and
the gap-fill insulating film comprises a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (Chen teaches, in ¶ [0023], isolation layer 22 comprise silicon oxide, silicon nitride or silicon oxynitride).
Conclusion
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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