DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 15, 19, and 20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In re claim 3, “a connecting plug” is not described with in the specification. The specification of the instant application describes a connection plug (CA) and this is interpreted as the connecting plug per the limitations of claim 3
In re claim 15, the limitations of “a plurality of air gaps are arranged between the plurality of first connectors”, “a plurality of first connectors”, “a plurality of second connectors”, and “a dielectric coating, different from the first dielectric layer, conformally formed on exposed surfaces of the plurality of first connectors and laterally surrounding the first dielectric layer” are not described in the specification. The plurality of air gaps between a plurality of first connectors is not described within the specification. The plurality of first and second connectors are interpreted as connectors 262 and 264 as mentioned in the specification. The dielectric coating and it being different from the first dielectric layer is not described within the specification.
In re claims 19 and 20, as stated above for claim 15 air gaps between first connectors that allow for liquid coolant flow passage and being defied by a dielectric coating are not described within the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Leobandung (US Publication 20220317177).
Regarding claim 1, Brunschwiler teaches a semiconductor package, comprising:
a first die having a front side region and a backside (Fig. 1, bottom die of chip stack 106 with front / back sides top / bottom respectively)
a substrate carrying the first die with the substrate comprising a first cavity allowing a liquid to pass through (Fig. 1, substrate 112, para 29, first cavity 113);
a cold plate over the first die with the cold plate comprising a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first cavity and the second cavity (Fig. 1, cold plate 114, second cavity 115 connected to first cavity 113 fluid flow denoted by arrows)
Brunschwiler does not specifically teach:
wherein the front side region comprises an active region in which a transistor is located and a STI region next to the active region ; and an underground interconnection (UGI) disposed in the STI region of the front side region of the first die.
Leobandung teaches:
wherein the front side region comprises an active region in which a transistor is located and a STI region next to the active region (Fig. 35, transistor 604 in front side region and STI region 620 next to active region) and;
an underground interconnection (UGI) disposed in the STI region of the front side region of the first die (Fig. 35, UGI 502).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a transistor, STI region, active region, and an underground connection as taught by Leobandung in order to improve the operability and reliability of the device.
Regarding claims 2-4, Brunschwiler as modified teaches the limitations of claim 1 upon which claims 2-4 depend.
Brunschwiler does not specifically teach:
[claim 2] wherein the underground interconnection is disposed adjacent to the transistor, and a sidewall of the underground interconnection is isolated from the transistor by a spacer.
[claim 3] wherein a sidewall of the underground interconnection is connected to a connecting plug disposed in the active region, and the connecting plug is connected to the transistor.
[claim 4] wherein a connecting via is connected to a bottom surface of the underground interconnection.
Leobandung teaches:
[claim 2] wherein the underground interconnection is disposed adjacent to the transistor, and a sidewall of the underground interconnection is isolated from the transistor by a spacer (Fig. 35, UGI 502 adjacent to and isolated from transistor 604 by spacer 3402).
[claim 3] wherein a sidewall of the underground interconnection is connected to a connecting plug disposed in the active region, and the connecting plug is connected to the transistor (Fig. 24A/B, connecting plug 2402 in active region 2002 connected to UGI 502).
[claim 4] wherein a connecting via is connected to a bottom surface of the underground interconnection (Fig. 38A, 3708 connected to UGI 502 on bottom when rotated180 degrees).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a transistor, STI region, active region, underground connection, and associated vias and connectors as taught by Leobandung in order to improve the operability and reliability of the device.
Regarding claim 5, Brunschwiler as modified teaches the limitations of claim 1 upon which claim 5 depends.
Brunschwiler teaches wherein the substrate further comprises:
an upper portion defining a first part of the first cavity (Fig. 1, upper portion of 112 closest to 106 defining top portion of cavity 113);
a lower portion defining a second part of the first cavity (Fig. 1, lower portion of 112 closest to 102 defining lower portion of cavity 113); and
a bonding structure connecting the upper portion and the lower portion of the substrate (Fig. 1, solid black line through 112, para 29 "bonding two silicon halves"),
wherein the first part and the second part of the first cavity combined is configured to form a fluidic channel allowing the liquid to pass through (para 29).
Regarding claim 7, Brunschwiler as modified teaches the limitations of claim 1 upon which claim 6 depends.
Brunschwiler teaches wherein the substrate further comprises:
a first interconnect layer facing toward the first die (Fig. 1, 106 facing side of 112 with vias 108, para 32);
a second interconnect layer facing away from the first die (Fig. 1, 102 facing side of 112 with vias 108, para 32);
a through via electrically, optically, or thermally coupling the first interconnect layer and the second interconnect layer (Fig. 1, via 108); and
an isolation structure proximal to the first sealing structure and the second sealing structure, configured to isolate the through via from the first sealing structure and the second sealing structure (Fig. 2, vias 108 in 112 channel area 113).
Claims 8-11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Leobandung (US Publication 20220317177) and Bothe et al (US Publication 20240429122).
Regarding claim 8, Brunschwiler teaches a semiconductor package, comprising:
a first die having a front side region and a backside (Fig. 1, bottom die of chip stack 106 with front / back sides top / bottom respectively),
a first supporter disposed immediately under the first die and thermally coupled to the first die (Fig. 8, 212 below 206, para 44);
Brunschwiler does not teach:
wherein the front side region comprises an active region in which a transistor is located and a STI region next to the active region;
an underground interconnection disposed in the STI region of the front side region of the first die (Fig. 35, UGI 502);
wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die.
Leobandung teaches:
wherein the front side region comprises an active region in which a transistor is located and a STI region next to the active region (Fig. 35, transistor 604 in front side region and STI region 620 next to active region);
an underground interconnection disposed in the STI region of the front side region of the first die (Fig. 35, UGI 502);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a transistor, STI region, active region, and an underground connection as taught by Leobandung in order to improve the operability and reliability of the device.
Brunschwiler as modified still lacks wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die.
Bothe teaches wherein a thermal conductivity of the first supporter is greater than a thermal conductivity of the first die (para 35 and 65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a first supporter with a higher thermal conductivity than that of the first die as taught by Bothe in order to improve the thermal properties of the device.
Regarding claims 9-11, Brunschwiler as modified teaches the limitations of claim 8 upon which claim 9-11 depend.
Brunschwiler does not specifically teach:
[claim 9] wherein the underground interconnection is disposed adjacent to the transistor, and a sidewall of the underground interconnection is isolated from the transistor by a spacer.
[claim 10] wherein a sidewall of the underground interconnection is connected to a connecting plug disposed in the active region, and the connecting plug is connected to the transistor.
[claim 11] wherein a connecting via is connected to a bottom surface of the underground interconnection.
Leobandung teaches:
[claim 9] wherein the underground interconnection is disposed adjacent to the transistor, and a sidewall of the underground interconnection is isolated from the transistor by a spacer (Fig. 35, UGI 502 adjacent to and isolated from transistor 604 by spacer 3402).
[claim 10] wherein a sidewall of the underground interconnection is connected to a connecting plug disposed in the active region, and the connecting plug is connected to the transistor (Fig. 24A/B, connecting plug 2402 in active region 2002 connected to UGI 502).
[claim 11] wherein a connecting via is connected to a bottom surface of the underground interconnection (Fig. 38A, 3708 connected to UGI 502 on bottom when rotated180 degrees).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a transistor, STI region, active region, underground connection, and associated vias and connectors as taught by Leobandung in order to improve the operability and reliability of the device.
Regarding claim 14, Brunschwiler as modified teaches the limitations of claim 8 upon which claim 14 depends.
Brunschwiler does not teach wherein the first supporter is composed of diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, or silicon carbide.
Bothe teaches wherein the first supporter is composed of diamond, graphene, boron nitride, boron arsenide, cubic boron arsenide, aluminum nitride, or silicon carbide (para 35 and 65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a first supporter as taught by Bothe in order to improve the thermal properties of the device.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Leobandung (US Publication 20220317177) and Bothe et al (US Publication 20240429122) and further in view of Chainer (US Publication 20170186728).
Regarding claim 12, Brunschwiler as modified teaches the limitations of claim 8 upon which claim 12 depends.
Brunschwiler does not teach wherein the first supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon, and with the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die.
Bothe teaches wherein the first supporter comprises an interposer composed of a material with a thermal conductivity greater than that of silicon (para 35 and 65)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the interposer with thermal conductivity greater than silicon as taught by Bothe in order to improve the thermal management properties of the device.
Brunschwiler as modified still lacks the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die.
Chainer teaches the interposer having a cross sectional width greater than or substantially identical to a cross sectional width of the first die (para 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the interposer width as taught by Chainer in order to improve the thermal and mechanical robustness of the device.
Regarding claim 13¸Brunschwiler as modified teaches the limitations of claim 8 upon which claim 13 depends.
Brunschwiler lacks wherein the first supporter and the first die combined form a composite layer with at least one via passing through the first die and the first supporter.
Chainer teaches wherein the first supporter and the first die combined form a composite layer with at least one via passing through the first die and the first supporter (Fig. 10, 1000, para 57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include the supporter and die composite layer with at least one via as taught by Chainer in order to improve the thermal and mechanical robustness of the device.
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Brunschwiler et al (US Publication 20170179001) in view of Leobandung (US Publication 20220317177), Chainer (US Publication 20170186728), and Lai et al (US Publication 20230107847).
Regarding claim 15, Brunschwiler teaches a semiconductor package, comprising:
a first semiconductor die disposed over a first substrate (Fig. 1, first die in die stack 106 disposed over first substrate 102);
a plurality of second semiconductor dies disposed over the first semiconductor die or adjacent to the first semiconductor die (Fig. 1, plurality of dies above first die in die stack 106);
a plurality of first connectors arranged between and electrically connecting the first semiconductor die and the first substrate (Fig. 1, connectors 101 connecting first die in die stack 106 to first substrate 102);
a plurality of second connectors arranged between and electrically connecting two of the second semiconductor dies (Fig. 1, connectors 118 between and electrically connecting dies in die stack 106);
wherein a plurality of air gaps are arranged between the plurality of first connectors (Fig. 1, gaps between 101s);
Brunschwiler does not teach:
a first dielectric layer encapsulating the plurality of second connectors,
a dielectric coating, different from the first dielectric layer, conformally formed on exposed surfaces of the plurality of first connectors and laterally surrounding the first dielectric layer;
an underground interconnection;
wherein one of the first semiconductor die and the second semiconductor die comprises a front side region comprising an active region in which a transistor is located and a STI region next to the active region, the underground interconnection is disposed in the STI region of the front side region of the first die.
Leobandung teaches:
an underground interconnection (Fig. 35, UGI 502);
wherein one of the first semiconductor die and the second semiconductor die comprises a front side region comprising an active region in which a transistor is located and a STI region next to the active region, the underground interconnection is disposed in the STI region of the front side region of the first die (Fig. 35, transistor 604 in front side region and STI region 620 next to active region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a transistor, STI region, active region, and an underground connection as taught by Leobandung in order to improve the operability and reliability of the device.
Brunschwiler as modified still lacks a first dielectric layer encapsulating the plurality of second connectors.
Lai teaches a first dielectric layer encapsulating the plurality of second connectors (Fig. 9, 90, para 95);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include a dielectric layer as taught by Chainer in order to improve the operability and reliability of the device.
Brunschwiler as modified still lacks a dielectric coating, different from the first dielectric layer, conformally formed on exposed surfaces of the plurality of first connectors and laterally surrounding the first dielectric layer.
Chainer teaches a dielectric coating, different from the first dielectric layer, conformally formed on exposed surfaces of the plurality of first connectors and laterally surrounding the first dielectric layer (Fig. 13, 1307, para 63-66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler as modified to include a dielectric coasting as taught by Chainer in order to improve the operability and reliability of the device.
Regarding claims 16-18, Brunschwiler as modified teaches the limitations of claim 15 upon which claims 16-18 depend.
Brunschwiler does not teach:
[claim 16] wherein the underground interconnection is disposed adjacent to the transistor, and a sidewall of the underground interconnection is isolated from the transistor by a spacer.
[claim 17] wherein a sidewall of the underground interconnection is connected to a connecting plug disposed in the active region, and the connecting plug is connected to the transistor.
[claim 18] wherein a connecting via is connected to a bottom surface of the underground interconnection.
Leobandung teaches:
[claim 16] wherein the underground interconnection is disposed adjacent to the transistor, and a sidewall of the underground interconnection is isolated from the transistor by a spacer (Fig. 35, UGI 502 adjacent to and isolated from transistor 604 by spacer 3402).
[claim 17] wherein a sidewall of the underground interconnection is connected to a connecting plug disposed in the active region, and the connecting plug is connected to the transistor (Fig. 24A/B, connecting plug 2402 in active region 2002 connected to UGI 502).
[claim 18] wherein a connecting via is connected to a bottom surface of the underground interconnection (Fig. 38A, 3708 connected to UGI 502 on bottom when rotated180 degrees).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Brunschwiler to include a transistor, STI region, active region, underground connection, and associated vias and connectors as taught by Leobandung in order to improve the operability and reliability of the device.
Regarding claim 19, Brunschwiler as modified discloses wherein the air gaps are configured to allow passage of liquid coolant under an immersion cooling operation (the gaps that are present would allow liquid to pass through, thus read on the ‘configured to’ language here).
Allowable Subject Matter
Claim 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Further, claim 20 is not rejected under prior art, as the combination of claim 20 with claim would likely be allowable once the 112a rejection above was overcome (or explained as to where the support is found and clarified).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ecton (US Publication 20250087587) – Embedded organic bridge component for semiconductor packages.
Duan et al (US Publication 20240030147) – Multi-die panel-level high performance computing components.
Song et al (US Patent 11984421) – Integrated circuit chip having BS-PDN structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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