DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 06/10/2026 Response to Election/Restriction.
Claims 1-12, 19-24 are pending and examined. Claims 19-24 are newly added. Claims 13-18 have been cancelled.
Claim Rejections - 35 USC § 112
Claims 11, 20, 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 recites limitations “sources current to the second ground node in response to the second state of the first control signal and deassertion of the dummy word line” on lines 4-6. Examiner is not able to find support for this limitation in the disclosure. From FIG. 4A, when the read dummy word line DWLR is deasserted, transistor N3 turns off and transistor N4 maintains on with VDDMA voltage supply. There appears no current flowing to the second ground node GND2T and dummy bit line DBLR is not discharged as shown in FIG. 4C.
Claim 20 recites limitations “during the second state of the first control signal and when the dummy word line is deasserted, sourcing current to the second ground node” on lines 1-3. Same rejection is applied as in claim 20.
Claim 22 recites limitations “wherein the ground generation circuitry is configured, in the second state of the first control signal and when a dummy read word line is at a logic low, to source current to the second ground node” on lines 1-3. Same rejection is applied as in claim 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 10, 23-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,240,228 to Chen et al. (hereafter Chen).
Regarding independent claim 1, Chen teaches a memory system, comprising:
a memory array (FIG. 2: memory array 210);
a first plurality of dummy read cells configured to discharge a dummy bit line (FIG. 2: dummy ends of dummy memory cells, which are NOT coupled to the discharge current adjuster 240, see dummy cell 22N for example, see 3:15-29), each dummy read cell of the first plurality of dummy read cells including a respective transistor coupled between the dummy bit line and a first ground node (FIG. 7B: a dummy memory cell 720 comprising transistors MN5-MN6 coupled between ground node CDT1 and dummy bit line DBL as an example of dummy read cell), wherein the first ground node is connected to a ground reference (FIG. 2: dummy memory cell 22N coupled to first ground node CDTN and then to GND);
a second plurality of dummy read cells configured to discharge the dummy bit line (FIG. 2: dummy ends of dummy memory cells, which are coupled to the discharge current adjuster 240, see dummy cells 221-222, see 3:15-29), each dummy read cell of the second plurality of dummy read cells including a respective transistor coupled between the dummy bit line and a second ground node (FIG. 7B: dummy memory cell 720 comprising transistors MN5-MN6 coupled between ground node CDT1 and dummy bit line DBL as an example of dummy read cell; FIG. 2 shows dummy memory cell 221-222 coupled to second ground node CDT1/CDT2);
wherein the first plurality of dummy read cells and the second plurality of dummy read cells cooperate to discharge the dummy bit line in a dummy read operation to provide a self-timing signal (see FIG. 2 and 2:65-3:13);
read circuitry configured to retrieve data from a selected row in the memory array during a read operation in response to the self-timing signal (FIG. 2: sense amplifier 230); and
ground generation circuitry configured to connect the second ground node to the ground reference in response to a first state of a control signal (FIGS. 2: discharge current adjuster 240 coupled CDT1/CDT2 to GND; FIG. 4 shows discharge current adjuster 240 is in operation in response to active state of signal BEN of FIG. 4, see 4:63-5:6) and to allow the second ground node to float in response to a second state of the control signal (FIG. 4 shows discharge current adjuster 240 is in no operation, i.e. floating, in response to inactive state of signal BEN of FIG. 4, see 4:63-5:6).
Regarding dependent claim 4, Chen teaches wherein the ground generation circuitry comprises: a first n-channel transistor having a drain connected to the second ground node, a source connected to the ground reference, and a gate connected to the control signal (FIG. 3B: transistor M1 connected to CDT1 and GND, gate received signal BEN); and a second n-channel transistor having a drain connected to the second ground node, a source connected to the ground reference, and a gate connected to a dummy read word line (FIG. 7B: transistor MN5 having source/drain coupled to CDT1 and gate receiving DWLA1 as in FIG. 7B, and drain/source coupled to GND via DBL and discharge current adjuster 240 as in FIG. 2).
Regarding independent claim 10, Chen teaches a method of reading a memory array, the method comprising:
inherently decoding an address and asserting a corresponding word line based thereupon (because decoding a row address for selection of a word line is essential step in storage memory operation);
inherently performing a dummy decode to assert a dummy word line (FIG. 2: in order to activate one of word line signals DWL[1:N] for dummy word line selection);
discharging a dummy bit line in response to the assertion of the dummy word line (FIG. 7A: discharge dummy bit line DBL in response to assertion of dummy word line DWLA1); and
in response to the discharging of the dummy bit line, activating input/output circuitry to read a row in the memory array corresponding to the asserted word line (FIG. 2: sense amplifier 230, see 2:65-3:13);
wherein discharging the dummy bit line comprises:
discharging the dummy bit line using a first plurality of dummy read cells each utilizing a respective transistor coupled between the dummy bit line (FIG. 2: dummy ends of dummy memory cells, which are NOT coupled to the discharge current adjuster 240, see dummy cell 22N for example, see 3:15-29) and a first ground node connected to a ground reference (FIG. 2: dummy memory cell 22N coupled to first ground node CDTN and then to GND);
activating ground generation circuitry based on a first control signal to connect a second ground node to the ground reference in response to a first state of the first control signal (FIGS. 2: discharge current adjuster 240 coupled CDT1/CDT2 to GND; FIG. 4 shows discharge current adjuster 240 is in operation in response to active state of signal BEN of FIG. 4, see 4:63-5:6) and allow the second ground node to float in response to a second state of the first control signal (FIG. 4 shows discharge current adjuster 240 is in no operation, i.e. floating, in response to inactive state of signal BEN of FIG. 4, see 4:63-5:6); and
further discharging the dummy bit line using a second plurality of dummy read cells each utilizing a respective transistor coupled between the dummy bit line and the second ground node (FIG. 2: discharge current adjuster further discharges DBL); and
connecting the second ground node to the ground reference in response to a first state of the first control signal (FIGS. 2: discharge current adjuster 240 coupled CDT1/CDT2 to GND; FIG. 4 shows discharge current adjuster 240 is in operation in response to active state of signal BEN of FIG. 4, see 4:63-5:6) and controlling the second ground node to float in response to a second state of the first control signal (FIG. 4 shows discharge current adjuster 240 is in no operation, i.e. floating, in response to inactive state of signal BEN of FIG. 4, see 4:63-5:6).
Regarding dependent claim 23, Chen teaches wherein the first plurality of dummy read cells includes a first subset of dummy read cells connected to a first ground trace (FIG. 2: ground trace coupled to CDTN) and the second plurality of dummy read cells includes a second subset of dummy read cells connected to a second ground trace that is different from the first ground trace (FIG. 2: ground trace coupled to CDT1/CDT2).
Regarding dependent claim 24, Chen teaches wherein the second ground node is configured to be selectively connected to ground (FIGS. 2: discharge current adjuster 240 coupled CDT1/CDT2 to GND; FIG. 4 shows discharge current adjuster 240 is in operation in response to active state of signal BEN of FIG. 4, see 4:63-5:6) or allowed to float by the ground generation circuitry based on the first control signal (FIG. 4 shows discharge current adjuster 240 is in no operation, i.e. floating, in response to inactive state of signal BEN of FIG. 4, see 4:63-5:6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding dependent claim 5, it includes limitations similar to those of claim 4, except for the features related to the P-type transistor.
It would have been obvious to a person of ordinary skill in the art that N-type and P-type transistors are complementary and interchangeable.
Claims 2-3, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 9,786,359 to Liaw (hereafter Liaw).
Chen teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 2, Liaw teaches a memory array (see FIG. 4A), first plurality of dummy read cells and second plurality of dummy read cells coupled to a dummy bit line (FIG. 4A: first SRAM tracking cells 50A and second SRAM tracking cells 50B coupled to tracking BL 210); wherein the memory array is comprised of rows of SRAM cells, each SRAM cell having a dual-port design such that it is read through a read port connected to a read bit line (FIG. 1: SRAM cell 10 is read through an inherent read port connected to RBL 150); wherein the dummy bit line is a dummy read bit line (FIG. 5A: BL 210 is dummy read bit line); wherein each dummy read cell of the first plurality of dummy read cells has a dual-port design such that it is read through a read port connected to the dummy read bit line (FIG. 5A: first SRAM tracking cells 50A is read through read port coupled to tracking BL 210); wherein each dummy read cell of the second plurality of dummy read cells has a dual-port design such that it is read through a read port connected to the dummy read bit line (FIG. 5B: second SRAM tracking cells 50B is read through read port coupled to tracking BL 210); and wherein the read port of each dummy read cell of the second plurality of dummy read cells includes the respective transistor of that dummy read cell (transistor 58 of FIG. 5A and transistor 58 of FIG. 5B).
Since Chen and Liaw are both from the same field of endeavor, the purpose disclosed by Chen would have been recognized in the pertinent art of Liaw.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply method of discharging dummy read bit line suggested in Chen for the dual-port SRAM device of Liaw for the purpose of reducing data reading errors in a low operating voltage (see Chen, 1:33-57).
Regarding dependent claim 3, Liaw teaches wherein the read port of each dummy read cell of the second plurality of dummy read cells comprises: a first n-channel transistor having a drain connected to the dummy read bit line, a source, and a gate connected to a dummy read word line (FIG. 5A: transistor 56); and a second n-channel transistor having a drain connected to the source of the first n- channel transistor, a source connected to the second ground node, and a gate connected to a supply voltage (FIG. 5A: transistor 58); and further comprising a dummy decoder configured to assert the dummy read word line to beginning begin the dummy read operation (FIG. 5A: Iread tracking control circuit 60).
Regarding dependent claim 6, Liaw teaches wherein the dummy bit line is a dummy read bit line (FIG. 5A: tracking BL); wherein the first plurality of dummy read cells and the second plurality of dummy read cells are organized into a dummy read column, with the dummy read bit line running through the dummy read column (FIG. 4A: see column comprising dummy memory cells 50A and 50B); and a plurality of load cells connected to the dummy read bit line to match a capacitance on the dummy read bit line to a capacitance on a bit line of the memory array (see 6:38-53).
Claims 7-9, 12, 19, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 9,858,217 to Marfatia et al. (hereafter Marfatia).
Chen teaches, as applied in prior rejection of claims 1 and 10, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 7, Marfatia teaches plurality of memory arrays (FIG. 4: each memory array coupled to one of the multiplexer 408), each memory array comprises a plurality of dummy read cells coupled to a dummy bit line (see FIG. 4 and 5(B)).
Since Chen and Marfatia are both from the same field of endeavor, the purpose disclosed by Chen would have been recognized in the pertinent art of Marfatia.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art:
to apply method of discharging dummy read bit line suggested in Chen for each of the memory array of Marfatia for the purpose of reducing data reading errors in a low operating voltage (see Chen, 1:33-57);
to realize that if the memory system comprising more than one memory array as taught in Marfatia, the second memory array would comprise third plurality of dummy read cells, fourth plurality of dummy read cells, a second ground generation circuitry similar to those of the memory array of Chen.
Regarding dependent claim 8, Chen teaches wherein the ground generation circuitry comprises: a first n-channel transistor having a drain connected to the second ground node, a source connected to the ground reference, and a gate connected to the control signal (FIG. 3B: transistor M1 connected to CDT1 and GND, gate received signal BEN); and a second n-channel transistor having a drain connected to the second ground node, a source connected to the ground reference, and a gate connected to a dummy read word line (FIG. 7B: transistor MN5 having source/drain coupled to CDT1 and gate receiving DWLA1 as in FIG. 7B, and drain/source coupled to GND via DBL and discharge current adjuster 240 as in FIG. 2).
Regarding dependent claim 9, it includes limitations similar to those of claim 8, except for the features related to the P-type transistor.
It would have been obvious to a person of ordinary skill in the art that N-type and P-type transistors are complementary and interchangeable.
Regarding dependent claim 12, it encompasses the same scope of invention as to that of claim 7 except it drafts in method format instead of apparatus format. The claim is therefore rejected for the same reason as set forth above.
Regarding dependent claim 19, Chen teaches wherein activating the ground generation circuitry includes controlling, based on the first control signal, whether the second ground node is connected to ground or allowed to float (FIGS. 3B and 7BL: e.g. signal BEN is independent from signal DWLA1. It is seen that the dummy memory cell of FIG. 7B and discharge current adjuster 240 are connected in series between DBL-CDT1-GND).
Regarding dependent claim 21, Marfatia teaches a second memory array comprising an additional ground generation circuitry.
Chen teaches wherein activating a ground generation circuitry includes controlling, based on a control signal, whether a ground node is connected to ground or allowed to float (FIGS. 3B and 7BL: e.g. signal BEN is independent from signal DWLA1. It is seen that the dummy memory cell of FIG. 7B and discharge current adjuster 240 are connected in series between DBL-CDT1-GND).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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August 14, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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