DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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2. Claims 1-2 & 4-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-20, respectively, of U.S. Patent No. 12,094,541 (same assignee/inventor).
Although the claims at issue are not identical, they are not patentably distinct from each other because the following comparisons:
Claim 1 (this application) obviously read on the subject matter of claim 14 (patent ‘541) because both claims recite similar claimed structure with similar component layouts such as, for example, a non-volatile memory having x-th word lines, y-th word lines, m-bit data being stored in memory cells, x-th and y-th internal processing’s, etc. Additionally, both claims also contain identical operation steps such as, for example, counting first/second number of first/second combinations of data, calculating polarity of the shift amount of ration, determining magnitude of an absolute value of the shift amount, and determining the read voltage based on such calculated shift amount of the read voltage, etc. Additionally, the claimed ”threshold voltage regions” of claim 1 (application) have the same meaning as the claimed “threshold voltage distributions”, which is considered well-known to a skilled person in this art as well.
Claim 2 (application) contains similar language as claim 15 (patent ‘541).
Claim 4 (application) contains identical language as claim 16 (patent ‘541).
Claim 5 (application) contains identical language as claim 17 (patent ‘541).
Claim 6 (application) contains identical language as claim 18 (patent ‘541).
Claim 7 (application) contains similar language as claim 19 (patent ‘541).
Claim 8 (application) contains identical language as claim 20 (patent ‘541).
3. Claims 1-2 & 4-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-20, respectively, of U.S. Patent No. 11,195,585 (same assignee/inventor).
Although the claims at issue are not identical, they are not patentably distinct from each other because the following comparisons:
Claim 1 (this application) obviously read on the subject matter of claim 14 (patent ‘585) because both claims recite similar claimed structure with similar component layouts such as, for example, a non-volatile memory having x-th word lines, y-th word lines, m-bit data being stored in memory cells, x-th and y-th internal processing’s, etc. Additionally, both claims also contain identical operation steps such as, for example, counting first/second number of first/second combinations of data, calculating polarity of the shift amount of ration, determining magnitude of an absolute value of the shift amount, and determining the read voltage based on such calculated shift amount of the read voltage, etc. Additionally, the claimed ”threshold voltage regions” of claim 1 (application) have the same meaning as the claimed “threshold voltage distributions”, which is considered well-known knowledge to a skilled person in this art as well.
Claim 2 (application) contains similar language as claim 15 (patent ‘585).
Claim 4 (application) contains identical language as claim 16 (patent ‘585).
Claim 5 (application) contains identical language as claim 17 (patent ‘585).
Claim 6 (application) contains identical language as claim 18 (patent ‘585).
Claim 7 (application) contains similar language as claim 19 (patent ‘585).
Claim 8 (application) contains identical language as claim 20 (patent ‘585).
Allowable Subject Matter
4. The following claims are objected as being dependent upon the rejected claim 1 above, but tentatively contain following novel limitations over the prior arts as follows:
Claim 3 recite the novel step of calculating a number of fail bits using the read first data set and the second data set, and not to perform the second processing when the calculated number of fail bits is smaller than a certain value.
Claims 9-10 recite that each memory group corresponds to m pages, and wherein the read voltage is applied to the y-th word line to read the data from the y-th memory group.
Claims 11-12 recite that the memory controller includes an SRAM as buffer memory, and the y-th internal processing includes storing the read first data set in the buffer memory, and storing the generated second data set in the buffer memory, the first number is counted using the first data set in the buffer memory and the second data set in the buffer memory, and the second number is counted using the first data set in the buffer memory and the second data set in the buffer memory.
Claims 13-14 recite that the reading data from the y-th memory group as the first data set includes: reading a third data set from the y-th memory group by using a first voltage and a second voltage; reading a first single state data set from the y-th memory group by using a third voltage between the first voltage and the second voltage; and extracting, from the third data set, bits corresponding to a first value of the first single state data set as the first data set, and that reading data from the y-th memory group as the first data set further includes steps of generating a first expected data set by an error correction on the third data set; and extracting, from the first expected data set, bits corresponding to the first value of the first single state data set as the second data set.
Claims 15-16 recite the steps of reading data from the y-th memory group as the first data set further includes: storing the third data set in the buffer memory storing the first single state data set in the buffer memory generating a first expected data set by an error correction on the third data set in the buffer; storing the first expected data set in the buffer memory; and extracting, from the first expected data set in the buffer, bits corresponding to the first value of the first single state data set in the buffer as the second data set.
Claims 17-20 recite the m value is either 3 or 4, and that the first voltage is between the first threshold voltage region, and the second threshold voltage region, and the second voltage is either between the fifth threshold voltage region and the sixth threshold voltage region, or that between fourth threshold voltage region and fifth threshold voltage region..
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827