DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination. Claims 1, 7, and 16 are independent claims. This Office Action is FINAL.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes multiple claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are recited in claims 1, 5-6, 16 and 20 with functional language italicized and generic placeholder and linking phrase in bold for claims 1, 5-6, 16 and 20:
1. A system comprising:
one or more first graphics processing clusters (GPCs) that are operating in a first state;
one or more second GPCs that are operating in a second state that is different from the first state; and
one or more testing components to perform a test of the one or more second GPCs based at least on the one or more second GPCs operating in the second state and the one or more first GPCs operating in the first state that is different from the second state.
5. The system of claim 1, further comprising:
one or more first texture processing clusters (TPCs) of the one or more first GPCs, the one or more first TPCs operating in the first state;
one or more second TPCs of the one or more first GPCs, the one or more second TPCs operating in the second state; and
one or more second testing components to perform a second test of the one or more second TPCs based at least on the one or more second TPCs operating in the second state.
6. The system of claim 1, wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a second system for performing deep learning operations;
a third system implemented using a machine;
a fourth system incorporating one or more virtual machines (VMs); a fifth system implemented at least partially in a data center; or
a sixth system implemented at least partially using cloud computing resources.
16. A system comprising:
one or more first texture processing clusters (TPCs) that are operating in a first state;
one or more second TPCs that are operating in a second state that is different from the first state; and
one or more testing components to perform a test of the one or more second TPCs based at least on the one or more first TPCs operating in the first state.
20. The system of claim 16, wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a second system for performing deep learning operations;
a third system implemented using a machine;
a fourth system incorporating one or more virtual machines (VMs);
a fifth system implemented at least partially in a data center; or
a sixth system implemented at least partially using cloud computing resources.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the originally filed specification as performing the claimed function, and equivalents thereof. The portions of the specification that describe the corresponding structure that performs the claimed functions for the claims above are Fig. 2B, paragraphs 0032-0036 and paragraph 0015, Fig. 5, paragraphs 0053-0065.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-9, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shirvani et al (U.S. Publ. No. 2018/0365017 A1), hereinafter Shirvani in view of Peng et al (U.S. Patent No. 8,341,476 B1), hereinafter Peng.
Regarding claim 1, Shirvani teaches:
A system comprising:
one or more first graphics processing clusters (GPCs) (Shirvani, Figs. 3, 4A shows GPC 350 that is described in paragraph 0050);
one or more second GPCs ( Shirvani, Figs. 3, 4A shows GPC 350 that is described in paragraph 0041 “one or more general processing clusters (GPCs) 350” Paragraph 0045 teaches “The state may indicate which GPC 350 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 320 manages the execution of a plurality of tasks on the one or more GPCs 350.”).
Shirvani does not distinctly disclose first GPCs that are operating in a first state; second GPCs that are operating in a second state that is different from the first state; and one or more testing components to perform a test of the one or more second GPCs based at least on the one or more second GPCs operating in the second state and the one or more first GPCs operating in the first state that is different from the second state.
Peng, in the same field of endeavor, teaches:
first GPCs that are operating in a first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “Partition 1 of the memory 112 [in active first state] is for access by the non-BIST components of the SOC circuit 104”);
second GPCs that are operating in a second state that is different from the first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”); and
one or more testing components (Peng, Fig. 1 , col. 2 lines 33-68 and col. 3, lines 1-23 Automated Test Equipment 102, BIST Engine 110 and Control Module 118) to perform a test of the one or more second GPCs (Peng, Fig. 4, block 406 “At 406, a BIST is executed on some or all of the second portion of the memory 112. For example, if Partition 1 of the memory 112 is for access by the non-BIST components of the SOC circuit 104, then the BIST is executed on Partitions 2, 3, and 4. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) based at least on the one or more second GPCs operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) and the one or more first GPCs operating in the first state that is different from the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” The two different portions of memory are in first state and second state concurrently at same time).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shirvani to incorporate the teachings of Peng and provide for first GPCs that are operating in a first state; second GPCs that are operating in a second state that is different from the first state; and one or more testing components to perform a test of the one or more second GPCs based at least on the one or more second GPCs operating in the second state and the one or more first GPCs operating in the first state that is different from the second state because first DUT could pass BIST when second DUT is inactive, but the first DUT may have functional failures when the second DUT is operating at full functionality, thus such a mechanism provides greater fault coverage and detection of faults (Peng, col. 1, lines 49-55).
Regarding claim 2, Shirvani as modified by Peng teaches all of the limitations of claim 1 as cited above and Peng further teaches wherein:
the one or more first GPCs are operating in the first state based at least on the one or more first GPCs operating in an active state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “Partition 1 of the memory 112 [in active first state] is for access by the non-BIST components of the SOC circuit 104”); and
the one or more second GPCs are operating in the second state based at least on the one or more second GPCs operating in at least one of an idle state, a sleep state, or a low- power state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”).
The motivation to combine for claim 2 is the same as the motivation to combine for claim 1.
Regarding claim 3, Shirvani as modified by Peng teaches all of the limitations of claim 1 as cited above and Peng further teaches wherein the test includes at least one of a structural test or a functional test (Peng, Col. 1, lines 47-55 teaches BIST is a type of structural test because adding hardware specifically for testing as shown in Fig. 1 but functional failures may occur).
The motivation to combine for claim 3 is the same as the motivation to combine for claim 1.
Regarding claim 5, Shirvani as modified by Gangasani teaches all of the limitations of claim 1 as cited above and Shirvani further teaches one or more first texture processing clusters (TPCs) of the one or more first GPCs (Shirvani, Fig. 4A shows GPC 350 includes multiple TPC 420 that is taught in paragraphs 0050-0055), the one or more first TPCs operating in the first state (Shirvani, paragraphs 0062 and 0070 teach TPCs operate in the same state as GPC, so when GPC is idle, see paragraph 0046, then TPC is in idle state.);
one or more second TPCs of the one or more first GPCs, the one or more second TPCs operating in the second state (Shirvani, Fig. 4A shows multiple TPCs 420 and paragraph 0051 teaches “pipeline manager 410 manages the configuration of the one or more TPCs 420 for processing tasks allocated to the GPC 350. In one embodiment, the pipeline manager 410 may configure at least one of the one or more TPCs 420 to implement at least a portion of a graphics rendering pipeline” (i.e. active state is second state). Paragraph 0062 teaches “tasks are allocated to a particular TPC 420 within a GPC 350” so different TPCs may be in different states.).
Shirvani does not distinctly disclose one or more second testing components to perform a second test of the one or more second TPCs based at least on the one or more second TPCs operating in the second state.
Peng, in the same field of endeavor, further teaches one or more second testing components (Peng, Fig. 1 , col. 2 lines 33-68 and col. 3, lines 1-23 Automated Test Equipment 102 or BIST Engine 110 and Control Module 118; e.g. BIST Engine 110 is second testing component) to perform a second test of the one or more second TPCs (Peng, Fig. 4, block 406 “At 406, a BIST is executed on some or all of the second portion of the memory 112. For example, if Partition 1 of the memory 112 is for access by the non-BIST components of the SOC circuit 104, then the BIST is executed on Partitions 2, 3, and 4. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) based at least on the one or more second TPCs operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”).
The motivation to combine for claim 5 is the same as the motivation to combine for claim 1.
Regarding claim 7, Shirvani teaches:
A method comprising:
determining that one or more first streaming multiprocessors (SMs) of a system (Shirvani, Figs. 4A, 5 shows SMs 440 that is described in paragraphs 0051, 0056, 0061-0068);
determining that one or more second SMs of the system (Shirvani, Figs. 4A, 5 shows SM 440 that is described in paragraph 0054 “Each TPC 420 included in the GPC 350 includes an M-Pipe Controller (MPC) 430, a primitive engine 435, one or more SMs 440” Paragraph 0062 teaches “the work distribution unit 325 dispatches tasks for execution on the GPCs 350 of the PPU 300. The tasks are allocated to a particular TPC 420 within a GPC 350 and, if the task is associated with a shader program, the task may be allocated to an SM 440.” Each TPC 420 contains multiple SM 440. If one GPC is in active state, then at least one TPC contained in that GPC is in active state and at least one SM contained in TPC is in active state.).
Shirvani does not distinctly disclose determining that first SMs are operating in a first state; determining that second SMs are operating in a second state that is different from the first state; and causing a test to be performed on the one or more second SMs based at least on the one or more second SMs operating in the second state and the one or more first SMs operating in the first state.
Peng, in the same field of endeavor, teaches:
determining that first SMs are operating in a first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “Partition 1 of the memory 112 [in active first state] is for access by the non-BIST components of the SOC circuit 104”);
determining that second SMs are operating in a second state that is different from the first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”); and
causing a test to be performed on the one or more second SMs (Peng, Fig. 4, block 406 “At 406, a BIST is executed on some or all of the second portion of the memory 112. For example, if Partition 1 of the memory 112 is for access by the non-BIST components of the SOC circuit 104, then the BIST is executed on Partitions 2, 3, and 4. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) based at least on the one or more second SMs operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) and the one or more first SMs operating in the first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” The two different portions of memory are in first state and second state concurrently at same time).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shirvani to incorporate the teachings of Peng and provide for determining that first SMs are operating in a first state; determining that second SMs are operating in a second state that is different from the first state; and causing a test to be performed on the one or more second SMs based at least on the one or more second SMs operating in the second state and the one or more first SMs operating in the first state because first DUT could pass BIST when second DUT is inactive, but the first DUT may have functional failures when the second DUT is operating at full functionality, thus such a mechanism provides greater fault coverage and detection of faults (Peng, col. 1, lines 49-55).
Regarding claim 8, Shirvani as modified by Peng teaches all of the limitations of claim 7 as cited above and Peng further teaches the one or more first SMs are operating in the first state based at least on the one or more first SMs operating in an active state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “Partition 1 of the memory 112 [in active first state] is for access by the non-BIST components of the SOC circuit 104”); and
the one or more second SMs are operating in the second state based at least on the one or more second SMs operating in at least one of an idle state, a sleep state, or a low- power state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”).
The motivation to combine for claim 8 is the same as the motivation to combine for claim 7.
Regarding claim 9, Shirvani as modified by Peng teaches all of the limitations of claim 7 as cited above and Peng further teaches wherein the test includes at least one of a structural test or a functional test (Peng, Col. 1, lines 47-55 teaches BIST is a type of structural test because adding hardware specifically for testing as shown in Fig. 1 but functional failures may occur).
The motivation to combine for claim 9 is the same as the motivation to combine for claim 7.
Regarding claim 11, Shirvani as modified by Peng teaches all of the limitations of claim 7 as cited above and Peng further teaches wherein the one or more first SMs are operating in the first state during a first time interval (Peng, col. 5, lines 30-67 Partition 1 is for access by non-BIST components and in active first state and Partitions 2-4 are in second idle or not active state that BIST is performed on for first iteration [i.e. first time interval] starting at 404 to 410 and for “No” in 410 (All Partitions not tested) loop back to 404 to start second iteration), and wherein the method further comprises:
determining that the one or more first SMs of the system are operating in the second state during a second time interval (Peng, col. 5, lines 66-67 and col. 6, lines 1-9 teaches second iteration of method 400 in which Partition 1, 3, 4 BIST is executed so Partition 1 is in second state of sleep/idle/not active during the second time interval); and
causing a second test to be performed on the one or more first SMs during the second time interval based at least on the one or more first SMs operating in the second state (Peng, col. 5, lines 66-67 and col. 6, lines 1-9 teaches second iteration of method 400 in which Partition 1, 3, 4 BIST is executed so Partition 1 is in second state of sleep/idle/not active during the second time interval and test is performed).
The motivation to combine for claim 11 is the same as the motivation to combine for claim 7.
Regarding claim 12, Shirvani as modified by Peng teaches all of the limitations of claim 11 as cited above and Peng further teaches:
the test is performed on the one or more second SMs using one or more first testing components (Peng, Fig. 1 , col. 2 lines 33-68 and col. 3, lines 1-23 Automated Test Equipment 102 or BIST Engine 110 and Control Module 118; e.g. ATE 102 is first testing component); and
the second test is performed on the one or more first SMs using one or more second testing components that are different from the one or more first testing components (Peng, Fig. 1 , col. 2 lines 33-68 and col. 3, lines 1-23 Automated Test Equipment 102 or BIST Engine 110 and Control Module 118; e.g. BIST Engine 110 is second testing component).
The motivation to combine for claim 12 is the same as the motivation to combine for claim 7.
Regarding claim 13, Shirvani as modified by Peng teaches all of the limitations of claim 7 as cited above and Peng further teaches wherein the determining that the one or more second SMs are operating in the second state comprises at least one of:
determining that a schedule indicates that the one or more second SMs are operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions and Fig. 4, col. 5, lines 7-67 and Col. 6, lines 1-25 teaches a schedule of testing created indicating: first iteration, Partition 1 is non-BIST component in active state, Partitions 2-4 BIST components under test that are not used/idle state; second iteration, Partition 2 is non-BIST component in active state, Partitions 1, 3-4 BIST components under test that are not used/idle state; and so on);
monitoring the one or more second SMs to determine that the one or more second SMs are operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”); or
receiving an indication that the one or more second SMs are operating in the second state (Peng, col. 6, lines 37-40 “At 502, the BIST is initiated on the portions of the memory 112 undergoing the test. The BIST is initiated by a triggering command or other signal from the ATE 102 over the input line 114.” This also indicates that Partitions are operating in not used/idle second state).
The motivation to combine for claim 13 is the same as the motivation to combine for claim 7.
Regarding claim 14, Shirvani as modified by Peng teaches all of the limitations of claim 7 as cited above and Peng teaches further comprising causing the one or more second SMs to operate in the first state based at least on the test being complete (Peng, Fig. 4, col. 5, lines 7-67 and col. 6, lines 1-25 teaches a first iteration, Partition 1 is non-BIST component in active state, Partitions 2-4 BIST components under test that are not used/idle state; second iteration, Partition 2 is non-BIST component in active state (thus for Partition 2 test is complete and operating in first state), Partitions 1, 3-4 BIST components under test that are not used/idle state).
The motivation to combine for claim 14 is the same as the motivation to combine for claim 7.
Regarding claim 15, Shirvani as modified by Peng teaches all of the limitations of claim 7 as cited above and Shirvani further teaches determining that one or more first graphics processing clusters (GPCs) of the system (Shirvani, Figs. 3, 4A shows GPC 350 that is described in paragraph 0050);
determining that one or more second GPCs of the system ( Shirvani, Figs. 3, 4A shows GPC 350 that is described in paragraph 0041 “one or more general processing clusters (GPCs) 350” Paragraph 0045 teaches “The state may indicate which GPC 350 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 320 manages the execution of a plurality of tasks on the one or more GPCs 350.”)
Shirvani does not distinctly disclose determining that the first GPCs of the system are operating in the first state; determining that the second GPCs of the system are operating in the second state; and causing a second test to be performed on the one or more second GPCs based at least on the one or more second GPCs operating in the second state.
Peng, in the same field of endeavor, further teaches:
determining that the first GPCs of the system are operating in the first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “Partition 1 of the memory 112 [in active first state] is for access by the non-BIST components of the SOC circuit 104”);
determining that the second GPCs of the system are operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”); and
causing a second test to be performed on the one or more second GPCs (Peng, Fig. 4, block 406 “At 406, a BIST is executed on some or all of the second portion of the memory 112. For example, if Partition 1 of the memory 112 is for access by the non-BIST components of the SOC circuit 104, then the BIST is executed on Partitions 2, 3, and 4. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) based at least on the one or more second GPCs operating in the second state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”).
The motivation to combine for claim 15 is the same as the motivation to combine for claim 7.
Regarding claim 16, Shirvani teaches:
A system comprising:
one or more first texture processing clusters (TPCs) (Shirvani, Fig. 4A shows GPC 350 includes multiple TPC 420 that is taught in paragraphs 0050-0055);
one or more second TPCs (Shirvani, Fig. 4A shows multiple TPCs 420 and paragraph 0051 teaches “pipeline manager 410 manages the configuration of the one or more TPCs 420 for processing tasks allocated to the GPC 350. In one embodiment, the pipeline manager 410 may configure at least one of the one or more TPCs 420 to implement at least a portion of a graphics rendering pipeline”. Paragraph 0062 teaches “tasks are allocated to a particular TPC 420 within a GPC 350” so different TPCs may be in different states.).
Shirvani does not distinctly disclose first TPCs that are operating in a first state; second TPCs that are operating in a second state that is different from the first state; and one or more testing components to perform a test of the one or more second TPCs based at least on the one or more first TPCs operating in the first state.
Peng, in the same field of endeavor, teaches:
first TPCs that are operating in a first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “Partition 1 of the memory 112 [in active first state] is for access by the non-BIST components of the SOC circuit 104”);
second TPCs that are operating in a second state that is different from the first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” Col. 5, lines 30-35 teaches that “then the BIST is executed on Partitions 2, 3, and 4 [in sleep/idle second state]. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”); and
one or more testing components (Peng, Fig. 1, col. 2 lines 33-68 and col. 3, lines 1-23 Automated Test Equipment 102, BIST Engine 110 and Control Module 118) to perform a test of the one or more second TPCs (Peng, Fig. 4, block 406 “At 406, a BIST is executed on some or all of the second portion of the memory 112. For example, if Partition 1 of the memory 112 is for access by the non-BIST components of the SOC circuit 104, then the BIST is executed on Partitions 2, 3, and 4. By testing Partitions 2, 3, and 4, most of the memory 112 is tested during this particular BIST test while still allowing the non-BIST components of the SOC circuit 104 to operate in a normal fashion because the components have access to Partition 1 of the memory 112.”) based at least on the one or more first TPCs operating in the first state (Peng, Fig. 3 shows embedded memory 112 divided into several partitions. Col. 4, lines 11-21 teach “The BIST engine 110 of the present disclosure allows a BIST to be executed on a portion of the memory 112 [in sleep/idle second state] rather than on the entire memory. By executing a BIST on only a portion of the memory 112, the components on the SOC circuit 104 may access other portions of the memory 112 [in active first state] for their exclusive use.” The two different portions of memory are in first state and second state concurrently at same time).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shirvani to incorporate the teachings of Peng and provide for first TPCs that are operating in a first state; second TPCs that are operating in a second state that is different from the first state; and one or more testing components to perform a test of the one or more second TPCs based at least on the one or more first TPCs operating in the first state because first DUT could pass BIST when second DUT is inactive, but the first DUT may have functional failures when the second DUT is operating at full functionality, thus such a mechanism provides greater fault coverage and detection of faults (Peng, col. 1, lines 49-55).
Claims 4, 6, and 10 are rejected under 35 U.S.C. § 103 as being unpatentable over Shirvani in view of Peng and further in view of Gangasani et al. (U.S. Patent Publication No. 2012/0226942 A1), hereinafter Gangasani.
Regarding dependent claim 4, Shirvani in view of Peng teaches all of the features with respect to claim 1 as given above. The combination of Shirvani in view of Peng does not distinctly disclose wherein the performance of the test of the one or more second GPCs comprises: storing state information of the one or more second GPCs; isolating the one or more second GPCs from the one or more first GPCs; performing the test of the one or more second GPCs by at least obtaining a result generated by the one or more second GPCs; and restoring the state information to the one or more second GPCs.
Gangasani, in the same field of endeavor, teaches wherein the performance of the test of the one or more second GPCs comprises:
storing state information of the one or more second GPCs (Gangasani, Fig. 10, block 1018, paragraph 0090);
isolating the one or more second GPCs from the one or more first GPCs (Gangasani, Fig. 10, block 1020, paragraph 0091, Fig.6, paragraph 0052);
performing the test of the one or more second GPCs by at least obtaining a result generated by the one or more second GPCs (Gangasani, Fig. 10, blocks 1022, 1024, 1040, 1042, 1044, 1026, paragraph 0091-0093); and
restoring the state information to the one or more second GPCs (Gangasani, Fig. 10, block 1028, paragraph 0096).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shirvani with that of Peng and to incorporate the teachings of Gangasani and provide for wherein the performance of the test of the one or more second GPCs comprises: storing state information of the one or more second GPCs; isolating the one or more second GPCs from the one or more first GPCs; performing the test of the one or more second GPCs by at least obtaining a result generated by the one or more second GPCs; and restoring the state information to the one or more second GPCs because such a mechanism provides generic BIST solutions without adversely increasing the total test time and impacting system performance while still meeting typical BIST goals of thorough fault-coverage and speed-of-test metrics. (Gangasani, paragraph 0029).
Regarding dependent claim 6, Shirvani in view of Peng teaches all of the features with respect to claim 1 as given above. The combination of Shirvani in view of Peng does not distinctly disclose wherein the system is comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a second system for performing deep learning operations; a third system implemented using a machine; a fourth system incorporating one or more virtual machines (VMs); a fifth system implemented at least partially in a data center; or a sixth system implemented at least partially using cloud computing resources.
Gangasani, in the same field of endeavor, teaches wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine (Gangasani, paragraphs 0002-0003 teaches systems and electronic devices that are real time mission critical “The consequences of such failures are of typically much greater concern when the electrical devices in which the failures occur are performing safety-related processes. The safety-related processes include applications that require on-going monitoring and verification of the processor performing safety-related processes.” Paragraph 0021 teaches “Each of the modules may be a system in its own right, or subsystems that are incorporated into electronic devices such as an automotive or avionics controller…”);
a second system for performing deep learning operations;
a third system implemented using a machine (Gangasani, paragraphs 0002-0003 teaches systems and electronic devices that are real time mission critical “The consequences of such failures are of typically much greater concern when the electrical devices in which the failures occur are performing safety-related processes. The safety-related processes include applications that require on-going monitoring and verification of the processor performing safety-related processes.” Paragraph 0021 teaches “Each of the modules may be a system in its own right, or subsystems that are incorporated into electronic devices such as an automotive or avionics controller…”);
a fourth system incorporating one or more virtual machines (VMs);
a fifth system implemented at least partially in a data center; or
a sixth system implemented at least partially using cloud computing resources.
The motivation to combine for claim 6 is the same as the motivation to combine for claim 4.
Regarding dependent claim 10, Shirvani in view of Peng teaches all of the features with respect to claim 7 as given above. The combination of Shirvani in view of Peng does not distinctly disclose wherein the causing the test to be performed of the one or more second SMs comprises: storing state information of the one or more second SMs; isolating the one or more second SMs from the one or more first SMs; performing the test of the one or more second SMs by at least obtaining a result generated by the one or more second SMs; and restoring the state information to the one or more second SMs.
Gangasani, in the same field of endeavor, teaches wherein the causing the test to be performed of the one or more second SMs comprises:
storing state information of the one or more second SMs (Gangasani, Fig. 10, block 1018, paragraph 0090);
isolating the one or more second SMs from the one or more first SMs (Gangasani, Fig. 10, block 1020, paragraph 0091, Fig.6, paragraph 0052);
performing the test of the one or more second SMs by at least obtaining a result generated by the one or more second SMs (Gangasani, Fig. 10, blocks 1022, 1024, 1040, 1042, 1044, 1026, paragraph 0091-0093); and
restoring the state information to the one or more second SMs (Gangasani, Fig. 10, block 1028, paragraph 0096).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shirvani with that of Peng and to incorporate the teachings of Gangasani and provide for wherein the causing the test to be performed of the one or more second SMs comprises: storing state information of the one or more second SMs; isolating the one or more second SMs from the one or more first SMs; performing the test of the one or more second SMs by at least obtaining a result generated by the one or more second SMs; and restoring the state information to the one or more second SMs because such a mechanism provides generic BIST solutions without adversely increasing the total test time and impacting system performance while still meeting typical BIST goals of thorough fault-coverage and speed-of-test metrics. (Gangasani, paragraph 0029).
Claims 17-20, the system claims that are similar in scope to system claims 2-4, 6, respectively, are rejected on the same grounds as claims 2-4, 6.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the arguments are directed to the claim amendments that are addressed in the Examiner’s new grounds of rejections given above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure. Applicants are required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Franko et al. (U.S. Patent Publn. No. 2009/0167771 A1) teaches a graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCie) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCie endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs.
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to INDRANIL CHOWDHURY whose telephone number is (571)272-0446. The examiner can normally be reached Mon.-Fri. 9:30-7:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/INDRANIL CHOWDHURY/ Examiner, Art Unit 2114
/ASHISH THOMAS/ Supervisory Patent Examiner, Art Unit 2114