Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites article “An" in line 1. The article is incorrect.
For purpose of compact prosecution, article “An” will be treated as if it were “A”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (U.S. 2020/0365655 A1, hereinafter refer to Chiu) in view of Van Dal et al. (U.S. 2020/0311524 A1, hereinafter refer to Van Dal).
Regarding Claim 1: Chiu discloses an RRAM memory cell (see Chiu, Figs.3 and 10A-11 as shown below and ¶ [0007]) comprising:
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a semiconductor substrate (see Chiu, Figs.10A-11 as shown above and ¶ [0009]);
a lower electrode (132/134) disposed over the semiconductor substrate (see Chiu, Figs.10A-11 as shown above and ¶ [0033]);
a first block of resistive switching dielectric material (140/142) electrically connected to the lower electrode (132/134) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0013], and ¶ [0020]);
a second block of resistive switching dielectric material (140/142) electrically connected to the lower electrode (132/134) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0013], and ¶ [0020]);
a first upper electrode (152/162) electrically connected to the first block of resistive switching dielectric material (140/142) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0015], and ¶ [0020]);
a second upper electrode (152/162) electrically connected to the second block of resistive switching dielectric material (140/142) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0015], and ¶ [0020]);
an electrical contact (218a) (140/142) (see Chiu, Figs.10A-10B as shown above and ¶ [0032]);
a first resistive contact (212) electrically connected between the first upper electrode (152/162) and the electrical contact (218a) (see Chiu, Figs.10A-10B as shown above and ¶ [0032]); and
a second resistive contact (212) electrically connected between the second upper electrode (152/162) and the electrical contact (218a) (see Chiu, Figs.10A-10B as shown above and ¶ [0032]);
wherein the first resistive contact (212) has a first electrical resistance between the first upper electrode (152/162) and the electrical contact (218a), and the second resistive contact (212) has a second electrical resistance between the second upper electrode (152/162) and the electrical contact (218a), and the first electrical resistance is different from the second electrical resistance (note: the first electrical resistance is necessary different from the second electrical resistance due to the nature of the processing conditions of forming upper electrodes and resistive contacts, for example due to imperfection of the dimensions of upper electrodes and resistive contacts) (see Chiu, Figs.10A-10B as shown above).
Chiu is silent upon explicitly disclosing wherein an electrical contact is a continuous layer, continuously connects the first resistive contact and the second resistive contact.
For support see Van Dal, which teaches wherein an electrical contact (127) is a continuous layer, continuously connects the first resistive contact (note: a contact region between top electrode 130c and electrical contact 127 is considered as a resistive contact) and the second resistive contact (note: a contact region between top electrode 130c and electrical contact 127 is considered as a resistive contact) (note: the Van Dal to electrode 130c is equivalent to the claimed limitation of separable top electrode and resistive contact because making separable conductive layers is not sufficient by itself to patentably distinguish over the integral conductive layer unless there are new or unexpected results) (see Van Dal, Fig.2 as shown below and ¶ [0038]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu and Van Dal to enable the Chiu electrical contact to be a continuous layer, continuously connects the first resistive contact and the second resistive contact as taught by Van Dal in order to obtain a resistive random-access memory (RRAM) cells, that the memory elements formed to have different threshold voltages (e.g., different voltages at which the memory elements change between high resistive states and low resistive states).
Regarding Claim 2: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein a transistor formed on the semiconductor substrate, wherein the lower electrode (132/134) is electrically connected to the transistor, and wherein the first block of resistive switching dielectric material (140/142) and the second block of resistive switching dielectric material (140/142) are disposed above the transistor (see Chiu, Figs.10A-11 as shown above).
Regarding Claim 3: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein a transistor formed on the semiconductor substrate, wherein the lower electrode (132/134)) is electrically connected to the transistor, and wherein the first block of resistive switching dielectric material (140/142) and the second block of resistive switching dielectric material (140/142) are disposed between the transistor and the electrical contact (218a) (see Chiu, Figs.10A-11 as shown above).
Regarding Claim 4: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein a source line electrically connected to the transistor (see Chiu, Figs.10A-11 as shown above).
Regarding Claim 5: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein a first bit line (218a) electrically connected to the first upper electrode (152/162) (see Chiu, Figs.10A-10B as shown above); and
a second bit line (218a) electrically connected to the second upper electrode (152/162) (see Chiu, Figs.10A-10B as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 6: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein a third block of resistive switching dielectric material (130b) electrically connected to the lower electrode (126/130a) (note: tunnel barrier layer in resistive random-access memory (RRAM) can perform both tunneling and resistive switching functions, acting as an internal resistor that modulates current flow and switching behavior) (see Van Dal, Fig.2 as shown above);
a third upper electrode (a lower portion of electrode 130c) electrically connected to the third block of resistive switching dielectric material (130b) (see Van Dal, Fig.2 as shown above); and
a third resistive contact (a contact region between top electrode 130c and electrical contact 127 is considered as a resistive contact) electrically connected between the third upper electrode (a lower portion of electrode 130c) and the electrical contact (127) (note: the Van Dal to electrode 130c is equivalent to the claimed limitation of separable top electrode and resistive contact because making separable conductive layers is not sufficient by itself to patentably distinguish over the integral conductive layer unless there are new or unexpected results) (see Van Dal, Fig.2 as shown above, ¶ [0038]);
wherein the third resistive contact has a third electrical resistance between the third upper electrode and the electrical contact (127), and the third electrical resistance is different from the first electrical resistance and the second electrical resistance (see Van Dal, Fig.2 as shown above).
Regarding Claim 7: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein a third bit line electrically connected to the third upper electrode (a lower portion of electrode 130c) (see Van Dal, Fig.2 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 8: Chiu as modified teaches an RRAM memory cell as set forth in claim 1 as above. The combination of Chiu and Van Dal further teaches wherein the first block of resistive switching dielectric material (140/142) and the second block of resistive switching dielectric material (140/142) comprise one of HfO2, Al2O3, TaOx, TiOx, WOx, VOx or CuOx (see Chiu, Figs.10A-10B as shown above and ¶ [0013]).
Regarding Claim 12: Chiu discloses a method of forming a RRAM memory cell (see Chiu, Figs.3 and 10A-11 as shown above and ¶ [0007]), comprising:
forming a transistor on a semiconductor substrate (see Chiu, Figs.10A-11 as shown above and ¶ [0009]);
forming a lower electrode (132/134) disposed over the semiconductor substrate;
forming a first block of resistive switching dielectric material (140/142) electrically that is connected to the lower electrode (132/134) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0013], and ¶ [0020]);
forming a second block of resistive switching dielectric material (140/142) that is electrically connected to the lower electrode (132/134) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0013], and ¶ [0020]);
forming a first upper electrode (152/162) that is electrically connected to the first block of resistive switching dielectric material (140/142) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0015], and ¶ [0020]);
forming a second upper electrode (152/162) that is electrically connected to the second block of resistive switching dielectric material (140/142) (see Chiu, Figs.3 and 10A-11 as shown above, ¶ [0015], and ¶ [0020]);
forming an electrical contact (218a) (see Chiu, Figs.10A-11 as shown above);
forming a first resistive contact (212) that is electrically connected between the first upper electrode (152/162) and the electrical contact (218a) (see Chiu, Figs.10A-10B as shown above and ¶ [0032]); and
forming a second resistive contact (212) that is electrically connected between the second upper electrode (152/162) and the electrical contact (218a) (see Chiu, Figs.10A-10B as shown above and ¶ [0032]);
wherein the first resistive contact (212) has a first electrical resistance between the first upper electrode (152/162) and the electrical contact (218a), and the second resistive contact (212) has a second electrical resistance between the second upper electrode (152/162) and the electrical contact (218a), and the first electrical resistance is different from the second electrical resistance r(note: the first electrical resistance is necessary different from the second electrical resistance due to the nature of the processing conditions of forming upper electrodes and resistive contacts, for example due to imperfection of the dimensions of upper electrodes and resistive contacts) (see Chiu, Figs.10A-10B as shown above).
Chiu is silent upon explicitly disclosing wherein an electrical contact is a continuous layer, continuously connects the first resistive contact and the second resistive contact.
For support see Van Dal, which teaches wherein an electrical contact (127) is a continuous layer, continuously connects the first resistive contact (note: a contact region between top electrode 130c and electrical contact 127 is considered as a resistive contact) and the second resistive contact (note: a contact region between top electrode 130c and electrical contact 127 is considered as a resistive contact) (note: the Van Dal to electrode 130c is equivalent to the claimed limitation of separable top electrode and resistive contact because making separable conductive layers is not sufficient by itself to patentably distinguish over the integral conductive layer unless there are new or unexpected results) (see Van Dal, Fig.2 as shown above and ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu and Van Dal to enable the Chiu electrical contact to be a continuous layer, continuously connects the first resistive contact and the second resistive contact as taught by Van Dal in order to obtain a resistive random-access memory (RRAM) cells, that the memory elements formed to have different threshold voltages (e.g., different voltages at which the memory elements change between high resistive states and low resistive states).
Regarding Claim 13: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein the first block of resistive switching dielectric material (140/142) and the second block of resistive switching dielectric material (140/142) are disposed above the transistor (see Chiu, Figs.10A-11 as shown above).
Regarding Claim 14: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein the first block of resistive switching dielectric material (140/142) and the second block of resistive switching dielectric material (140/142) are disposed between the transistor and the electrical contact (218a) (see Chiu, Figs.10A-11 as shown above).
Regarding Claim 15: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein forming a source line that is electrically connected to the transistor (see Chiu, Figs.10A-11 as shown above).
Regarding Claim 16: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein forming a first bit line that is electrically connected to the first upper electrode (152/162) (see Chiu, Figs.10A-10B as shown above); and
forming a second bit line that is electrically connected to the second upper electrode (152/162) (see Chiu, Figs.10A-10B as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 17: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein forming a third block of resistive switching dielectric material (130b) that is electrically connected to the lower electrode (126/130a) (note: tunnel barrier layer in resistive random-access memory (RRAM) can perform both tunneling and resistive switching functions, acting as an internal resistor that modulates current flow and switching behavior) (see Van Dal, Fig.2 as shown above);
forming a third upper electrode (a lower portion of electrode 130c) that is electrically connected to the third block of resistive switching dielectric material (130b) (see Van Dal, Fig.2 as shown above); and
forming a third resistive contact (a contact region between top electrode 130c and electrical contact 127 is considered as a resistive contact) that is electrically connected between the third upper electrode (a lower portion of electrode 130c) and the electrical contact (127) (note: the Van Dal to electrode 130c is equivalent to the claimed limitation of separable top electrode and resistive contact because making separable conductive layers is not sufficient by itself to patentably distinguish over the integral conductive layer unless there are new or unexpected results) (see Van Dal, Fig.2 as shown above, ¶ [0038]);
wherein the third resistive contact has a third electrical resistance between the third upper electrode and the electrical contact (127), and the third electrical resistance is different from the first electrical resistance and the second electrical resistance (see Van Dal, Fig.2 as shown above).
Regarding Claim 18: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein forming a third bit line that is electrically connected to the third upper electrode (a lower portion of electrode 130c) (see Van Dal, Fig.2 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 19: Chiu as modified teaches a method of forming a RRAM memory cell as set forth in claim 12 as above. The combination of Chiu and Van Dal further teaches wherein the first block of resistive switching dielectric material (140/142) and the second block of resistive switching dielectric material (140/142) comprise one of HfO2, Al2O3, TaOx, TiOx, WOx, VOx or CuOx see Chiu, Figs.10A-10B as shown above and ¶ [0013]).
Claim(s) 9-11 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (U.S. 2020/0365655 A1, hereinafter refer to Chiu) and Van Dal et al. (U.S. 2020/0311524 A1, hereinafter refer to Van Dal) as applied to claims 1 and 12 above, and further in view of Zhou et al. (U.S. 2018/0145253 A1, hereinafter refer to Zhou).
Regarding Claims 9, 10, and 11: Chiu as modified teaches an RRAM memory cell as applied to claim 1 above. The combination of Chiu and Van Dal is silent upon explicitly disclosing wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2 and a sublayer of Al2O3 (as claimed in claim 9);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Hf, and a sublayer of TaOx (as claimed in claim 10);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Ti, and a sublayer of TiOx (as claimed in claim 11).
For support see Zhou, which teaches wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2 and a sublayer of Al2O3 (see Zhou, ¶ [0021]) (as claimed in claim 9);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Hf, and a sublayer of TaOx (see Zhou, ¶ [0021]) (as claimed in claim 10);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Ti, and a sublayer of TiOx (see Zhou, ¶ [0021]) (as claimed in claim 11).
The combination of Chiu and Van Dal teachers claimed invention except for the material of resistive switching dielectric material. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu, Van Dal, and Zhou to enable the known resistive switching dielectric material comprise a sublayer of HfO2/Al2O3, HfO2/Hf/TaOx, HfO2/Ti/TiOx as taught by Zhou in order to include an oxygen scavenger layers, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Regarding Claims 20, 21, and 22: Chiu as modified teaches a method of forming a RRAM memory cell as applied to claim 12 above. The combination of Chiu and Van Dal is silent upon explicitly disclosing wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2 and a sublayer of Al2O3 (as claimed in claim 20);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Hf, and a sublayer of TaOx (as claimed in claim 21);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Ti, and a sublayer of TiOx (as claimed in claim 22).
For support see Zhou, which teaches wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2 and a sublayer of Al2O3 (see Zhou, ¶ [0021]) (as claimed in claim 20);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Hf, and a sublayer of TaOx (see Zhou, ¶ [0021]) (as claimed in claim 21);
wherein the first block of resistive switching dielectric material and the second block of resistive switching dielectric material comprise a sublayer of HfO2, a sublayer of Ti, and a sublayer of TiOx (see Zhou, ¶ [0021]) (as claimed in claim 22).
The combination of Chiu and Van Dal teachers claimed invention except for the material of resistive switching dielectric material. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu, Van Dal, and Zhou to enable the known resistive switching dielectric material comprise a sublayer of HfO2/Al2O3, HfO2/Hf/TaOx, HfO2/Ti/TiOx as taught by Zhou in order to include an oxygen scavenger layers, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
