DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 1-7 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 1 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: receiving, by a controller that is associated with a resistive memory element, a target conductance associated with the resistive memory element; adjusting, by the controller and while the controller is in a program mode, a conductance associated with the resistive memory element until the conductance is within a first range of the target conductance; determining, by the controller and while the controller is in the program mode, whether the conductance is within a second range of the target conductance, wherein determining whether the conductance is within the second range comprises converting a transient current flowing through the resistive memory element during the program mode into a transient timing signal, and measuring a phase shift between the transient timing signal and a reference timing signal representing the target conductance; and applying, by the controller and while the controller is in the program mode, electrical pulses to the resistive memory element that adjust the conductance associated with the resistive memory element until the conductance is within the second range of the target conductance, and a combination of other limitations in the independent claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 13-14, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 10, 15, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy (PGPUB 20240062814), hereinafter as Guy, in view of Syed et al. (Patent 11988555), hereinafter as Syed.
Regarding claim 8, Guy teaches a system comprising: a resistive memory element; and a controller that is coupled to the resistive memory element (Fig 1) and is configured to perform operations comprising:
receiving, target conductance (Fig 5) associated with the resistive memory element;
adjusting, while the controller is in a program mode, a conductance associated with the resistive memory element until the conductance is within a first range of the target conductance (Fig 7, step 701);
determining whether the conductance is within a second range of the target conductance; and applying, while the controller is in the program mode, electrical pulses to the resistive memory element that adjust the conductance associated with the resistive memory element until the conductance is within the second range of the target conductance (Fig 7, step 705),
but not expressly determining memory element state by measuring current,
Syed teaches a sensing circuit coupled to an output associated with the resistive memory element, the sensing circuit configured to measure the conductance of the resistive memory element using a transient current of the same electrical pulses applied by the controller to program the resistive memory element (col 4, line 52-55 “resistance state of the cell can be read during programming”).
Since Syed and Guy are both from the same field of semiconductor memory device, the purpose disclosed by Syed would have been recognized in the pertinent art of Guy.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to determine the resistance element state during programming as in Syed into the device of Guy for the purpose of improving reading speed of the memory cell.
Regarding claim 10, the examiner takes note that it is well known in the field that a cycling circuit that is configured to generate clocked pulses that are used to generate the electrical pulses.
Regarding claim 15, Guy teaches a controller that is coupled to a resistive memory element (Fig 1) and is configured to perform operations comprising:
receiving a target conductance (Fig 5) associated with the resistive memory element;
adjusting, while the controller is in a program mode, a conductance associated with the resistive memory element until the conductance is within a first range of the target conductance (Fig 7, step 701);
determining, by the controller, whether the conductance is within a second range of the target conductance; and applying, by the controller and while the controller is in the program mode, electrical pulses to the resistive memory element that adjust the conductance associated with the resistive memory element until the conductance is within the second range of the target conductance (Fig 7, step 705).
But does not teach use the same biasing configuration for both reading/writing,
Syed teaches to perform the adjusting, determining, and applying operations while maintaining a continuous programming bias configuration on select lines of a memory array coupled to the resistive memory element, without switching to a read bias configuration to determine whether the conductance is within the second range (col 4, line 52-55).
The reason for combining the references used in rejection of claim 8 applies.
Regarding claim 18, Guy and Syed teaches resistive memory element in the plurality of resistive memory elements is associated with a controller in an array of controllers, except each element associated with a separate/unique controller. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a memory element associate with a unique controller, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. V. Bemis Co., 193 USPQ 8.
Regarding claim 19, the examiner takes note that it is well known in the field that the controller includes a read mode that applies a read bias to a memory array during a read operation, and the read mode comprises a different operating mode than the program mode.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy and Syed, in view of Lee et al. (PGPUB 20240127892), hereinafter as Lee.
Regarding claim 9, Guy and Syed teach a system as in rejection of claim 8,
but not expressly in a program mode, an offset voltage associated with the resistive memory element.
Lee teaches an auto-offset zeroing circuit that is configured while the controller is in the program mode to adjust an offset voltage associated with the resistive memory element ([0044]).
Since Lee and Guy are both from the same field of semiconductor memory device, the purpose disclosed by Lee would have been recognized in the pertinent art of Guy.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use an offset as in Lee into the method of Guy for the purpose of writing data into a memory cell.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy and Syed, in view of Chen et al. (PGPUB 20250378885) hereinafter as Chen.
Regarding claim 11, Guy and Syed teach a system as in rejection of claim 8,
Bu not expressly a tapping circuit that is configured to receive a data signal from a column multiplexer associated with the resistive memory element.
Chen teaches to receive a data signal from a column multiplexer associated with the resistive memory element (Fig 5B, clamp circuit 541, and it is well known a column multiplexer is used in a memory device).
Since Chen and Guy are both from the same field of semiconductor memory device, the purpose disclosed by Chen would have been recognized in the pertinent art of Guy.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use tapping circuit as in Chen into the method of Guy for the purpose of controlling data writing into a memory cell.
Regarding claim 12, Guy teaches a tripping detector circuit that is configured to, in response to receiving a signal from a flip flop, enable the controller to apply the electrical pulses (Fig 5B, 546).
The reason for combining the references used in rejection of claim 11 applies.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy and Syed, in view of Kong et al. (PGPUB 20240331742) hereinafter as Kong.
Regarding claim 16, Guy and Syed teach a controller as in rejection of claim 15,
But not expressly a phase-shift detector, Kong teaches a phase-shift detector that includes:
a first input that is configured to receive a program current from the resistive memory element (Fig 7 D_I);
a second input that is configured to receive a reference current from a reference pulse generator (Fig 7, VrefQ);
a first output (Fig 7, output of 552) that is configured to transmit a first digital output signal based on the program current; and
a second output (Fig 7, output of 554) that is configured to transmit a second digital output signal based on the reference current.
Since Kong and Guy are both from the same field of semiconductor memory device, the purpose disclosed by Kong would have been recognized in the pertinent art of Guy.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use phase-shift detecting circuit as in Kong into the system of Guy for the purpose of controlling data writing into a memory cell.
Regarding claim 17, Guy teaches a latch pulse generator that is configured to generate a pulse signal based on the first digital output signal and the second digital output signal, the pulse signal having a duration that is substantially similar to a time difference between the first digital output signal and the second digital output signal (Fig 7, D-latches).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Claim Interpretation
In amended claim 1, “a transient current” and “a transient timing signal” are not clearly defined in the spec, and there is no whereabout information in the spec within the filing of 6/11/2026 from the applicant.
In the remaining of the office action, “a transient current” is being treated as “a current”, and “a transient timing signal” is being treated as “a timing signal”.
In amended claim 8, “a transient current” present a similar issue as that of claim 1.
In amended claim 15, “a continuous programming bias” is not clearly defined in the spec. In the remaining of the office action, it is being treated as “a bias”, as a bias signal is inherently will have a continuous property even if it goes up or goes down in values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
