DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites “the second electrode regions” (line 13) which should be replaced with “second electrode regions” to avoid antecedent basis issue.
Claim 16 recites “the second electrode regions” (lines 10-11) which should be replaced with “second electrode regions” to avoid antecedent basis issue.
Claim 20 recites “the first electrode regions” (line 12) which should be replaced with “first electrode regions” to avoid antecedent basis issue.
Claim 20 recites “the second electrode regions” (lines 13-14) which should be replaced with “second electrode regions” to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites “a lower structure” twice, in lines 2 and 3. It is unclear whether the second recited “a lower structure” (line 3) is intended to relate back to “a lower structure” recited in line 2 or to set forth an additional lower structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 9-10, 12, 15-16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139922 to Jhan et al. (hereinafter Jhan) in view of Tegen et al. (US 2009/0294907, hereinafter Tegen).
With respect to claim 1, Jhan discloses a semiconductor device (e.g., DRAM memory) (Jhan, Figs. 2K, 3, ¶0019-¶0040, ¶0077-¶0078), comprising:
a lower structure (e.g., bit line structures 200 and contact structures 300b) (Jhan, Figs. 2K, 3, ¶0022-¶0027) including conductive regions;
a capacitor (600) (Jhan, Figs. 2K, 3, ¶0031-¶0033, ¶0039-¶0040) including first electrode structures (600a) electrically connected to the conductive regions (300b) of the lower structure, a dielectric layer (600b) covering the first electrode structures (600a), and a second electrode structure (600c) on the dielectric layer (600b); and
an upper support pattern (510d) (Jhan, Figs. 2K, 3, ¶0032-¶0038) in contact with the first electrode structures (600a),
wherein each of the first electrode structures (600a) includes:
a first electrode region (e.g., a vertical lower portion of the first electrode 600a extending to the lower support layer 510b) (Jhan, Figs. 2K, 3,¶0031, ¶0037-¶0038) extending vertically; and
a second electrode region (e.g., a vertical upper portion of the first electrode 600a extending to from the lower support layer 510b to the upper support layer 510d) extending upwardly from the first electrode region; and
wherein the upper support pattern (510d) includes:
a first layer (512d) (Jhan, Figs. 2K, 3, ¶0031, ¶0037-¶0038) covering surfaces (e.g., side surfaces) of the second electrode regions (e.g., the vertical upper portions of the adjacent first electrode 600a) of the first electrode structures (600a) and connected to each other; and
a second layer (511d) (Jhan, Figs. 2K, 3, ¶0035) on the first layer (512d) and including a material (carbon-doped material) different from a material of the first layer (e.g., insulating layer 512d not doped with carbon) (Jhan, Figs. 2K, 3, ¶0037).
Further, Jhan does not specifically disclose a second electrode region having a side surface not vertically aligned with a side surface of the first electrode region, and wherein the upper support pattern includes: a first layer covering upper surfaces of the second electrode regions of the first electrode structures.
However, Tegen teaches forming a capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066) having a high aspect ratio structures and reduced footprint, wherein the capacitor structure comprises stacked structures having a lower region with a first diameter and an upper region with a second diameter smaller than the first diameter of the lower region, wherein the lower region includes the first electrode (80) on sides of the fill material (75) and the upper region includes first electrode (80) on sides of the fill material (75), and a second upper electrode region having a side surface not vertically aligned with a side surface of the first lower electrode region, and wherein the upper support pattern (e.g., bridge 110) (Tegen, Figs. 2a-2b, 7e, ¶0039, ¶0044) includes: a first layer (e.g., insulating layer 50) covering upper surfaces of the second electrode regions (e.g., upper electrode regions) of the first electrode structures (80), to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan by forming the first electrode structures having a shape of the stacked truncated cones and a bridge structure including an insulating layer on upper portions of the first electrode structures as taught by Tegen to have the semiconductor device, comprising: a second electrode region having a side surface not vertically aligned with a side surface of the first electrode region, and wherein the upper support pattern includes: a first layer covering upper surfaces of the second electrode regions of the first electrode structures, in order to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
Regarding claims 2 and 3, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan does not specifically disclose the semiconductor device, wherein, in each of the first electrode structures, a width of a lower region of the second electrode regions has a width less than a width of an upper region of the first electrode regions, and wherein a width of at least a portion of the second electrode regions increases in a direction away from the first electrode region (as claimed in claim 2); wherein the side surfaces of the second electrode regions are inclined with respect to upper surfaces of the first electrode regions (as claimed in claim 3).
However, Tegen teaches forming a capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066), wherein, in each of the first electrode structures (e.g., first electrode 80 in the openings 101/101 filled with the fill material 75), a width of a lower region of the second electrode regions (e.g., upper portions of the first electrode structure of the stacked capacitor) (Tegen, Figs. 2a-2b, 7e, ¶0035-¶0038) has a width less than a width of an upper region of the first electrode regions (e.g., a lower portion of the first electrode structure of the stacked capacitor), wherein a width of at least a portion of the second electrode regions increases in a direction away from the first electrode region, wherein the side surfaces of the second electrode regions (e.g., the upper portions of the first electrode structure of the stacked capacitor) are inclined with respect to upper surfaces of the first electrode regions (e.g., the lower portions of the first electrode structure of the stacked capacitor).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming the first electrode structures having a shape of the stacked truncated cones having a lower region with a diameter greater than that of the upper region as taught by Tegen to have the semiconductor device, wherein, in each of the first electrode structures, a width of a lower region of the second electrode regions has a width less than a width of an upper region of the first electrode regions, and wherein a width of at least a portion of the second electrode regions increases in a direction away from the first electrode region (as claimed in claim 2); wherein the side surfaces of the second electrode regions are inclined with respect to upper surfaces of the first electrode regions (as claimed in claim 3), in order to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
Regarding claim 7, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan does not specifically disclose the semiconductor device, wherein a distance between the second electrode regions is greater than a distance between upper portions of the first electrode regions.
However, Tegen teaches forming a capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066), wherein, in each of the first electrode structures (e.g., first electrode 80 in the openings 101/101 filled with the fill material 75), a width of a lower region of the second electrode regions (e.g., upper portions of the first electrode structure of the stacked capacitor) (Tegen, Figs. 2a-2b, 7e, ¶0035-¶0038) has a width less than a width of an upper region of the first electrode regions (e.g., a lower portion of the first electrode structure of the stacked capacitor), such that a distance between the second electrode regions (e.g., the upper portions of the first electrode structure of the stacked capacitor) is greater than a distance between upper portions of the first electrode regions (e.g., the lower portions of the first electrode structure of the stacked capacitor).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming the first electrode structures having a shape of the stacked truncated cones having a lower region with a diameter greater than that of the upper region as taught by Tegen to have the semiconductor device, wherein a distance between the second electrode regions is greater than a distance between upper portions of the first electrode regions, in order to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
Regarding claim 9, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan discloses the semiconductor device, wherein the first layer (512d) (Jhan, Fig. 3, ¶0077-¶0078) covers at least a portion of a side surface of the second electrode region (600a), wherein the first layer (512d) includes: convex portion configured to be convex in a direction perpendicular to an upper surface of the second electrode regions, and a concave portion (e.g., steps on both sides of the concave portion), but does not specifically disclose that the first layer covers at least a portion of an upper surface of the second electrode region, wherein the first layer includes, on the second electrode regions: convex portions; and a concave portion formed by the convex portions extending in a horizontal direction and in contact with each other.
However, Tegen teaches forming a capacitor structure (Tegen, Fig. 7e, ¶0025-¶0044, ¶0065-¶0066), wherein the first layer (50) covers at least a portion of an upper surface of the second electrode region (80), wherein the first layer includes, on the second electrode regions: convex portions (e.g., protruding portions); and a concave portion (e.g., a recess portion) formed by the convex portions (e.g., between the protruding portions) extending in a horizontal direction and in contact with each other, to stabilize the underlying first electrode layer (80).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming the bridge structure including a first insulating layer having a fork shaped structure including protruding portions and the recessed portions as taught by Tegen to have the semiconductor device, wherein the first layer covers at least a portion of an upper surface of the second electrode region, wherein the first layer includes, on the second electrode regions: convex portions; and a concave portion formed by the convex portions extending in a horizontal direction and in contact with each other, in order to stabilize the underlying first electrode layer, and to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
Regarding claim 10, Jhan in view of Tegen discloses the semiconductor device of claim 9. Further, Jhan discloses the semiconductor device, wherein the first layer (512d) (Jhan, Fig. 3, ¶0077-¶0078) has a flat portion having a flat surface between side surfaces of the second electrode regions (600a).
Regarding claim 12, Jhan in view of Tegen discloses the semiconductor device of claim 9. Further, Jhan discloses the semiconductor device, wherein an end of the concave portion (e.g., steps on both sides of the concave portion) (Jhan, Fig. 3, ¶0077-¶0078) is on a level lower than a level of the upper surface of the second electrode regions (600a).
Regarding claim 15, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan discloses the semiconductor device, wherein the first layer (512d) (Jhan, Fig. 2K, ¶0037) includes silicon nitride (SiN) and the second layer (511d) includes silicon carbonitride (e.g., carbon-doped silicon nitride).
With respect to claim 16, Jhan discloses a semiconductor device (e.g., DRAM memory) (Jhan, Fig. 3, ¶0019-¶0040, ¶0077-¶0078), comprising:
a lower structure (e.g., bit line structures 200 and contact structures 300b) (Jhan, Fig. 3, ¶0022-¶0027, ¶0077-¶0078);
a capacitor (600) (Jhan, Fig. 3, ¶0031-¶0033, ¶0039-¶0040) on the lower structure, wherein the capacitor (600) includes first electrode structures (600a), a dielectric layer (600b) covering the first electrode structures (600a), and a second electrode structure (600c) on the dielectric layer (600b); and
an upper support pattern (510d) (Jhan, Fig. 3, ¶0032-¶0038) in contact with the first electrode structures (600a),
wherein each of the first electrode structures (600a) includes:
a first electrode region (e.g., a vertical lower portion of the first electrode 600a extending to the lower support layer 510b) (Jhan, Fig. 3, ¶0031, ¶0037-¶0038) extending vertically; and
a second electrode region (e.g., a vertical upper portion of the first electrode 600a extending to from the lower support layer 510b to the upper support layer 510d) on the first electrode region,
wherein the upper support pattern (510d) includes a first layer (512d) (Jhan, Fig. 3, ¶0031, ¶0077-¶0078) covering side surfaces of the second electrode regions (e.g., the vertical upper portions of the adjacent first electrode 600a) of the first electrode structures (600a) and connected to each other, and
wherein the first layer (512d) (Jhan, Fig. 3, ¶0077-¶0078) has convex portion having a convex upper surface in a vertical direction away from an upper surface of the lower structure (200/300b) and a concave portion (e.g., a step portion) having a concave upper surface.
Further, Jhan does not specifically disclose that the upper support pattern includes: a first layer covering upper surfaces of the second electrode regions of the first electrode structures, and wherein the first layer has convex portions and a concave portion between the convex portions.
However, Tegen teaches forming a capacitor structure (Tegen, Fig. 7e, ¶0025-¶0044, ¶0065-¶0066) comprising the upper support pattern (e.g., bridge 110) (Tegen, Figs. 2a-2b, 7e, ¶0039, ¶0044) that includes a first layer (e.g., insulating layer 50) covering upper surfaces of the second electrode regions (e.g., upper electrode regions) of the first electrode structures (80), wherein the first layer has convex portions (e.g., protruding portions) and a concave portion (e.g., a recess portion) between the convex portions (e.g., between the protruding portions), to stabilize the underlying first electrode layer (80).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan by forming the first layer having a plurality of convex portions and concave portions as taught by Tegen to have the semiconductor device, wherein the upper support pattern includes: a first layer covering upper surfaces of the second electrode regions of the first electrode structures, and wherein the first layer has convex portions and a concave portion between the convex portions, in order to stabilize the underlying first electrode layer, and to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
Regarding claim 18, Jhan in view of Tegen discloses the semiconductor device of claim 16. Further, Jhan does not specifically disclose the semiconductor device, wherein lower surfaces of the second electrode regions have a horizontal width smaller than a width of each of upper surfaces of the first electrode regions, and wherein a horizontal distance between the second electrode regions deceases in a direction away from the lower surfaces of the second electrode regions, the direction perpendicular to the lower surfaces, and wherein the horizontal distance is at least about 10 nm or more.
However, Tegen teaches forming a capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066), wherein, in each of the first electrode structures (e.g., first electrode 80 in the openings 101/101 filled with the fill material 75), a width of a lower region of the second electrode regions (e.g., upper portions of the first electrode structure of the stacked capacitor) (Tegen, Figs. 2a-2b, 7e, ¶0035-¶0038) has a width less than a width of an upper region of the first electrode regions (e.g., a lower portion of the first electrode structure of the stacked capacitor), wherein a width of at least a portion of the second electrode regions increases in a direction away from the first electrode region, wherein the side surfaces of the second electrode regions (e.g., the upper portions of the first electrode structure of the stacked capacitor) are inclined with respect to upper surfaces of the first electrode regions (e.g., the lower portions of the first electrode structure of the stacked capacitor), such that a horizontal distance between the second electrode regions deceases in a direction away from the lower surfaces of the second electrode regions, the direction perpendicular to the lower surfaces, and wherein the diameter (e.g., horizontal distance) of the openings (100/101) including the first electrodes (80) is less than about 80 nm (Tegen, Figs. 2a-2b, 7e, ¶0035).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming the first electrode structures having a shape of the stacked truncated cones having a lower region with a diameter greater than that of the upper region as taught by Tegen, wherein the distance between the first electrodes corresponding to the diameter of the openings to have the semiconductor device, wherein lower surfaces of the second electrode regions have a horizontal width smaller than a width of each of upper surfaces of the first electrode regions, and wherein a horizontal distance between the second electrode regions deceases in a direction away from the lower surfaces of the second electrode regions, the direction perpendicular to the lower surfaces, and wherein the horizontal distance is at least about 10 nm or more, in order to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
With respect to claim 20, Jhan discloses a semiconductor device (e.g., DRAM memory) (Jhan, Fig. 3, ¶0019-¶0040, ¶0077-¶0078), comprising:
a lower structure (e.g., bit line structures 200 and contact structures 300b) (Jhan, Fig. 3, ¶0019, ¶0022-¶0027, ¶0077-¶0078) including conductive regions on a substrate (100);
first electrode structures (600a) (Jhan, Fig. 3, ¶0031-¶0033, ¶0039-¶0040) on a lower structure (200/300b), electrically connected to the conductive region (300b) of the lower structure, and extending in a vertical direction;
support patterns (510b/510d) in contact with the first electrode structures (600a);
a dielectric layer (600b) covering the first electrode structures (600a) and the support patterns (510b/510d); and
a second electrode structure (600c) on the dielectric layer (600b),
wherein each of the first electrode structures (600a) includes a first electrode region (e.g., a vertical lower portion of the first electrode 600a extending to the lower support layer 510b) (Jhan, Fig. 3, ¶0031, ¶0037-¶0038) and a second electrode region (e.g., a vertical upper portion of the first electrode 600a extending to from the lower support layer 510b to the upper support layer 510d) on the first electrode region,
wherein the support patterns (510b/510d) include:
an intermediate support pattern (510b) (Jhan, Fig. 3, ¶0032, ¶0077-¶0078) in contact with side surfaces of upper regions of the first electrode regions of the first electrode structures (600a); and
an upper support pattern (510d) (Jhan, Fig. 3, ¶0032, ¶0077-¶0078) in contact with side surfaces of the second electrode regions of the first electrode structures (600a).
Further, Jhan does not specifically disclose that an upper support pattern in contact with upper surfaces of the second electrode regions of the first electrode structures, and wherein in each of the first electrode structures, a minimum width of the second electrode region is less than a width of an upper region of the first electrode region.
However, Tegen teaches forming a capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066) having a high aspect ratio structures and reduced footprint, wherein the capacitor structure comprises stacked structures having a lower region with a first diameter and an upper region with a second diameter smaller than the first diameter of the lower region, wherein the lower region includes the first electrode (80) on sides of the fill material (75) and the upper region includes first electrode (80) on sides of the fill material (75), and wherein the upper support pattern (e.g., bridge 110) (Tegen, Figs. 2a-2b, 7e, ¶0039, ¶0044) includes: a first layer (e.g., insulating layer 50) covering upper surfaces of the second electrode regions (e.g., upper electrode regions) of the first electrode structures (80), to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan by forming the first electrode structures having a shape of the stacked truncated cones and a bridge structure including an insulating layer on upper portions of the first electrode structures as taught by Tegen to have the semiconductor device, wherein an upper support pattern in contact with upper surfaces of the second electrode regions of the first electrode structures, and wherein in each of the first electrode structures, a minimum width of the second electrode region is less than a width of an upper region of the first electrode region, in order to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139922 to Jhan in view of Tegen (US 2009/0294907) as applied to claim 2 (claim 1), and further in view of Lu et al. (US 2009/0224362, hereinafter Lu).
Regarding claim 4, Jhan in view of Tegen discloses the semiconductor device of claim 2. Further, Jhan does not specifically disclose the semiconductor device, wherein at least a portion of the side surface of the second electrode region has a concave shape in a direction toward a vertical central axis of the second electrode region.
However, Lu teaches forming a capacitor structure (Lu, Figs. 5A-5E, ¶0011, ¶0034-¶0036) including a first electrode structure (e.g., central pillar 120 and exterior pipe 110) having concave-convex surfaces such that a concave shape is formed in the second electrode region in a direction toward a vertical central axis of the first electrode (110/120), to increase capacitor surface area of the first electrode, and thus to obtain a memory capacitor structure with increased capacitance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming a capacitor structure including a first electrode having concave-convex surfaces as taught by Lu to have the semiconductor device, wherein at least a portion of the side surface of the second electrode region has a concave shape in a direction toward a vertical central axis of the second electrode region, in order to increase capacitor surface area of the first electrode, and thus to obtain a memory capacitor structure with increased capacitance (Lu, ¶0011, ¶0034, ¶0039).
Regarding claims 5-6, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan does not specifically disclose the semiconductor device, wherein the second electrode region includes: a lower portion of which a width decreases in a direction away from an upper surface of the first electrode region; and an upper portion of which a width increases in a direction away from the lower portion (as claimed in claim 5); wherein a slope of a side surface of the upper portion of the second electrode region is steeper than a slope of the lower portion of the second electrode region (as claimed in claim 6).
However, Lu teaches forming a capacitor structure (Lu, Figs. 5A-5E, ¶0011, ¶0034-¶0036) including a first electrode structure (e.g., central pillar 120 and exterior pipe 110) having concave-convex surfaces such that a concave shape is formed in the second electrode region in a direction toward a vertical central axis of the first electrode (110/120), to increase capacitor surface area of the first electrode, and thus to obtain a memory capacitor structure with increased capacitance.
Thus, Lu recognizes that the shape of the first electrode structures having concave-convex surfaces impacts capacitor surface area of the first electrode structures. Thus, the shape of the first electrode structures is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the shape of the first electrode structures as Lu has identified the shape of the first electrode structures as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific shape of the first electrode structures such that the second electrode region includes: a lower portion of which a width decreases in a direction away from an upper surface of the first electrode region; and an upper portion of which a width increases in a direction away from the lower portion (as claimed in claim 5); wherein a slope of a side surface of the upper portion of the second electrode region is steeper than a slope of the lower portion of the second electrode region (as claimed in claim 6), in order to increase capacitor surface area of the first electrode, and thus to obtain a memory capacitor structure with increased capacitance as taught by Lu (¶0011, ¶0034, ¶0036) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by optimizing the shape of the first electrode structures having concave-convex surfaces as taught by Lu to have the semiconductor device, wherein the second electrode region includes: a lower portion of which a width decreases in a direction away from an upper surface of the first electrode region; and an upper portion of which a width increases in a direction away from the lower portion (as claimed in claim 5); wherein a slope of a side surface of the upper portion of the second electrode region is steeper than a slope of the lower portion of the second electrode region (as claimed in claim 6), in order to increase capacitor surface area of the first electrode, and thus to obtain a memory capacitor structure with increased capacitance (Lu, ¶0011, ¶0034, ¶0039).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139922 to Jhan in view of Tegen (US 2009/0294907) as applied to claim 1, and further in view of Ding et al. (CN 116887599 A, hereinafter Ding).
Regarding claim 8, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan does not specifically disclose the semiconductor device, wherein a distance between the second electrode regions is about 10nm to about 15nm.
However, Ding teaches forming a capacitor structure comprising first electrode structures (20) (Ding, Fig. 2, Abstract, pp. 3, 6-8) including first electrode regions (21) and second electrode regions (22), wherein a first distance (L1) between the first electrode regions (21) is between 10nm and 20nm, a second distance (L2) between the second electrode regions (22) is L2=L1(0.4-0.8)nm, to provide the capacitor structure with improved structural stability.
Thus, a person of ordinary skill in the art would recognize that for the first distance of 20 nm, a second distance between the second electrode regions would be from about 8nm to about 16 nm. The claimed range lies inside the range of prior art.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming first electrode structures including a distance between the second electrode regions as taught by Ding to have the semiconductor device, wherein a distance between the second electrode regions is about 10nm to about 15nm, in order to provide the capacitor structure with improved structural stability (Ding, Abstract, pp. 3, 6-8).
Regarding claim 18, Jhan in view of Tegen discloses the semiconductor device of claim 16. Further, Jhan does not specifically disclose the semiconductor device, wherein lower surfaces of the second electrode regions have a horizontal width smaller than a width of each of upper surfaces of the first electrode regions, and wherein a horizontal distance between the second electrode regions deceases in a direction away from the lower surfaces of the second electrode regions, the direction perpendicular to the lower surfaces, and wherein the horizontal distance is at least about 10 nm or more.
However, Tegen teaches forming a capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066), wherein, in each of the first electrode structures (e.g., first electrode 80 in the openings 101/101 filled with the fill material 75), a width of a lower region of the second electrode regions (e.g., upper portions of the first electrode structure of the stacked capacitor) (Tegen, Figs. 2a-2b, 7e, ¶0035-¶0038) has a width less than a width of an upper region of the first electrode regions (e.g., a lower portion of the first electrode structure of the stacked capacitor), wherein a width of at least a portion of the second electrode regions increases in a direction away from the first electrode region, wherein the side surfaces of the second electrode regions (e.g., the upper portions of the first electrode structure of the stacked capacitor) are inclined with respect to upper surfaces of the first electrode regions (e.g., the lower portions of the first electrode structure of the stacked capacitor), such that a horizontal distance between the second electrode regions deceases in a direction away from the lower surfaces of the second electrode regions, the direction perpendicular to the lower surfaces.
Further, Ding teaches forming a capacitor structure comprising first electrode structures (20) (Ding, Fig. 2, Abstract, pp. 3, 6-8) including first electrode regions (21) and second electrode regions (22), wherein a first distance (L1) between the first electrode regions (21) is between 10nm and 20nm, a second distance (L2) between the second electrode regions (22) is L2=L1(0.4-0.8)nm, to provide the capacitor structure with improved structural stability.
Thus, a person of ordinary skill in the art would recognize that for the first distance of 20 nm, a horizontal distance between the second electrode regions would be from about 8nm to about 16 nm. The claimed range overlaps the range of prior art.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming the first electrode structures having a shape of the stacked truncated cones having a lower region with a diameter greater than that of the upper region as taught by Tegen, wherein a distance between the second electrode regions as taught by Ding to have the semiconductor device, wherein lower surfaces of the second electrode regions have a horizontal width smaller than a width of each of upper surfaces of the first electrode regions, and wherein a horizontal distance between the second electrode regions deceases in a direction away from the lower surfaces of the second electrode regions, the direction perpendicular to the lower surfaces, and wherein the horizontal distance is at least about 10 nm or more, in order to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry; and to provide the capacitor structure with improved structural stability (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066; Ding, Abstract, pp. 3, 6-8).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139922 to Jhan in view of Tegen (US 2009/0294907) as applied to claim 9, and further in view of Kim et al. (US Patent No. 8,704,283, hereinafter Kim).
Regarding claim 11, Jhan in view of Tegen discloses the semiconductor device of claim 9. Further, Jhan does not specifically disclose that an end of the concave portion is on a level higher than a level of the upper surface of the second electrode regions.
However, Kim teaches forming a capacitor comprising a first electrode structures (340) (Kim, Fig. 10, Col. 1, lines 40-52; Col.9, lines 17-60) having an upper electrode regions in contact with a support layer (365), wherein the support layer (365) (Kim, Fig. 10, Col. 9, lines 25-60) includes a concave (e.g., a step) portion having an end such that an end of the concave portion is on a level higher than a level of the upper surface of the second electrode regions of the first electrode structures (340), to provide improved supporting structure to stably support the first electrode of the capacitor (Kim, Col. 1, lines 40-52; Col.9, lines 17-60).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139922 to Jhan in view of Tegen (US 2009/0294907) as applied to claim 1, and further in view of Lim et al. (US Patent No. 9,171,670, hereinafter Lim).
Regarding claim 13, Jhan in view of Tegen discloses the semiconductor device of claim 1. Further, Jhan discloses the semiconductor device, wherein the first layer (512d) covers at least a portion of side surfaces of the second electrode regions (600a), and wherein the first layer (512d) includes: convex portion configured to be convex in a direction perpendicular to the upper surface of the second electrode regions, but does not specifically disclose that the first layer covers at least a portion of upper surfaces of the second electrode regions, and wherein the first layer includes: convex portions; a first concave portion formed by the convex portions extending in the horizontal direction and in contact with each other; and curved portions between at least portions of side surfaces of the second electrode regions.
However, Tegen teaches forming a capacitor structure (Tegen, Fig. 7e, ¶0025-¶0044, ¶0065-¶0066), wherein the first layer (50) covers at least a portion of an upper surface of the second electrode region (80), wherein the first layer includes, on the second electrode regions: convex portions (e.g., protruding portions); and a concave portion (e.g., a recess portion) formed by the convex portions (e.g., between the protruding portions) extending in a horizontal direction and in contact with each other, to stabilize the underlying first electrode layer (80).
Further, Lim teaches forming a capacitor structure (Lim, Figs. 1A-1C, Col. 1, lines 16-18; Col. 5, lines 43-67; Col. 6, lines 1-50) with increased aspect ratio and including a supporting structure (180) (Lim, Figs. 1A-1C, Col. 5, lines 43-67; Col. 6, lines 1-50) on an upper sidewalls of the first electrode (170) such that the supporting structure (180) has curved portions between at least portions of side surfaces of the second electrode regions of the first electrode (170), to provide the structure that prevent the first electrode from collapsing.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen by forming the bridge structure including a first insulating layer having a fork shaped structure including protruding portions and the recessed portions as taught by Tegen, wherein the supporting structure includes curved surfaces between sidewalls of the second electrode regions as taught by Lim to have the semiconductor device, wherein the first layer covers at least a portion of upper surfaces of the second electrode regions, and wherein the first layer includes: convex portions; a first concave portion formed by the convex portions extending in the horizontal direction and in contact with each other; and curved portions between at least portions of side surfaces of the second electrode regions, in order to stabilize the underlying first electrode layer, and to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry; and to provide a capacitor structure with increased aspect ratio and to prevent the first electrode from collapsing (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066; Lim, Col. 1, lines 16-18; Col. 6, lines 18-21).
Regarding claim 14, Jhan in view of Tegen and Lim discloses the semiconductor device of claim 13. Further, Jhan does not specifically disclose the semiconductor device, wherein each of the curved portions extends in a horizontal direction from at least a portion of side surfaces of the second electrode regions, and wherein the curved portions are in contact with each other and form a second concave portion opposing the first concave portion.
However, Lim teaches forming a capacitor structure (Lim, Figs. 1A-1C, Col. 1, lines 16-18; Col. 5, lines 43-67; Col. 6, lines 1-50) with increased aspect ratio and including a supporting structure (180) (Lim, Figs. 1A-1C, Col. 5, lines 43-67; Col. 6, lines 1-50) on an upper sidewalls of the first electrode (170) such that the supporting structure (180) has curved portions between at least portions of side surfaces of the second electrode regions of the first electrode (170), and each of the curved portions extends in a horizontal direction from at least a portion of side surfaces of the second electrode regions, and wherein the curved portions are in contact with each other and form a concave portion, to provide the structure that prevent the first electrode from collapsing.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan/Tegen/Lim by forming the supporting structure includes curved surfaces between sidewalls of the second electrode regions and forming a concave portion as taught by Lim, wherein the concave portion faces the concave portion of Jhan/Tegen formed on the lower surface of the first layer to have the semiconductor device, wherein each of the curved portions extends in a horizontal direction from at least a portion of side surfaces of the second electrode regions, and wherein the curved portions are in contact with each other and form a second concave portion opposing the first concave portion, in order to stabilize the underlying first electrode layer, and to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry; and to provide a capacitor structure with increased aspect ratio and to prevent the first electrode from collapsing (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066; Lim, Col. 1, lines 16-18; Col. 6, lines 18-21).
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139922 to Jhan in view of Tegen (US 2009/0294907) as applied to claim 16, and further in view of Choi et al. (US 2021/0151439, hereinafter Choi).
Regarding claim 17, Jhan in view of Tegen discloses the semiconductor device of claim 16. Further, Jhan discloses the semiconductor device, wherein the upper support pattern (510d) (Jhan, Fig. 3, ¶0031, ¶0035, ¶0037-¶0038, ¶0077-¶0078) further includes a second layer (511d) on the first layer (512d), but does not specifically disclose that the second layer includes groove portions in contact with the convex portions of the first layer and a protrusion portion between the groove portions and in contact with the concave portion.
However, Tegen teaches forming the capacitor structure (Tegen, Figs. 2a-2b, 7e, ¶0025-¶0044, ¶0065-¶0066) that comprises the upper support pattern (e.g., bridge 110) (Tegen, Figs. 2a-2b, 7e, ¶0039, ¶0044) including a first layer (e.g., insulating layer 50) having convex portions (e.g., protruding portions) and a concave portion (e.g., a recess portion) between the convex portions (e.g., between the protruding portions), to stabilize the underlying first electrode layer (80).
Further, Choi teaches forming a semiconductor memory device (DRAM) (Choi, Fig. 1A-1C, ¶0021-¶0057) comprising a capacitor structure (90) (Choi, Fig. 1A-1C, ¶0036-¶0044) and an upper supporter pattern (85) (Choi, Fig. 1a-1c, ¶0047-¶0048, ¶0057) having a first layer (85a) and a second layer (86a) including a capping layer having a protrusion of a convex shape and covering upper surface and side surfaces of the first layer (85a), to provide better support for the first electrode (91) of the capacitor (90).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Jhan by forming the upper support structure including the first layer having a plurality of convex portions and concave portions as taught by Tegen, wherein the first layer is covered with the support capping layer having convex shape as taught by Choi, and wherein the support capping layer covers surfaces of the convex portions and concave portions of the first layer to have the semiconductor device, wherein the second layer includes groove portions in contact with the convex portions of the first layer and a protrusion portion between the groove portions and in contact with the concave portion, in order to stabilize the underlying first electrode layer, and to provide a better support structure for a stacked capacitor structure having a high aspect ratio and reduced footprint without degrading the capacitance to obtain capacitors amenable to sustain scaling of the semiconductor industry (Tegen, ¶0003, ¶0025-¶0026, ¶0039, ¶0044, ¶0066; Choi, ¶0047-¶0048, ¶0057).
Regarding claim 19, Jhan in view of Tegen and Choi discloses the semiconductor device of claim 17. Further, Jhan discloses the semiconductor device, wherein the first layer (512d, silicon nitride (SiN)) (Jhan, Fig. 2K, ¶0037) and the second layer (511d, carbon-doped silicon nitride include different materials.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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