DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon ‘089 (US 2023/0120089 A1) in view of Han (US 2021/0175253 A1).
Regarding claim 1, Yoon ‘089 teaches a ferroelectric gate stack, comprising:
a semiconductor layer (CHL; see ¶ [0040]: channel layer CHL is made of silicon, which is known in the art as a semiconductor material);
a conductor layer (GL; ¶ [0036]: GL is a conductive layer) facing the semiconductor layer;
a plurality of ferroelectric layers (Figs. 4 and 5 shows multiple FLs) spaced apart from each other between the semiconductor layer and the conductor layer, the plurality of ferroelectric layers including a first ferroelectric layer (kFL; see Fig. 5F) and a second ferroelectric layer ( (k-1)FL );
a tunnel dielectric layer ( (k-1)ITL ) between the first ferroelectric layer and the second ferroelectric layer.
However, Yoon ‘089 does not teach an interface layer between the semiconductor layer and the first ferroelectric layer.
Han, in the same field of invention, teaches a ferroelectric gate stack comprising an interface layer (332; Fig. 7) between the semiconductor layer (322; ¶ [0094]: 322 is a channel layer; ¶ [0052]: made of silicon) and the first ferroelectric layer (312).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Han into the device of Yoon ‘089 to insert an interface layer between the semiconductor layer and the first ferroelectric layer. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the device by preventing defects due to oxygen vacancies at the interface between the first ferroelectric layer and the semiconductor layer (Han ¶ [0095]).
Regarding claim 2, the ferroelectric gate stack of claim 1, wherein
the interface layer includes an oxide (Han ¶ [0095]: silicon oxide) of a material (Yoon ‘089 ¶ [0040]: CHL made of silicon) in the semiconductor layer, and
the plurality of ferroelectric layers are a different material (Yoon ‘089 ¶ [0038]: HZO, PSZ, STB, BFO, HSO) than the interface layer.
Regarding claim 5, the ferroelectric gate stack of claim 1, wherein
the plurality of ferroelectric layers include a third ferroelectric layer (2FL; see Yoon ‘089 Fig. 5D) on the second ferroelectric layer,
the tunnel dielectric layer is a first tunnel dielectric layer ( (k-1)ITL is shown as one of the many ITLs in Fig. 5D) among a plurality of tunnel dielectric layers between the semiconductor layer and the conductor layer, and
the plurality of tunnel dielectric layers include a second tunnel dielectric layer (2ITL) between the second ferroelectric layer and the third ferroelectric layer.
Regarding claim 6, the ferroelectric gate stack of claim 1, wherein
the conductor layer does not surround the semiconductor layer (Yoon ‘089 Fig. 5F shows the top-left conductor layer GL does not completely surround CHL, since there are portions of CHL above and below the said GL),
opposite surfaces (left and right surfaces of (k-1)ITL) of the tunnel dielectric layer directly contact the first ferroelectric layer (kFL) and the second ferroelectric layer ( (k-1)FL ), respectively, and
opposite surfaces (left and right surfaces of interface layer 332; see Han Fig. 7) of the interface layer directly contact the first ferroelectric layer (312) and the semiconductor layer (322), respectively.
Regarding claim 7, the ferroelectric gate stack of claim 1, wherein
the conductor layer surrounds the semiconductor layer (Yoon ‘089 Fig. 3 shows topmost GL surrounding the topmost portion of CHL),
opposite surfaces (left and right surfaces of (k-1)ITL; Fig. 5F) of the tunnel dielectric layer directly contact the first ferroelectric layer (kFL) and the second ferroelectric layer ( (k-1)FL ), respectively, and
opposite surfaces (left and right surfaces of interface layer 332; Han Fig. 7) of the interface layer directly contact the first ferroelectric layer (312) and the semiconductor layer (322), respectively.
Regarding claim 8, the ferroelectric gate stack of claim 1, wherein
the plurality of ferroelectric layers are thicker than the tunnel dielectric layer (Yoon ‘089 Figs. 4A-4E; ¶ [0051]).
Regarding claim 9, the ferroelectric gate stack of claim 1, wherein
the conductor layer (GL; Yoon ‘089 Figs. 4-5) directly contacts one of the plurality of ferroelectric layers (1FL) that is farthest away from the semiconductor layer (CHL) among the plurality of ferroelectric layers (Yoon ‘089 Fig. 5F shows GL directly contacting 1FL)
Regarding claim 18, Yoon ‘089 teaches a ferroelectric gate stack, comprising:
a semiconductor layer (CHL; see ¶ [0040]: channel layer CHL made of silicon, which is known in the art as a semiconductor material);
a conductor layer (GL; ¶ [0036]: GL is a conductive layer) facing the semiconductor layer;
a ferroelectric (FE) stack (DL) between the semiconductor layer and the conductor layer, the FE stack including a plurality of ferroelectric material regions (Figs. 4 and 5 shows multiple FLs) separated from each other by one or more tunnel dielectric regions (ITL) in contact with the plurality of ferroelectric material regions; and
the plurality of ferroelectric material regions (1FL, 2FL, …, kFL; see Fig. 5E) include a ferroelectric material (¶ [0038]: HZO, HSO, PSZ, STB, BFO), and
the one or more tunnel dielectric regions (1ITL, 2ITL, …, (k-1)ITL) include a dielectric material (¶ [0039]: SiO2 ) configured to increase a memory window (¶ [0006], [0042], [0047]-[0048]: improved retention characteristics ) of the ferroelectric gate stack,
the ferroelectric material is different than the dielectric material (see lists of materials above).
Yoon ‘089 further teaches the ferroelectric material to be made of PSZ, STB, FGO, HZO, or HSO (¶ [0041]). However, Yoon ‘089 does not teach the device comprising an interface layer between the semiconductor layer and the FE stack, wherein a material of the interface layer is different than the ferroelectric material, and wherein opposite surfaces of the interface layer are in contact with the semiconductor layer and the FE stack.
Han, in the same field of invention, teaches a ferroelectric gate stack comprising
an interface layer (332; Fig. 7) between the semiconductor layer (322; ¶ [0094], [0052]: 322 is a channel layer made of silicon) and the FE stack (312: Yoon ‘089 in view of Han teaches 312 to be an FE stack),
wherein a material (¶ [0095]: silicon nitride, silicon nitride, silicon oxynitride, aluminum oxide) of the interface layer is different than the ferroelectric material (Yoon ‘089 in view of Han teaches this), and
wherein opposite surfaces (right and left surfaces of 332) of the interface layer are in contact with the semiconductor layer (322) and the FE stack (312).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Han into the device of Yoon ‘089 to add an interface layer between and contacting the semiconductor layer and the FE stack, wherein the material of the interface layer is different than the ferroelectric material. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the device by preventing defects due to oxygen vacancies at the interface between the first ferroelectric layer and the semiconductor layer (Han ¶ [0095]).
Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon ‘089 (US 2023/0120089 A1) in view of Han (US 2021/0175253 A1) as applied to claims 1 and/or 18 above, and further in view of Yoon ‘794 (US 2024/0040794 A1).
Regarding claim 3, Yoon ‘089 et al. teach the ferroelectric gate stack of claim 1, wherein the plurality of ferroelectric layers include hafnium zirconium oxide (Yoon ‘089 ¶ [0038]: HZO ) and further teach the tunnel dielectric layer includes silicon oxide (¶ [0039]). However, Yoon ‘089 et al. do not teach the tunnel dielectric layer includes aluminum oxide.
Yoon ‘794, in the same field of invention, teaches the tunnel dielectric layer (CL) to include either silicon oxide or aluminum oxide (¶ [0078]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yoon ‘794 into the device of Yoon ‘089 et al. to substitute the silicon oxide material of the tunnel dielectric layer with that of aluminum oxide. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of substituting materials for the same purpose as providing electrical insulations between each layer of the plurality of ferroelectric layer (Yoon ‘794 ¶ [0078]), and/or to transform the material of each of the ferroelectric layer to a crystal (Yoon ‘794 ¶ [0040]) for the further purpose of optimizing the threshold voltage of the memory cell (¶ [0005]) thereby requiring the use of an amorphous aluminum oxide layer (¶ [0078]).
Regarding claim 20, Yoon ‘089 et al. teach the ferroelectric gate stack of claim 18, wherein
the plurality of ferroelectric regions include hafnium zirconium oxide (Yoon ‘089 ¶ [0038]: HZO ),
the interface layer includes an oxide (Han ¶ [0095]: silicon oxide) of a material (Yoon ‘089 ¶ [0040]: CHL is made of silicon) in the semiconductor layer.
Yoon ‘089 et al. further teach the one or more tunnel dielectric regions include silicon oxide (¶ [0039]). However, Yoon ‘089 et al. do not teach: the one or more tunnel dielectric regions include aluminum oxide.
Yoon ‘794, in the same field of invention, teaches the tunnel dielectric layer (CL) to include either silicon oxide or aluminum oxide (¶ [0078]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yoon ‘794 into the device of Yoon ‘089 et al. to substitute the silicon oxide material of the tunnel dielectric layer with that of aluminum oxide. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of substituting materials for the same purpose as providing electrical insulations between each layer of the plurality of ferroelectric layer (Yoon ‘794 ¶ [0078]), and/or to transform the material of each of the ferroelectric layer to a crystal (Yoon ‘794 ¶ [0040]) for the further purpose of optimizing the threshold voltage of the memory cell (¶ [0005]) thereby requiring the use of an amorphous aluminum oxide layer (¶ [0078] ).
Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon ‘089 (US 2023/0120089 A1) in view of Han (US 2021/0175253 A1) as applied to claims 1 and/or 18 above, and further in view of Zhao (US 2024/0164107 A1).
Regarding claim 4, Yoon ‘089 et al. teach the ferroelectric gate stack of claim 1 and further teaches the plurality of ferroelectric layers are thicker than the tunnel dielectric layer (Yoon ‘089 Figs. 4A-4E; ¶ [0051]). However, Yoon ‘089 et al. do not explicitly teach wherein the semiconductor layer and the conductor layer are separated from each other by a distance of less than or equal to 20 nm, and the plurality of ferroelectric layers, the tunnel dielectric layer, and the interface layer define a stacked structure having a thickness of less than or equal to 20 nm.
Zhao, in the same field of invention, teaches the semiconductor layer and the conductor layer are separated from each other by a distance of less than or equal to 20 nm (¶ [0086]: thickness of the ferroelectric film can be at least 5 nm; note: Yoon ‘089 teaches the plurality of ferroelectric film to be in between the semiconductor layer and the conductor layer in claim 1 rejection above), and
the plurality of ferroelectric layers, the tunnel dielectric layer, and the interface layer define a stacked structure having a thickness of less than or equal to 20 nm (¶ [0087]: thickness of interface layer 228 can be no more than 3 nm; ¶ [0079]: thickness of ferroelectric material can be scaled to a range of 5nm to 50 nm; also Yoon ‘089 teaches the tunnel dielectric layer to be thinner than the ferroelectric layer, see note above).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the additional teachings of Zhao into the device of Yoon ‘089 et al. to have the thickness of the layers in between the semiconductor layer and the conductor layer to be less than or equal to 20 nm. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using any deposition known in the art for depositing the plurality of ferroelectric layers and interface layer (Zhao ¶ [0086]-[0087]), which results in an optimized thickness of the ferroelectric film and an improved device density and scalability (¶ [0005]), and optimizing the range of the coercive voltage (¶ [0079]). Furthermore, the written disclosure of the instant application has not shown any criticality of the thicknesses of these layers. See also MPEP § 2144.05.
Regarding claim 19, Yoon ‘089 et al. teach the ferroelectric gate stack of claim 18 and further teaches the plurality of ferroelectric layers are thicker than the tunnel dielectric layer (Yoon ‘089 Figs. 4A-4E; ¶ [0051]). However, Yoon ‘089 et al. do not teach a thickness of the FE stack is less than or equal to 20 nm in a direction corresponding to a minimum distance between the semiconductor layer from the conductor layer.
Zhao, in the same field of invention, teaches a thickness of the FE stack is less than or equal to 20 nm (¶ [0086]: thickness of the ferroelectric film can be at least 5 nm) in a direction (Yoon ‘089 in view of Zhao teaches this to be the horizontal direction in Yoon ‘089 Figs.4-5) corresponding to a minimum distance between the semiconductor layer from the conductor layer (Yoon ‘089 Figs. 4-5 shows this to be the distance between semiconductor layer CHL and conductor layer GL).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the additional teachings of Zhao into the device of Yoon ‘089 et al. to set the thickness of the ferroelectric film to be less than or equal to 20 nm. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using any deposition known in the art for depositing the plurality of ferroelectric layers and interface layer (Zhao ¶ [0086]-[0087]), which results in an optimized thickness of the ferroelectric film and an improved device density and scalability (¶ [0005]). Furthermore, the written disclosure of the instant application has not shown any criticality of the thicknesses of these layers. See MPEP § 2144.05.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon ‘089 (US 2023/0120089 A1) in view of Han (US 2021/0175253 A1) as applied to claim 1 above, and further in view of Zhao (US 2024/0164107 A1) and Van Houdt (US 2017/0178698 A1).
Regarding claim 10, Yoon ‘089 et al. teach the ferroelectric gate stack of claim 1 but does not teach the device wherein the plurality of ferroelectric layers each have a thickness of 6 nm to 10 nm.
Zhao, in the same field on invention, teaches the plurality of the ferroelectric layers each have a thickness of 6 nm to 10 nm (¶ [0086]: thickness of the ferroelectric film can be at least 5 nm).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the further teachings of Zhao into the device of Yoon ‘089 et al. to set each individual thickness of the ferroelectric layers from 6 nm to 10 nm. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using any deposition known in the art for depositing the plurality of ferroelectric layers and interface layer (Zhao ¶ [0086]-[0087] ), which results in an optimized thickness of the ferroelectric film and an improved device density and scalability (¶ [0005]), and an optimized coercive voltage range (¶ [0079]). Furthermore, the written disclosure of the instant application has not shown any criticality of the thicknesses of these layers. See MPEP § 2144.05.
However, Yoon ‘089 et al. do not teach a thickness of the tunnel dielectric layer is 0.5 nm to 3.0 nm.
Van Houdt, in the same field of invention, teaches a ferroelectric memory device (¶ [0027]) wherein a thickness (¶[0081]: 2nm or below) of the tunnel dielectric layer (410; ¶ [0081]) is 0.5 nm to 3.0 nm (¶[0081]: 2nm or below ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Van Houdt into the device of Yoon ‘089 et al. to set the thickness of the tunnel dielectric layer to a range of 0.5 nm to 3.0 nm. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of optimizing the refresh rate of the device by varying the thickness of the tunnel dielectric layer (Van Houdt Fig. 12 and ¶ [0078]). Furthermore, the written disclosure of the instant application has not shown any criticality of the thicknesses of these layers. See MPEP § 2144.05.
Claims 11-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2022/0231049 A1) in view of Yoon ‘089 (US 2023/0120089 A1) and Han (US 2021/0175253 A1).
Regarding claim 11, Lin teaches a memory device (Fig. 26), comprising:
a channel (224A);
a source (244; ¶ [0053]) connected to a first end (top end of 224A; see right side of figure) of the channel;
a drain (245; ¶ [0053]) connected to a second end (bottom end of 224A) of the channel;
a conductor layer (220) facing the channel;
a ferroelectric layer (223A).
However, Lin does not teach the memory device wherein
the ferroelectric layer is a plurality of ferroelectric layers spaced apart from each other between the channel and the conductor layer, the plurality of ferroelectric layers including a first ferroelectric layer and a second ferroelectric layer; and the memory device further comprising:
a tunnel dielectric layer between the first ferroelectric layer and the second ferroelectric layer.
Yoon ’089, in the same field of invention, teaches a memory device comprising
a plurality of ferroelectric layers (Figs. 4 and 5 shows multiple FLs) spaced apart from each other between the channel and the conductor layer, the plurality of ferroelectric layers including a first ferroelectric layer (kFL; see Fig. 5F) and a second ferroelectric layer ( (k-1)FL );
a tunnel dielectric layer ( (k-1)ITL ) between the first ferroelectric layer and the second ferroelectric layer.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yoon ‘089 into the device of Lin to configure the ferroelectric layer to be comprised of at least two ferroelectric layers that are separated from each other by a tunnel dielectric layer. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of adding said features to the data storage layer (DL; Yoon ‘089 ¶ [0007]-[0008], [0037]-[0039]) in order to improve the memory retention of the device (¶ [0002], [0005]).
However, Yoon does not teach an interface layer between the channel and the first ferroelectric layer.
Han, in the same field of invention, teaches a ferroelectric gate stack comprising an interface layer (332; Fig. 7) between the channel (322; ¶ [0094]) and the first ferroelectric layer (312).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Han into the device of Lin et al. to add an interface layer between the channel and the first ferroelectric layer. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the device by preventing defects due to oxygen vacancies at the interface between the first ferroelectric layer and the semiconductor layer (Han ¶ [0095]).
Regarding claim 12, the memory device of claim 11, further comprising:
processing circuitry (Lin ¶ [0016]: functional circuits of device 10 control memory device 120) connected to a memory cell (¶ [0014]: memory device 120 is comprised of memory cells) including the plurality of ferroelectric layers (in view of Yoon ‘089, these cells having the plurality of ferroelectric layers), wherein
the processing circuitry is configured to switch a polarization state (Yoon ‘089 ¶ [0040]: polarization in data storage DL) in a corresponding one of the plurality of ferroelectric layers by controlling a program voltage (¶ [0040]: voltage is applied to gate line GL to store data) or an erase voltage applied to the memory cell using the conductor layer.
Regarding claim 16, the memory device of claim 11, wherein
the conductor layer does not surround the channel, or
the conductor layer surrounds the channel (Lin Fig. 26 shows top-most conductor layer 220 horizontally surrounding both left and end ends of channel 224A) and the channel extends through an opening (opening of the top-most horizontal layer of 220) defined in the conductor layer (said opening of conductor layer 220 is filled with dielectric 203; channel 224A extends above and below conductor layer 220 at the same level as dielectric 203).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2022/0231049 A1) in view of Yoon ‘089 (US 2023/0120089 A1) and Han (US 2021/0175253 A1) as applied to claim 12 above, and further in view of Wu (US 2022/0005830 A1) and Zhao (US 2024/0164107 A1).
Regarding claim 13, Lin et al. teach the memory device of claim 12. However, Lin et al. do not teach: the processing circuitry is configured to operate the memory cell with a memory window sufficient for 2-bit operation by controlling a write voltage applied through the conductor layer to the memory cell so a level of the write voltage is sufficient for 2-bit operation.
Wu, in the same field of invention, teaches a memory device wherein the processing circuitry is configured to operate the memory cell with a memory window (¶ [0025]: range of write voltage greater than the threshold voltage) sufficient for 2-bit operation (¶ [0099]) by controlling a write voltage (¶ [0025]) applied through the conductor layer to the memory cell so a level of the write voltage is sufficient for 2-bit operation (¶ [0099], [0029]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Lin et al. to configure the device to have a 2-bit operation. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the power efficiency and storage capacity of the device (Wu ¶ [0029] ).
Lin et al. in view of Wu further teaches the write voltage has to be greater than a threshold voltage (Wu ¶ [0022], [0024]-[0025]). However, Lin et al. in view of Wu do not teach
the memory window sufficient for 2-bit operation is greater than or equal to 3.0 V, and a magnitude of the level of the write voltage sufficient for 2-bit operation is greater than or equal to 7.0 V and less than or equal to 15.0 V.
Zhao, in the same field of invention, teaches a memory window that is greater than or equal to 3.0 V (¶ [0079]: programming voltage Vp can have a magnitude from 3 V to 10 V), and a magnitude of the level of the write voltage is greater than or equal to 7.0 V and less than or equal to 15.0 V (¶ [0079]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the additional teachings of Zhao into the device of Lin et al. in view of Wu to set the memory window for the 2-bit operation to be greater than or equal to 3.0V and to set the write voltage to greater than 7.0 V and less than or equal to 15.0 V. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of optimizing the thickness of the ferroelectric material that leads to a corresponding memory window and write voltage that is sufficient for 2-bit operation and still be able to optimally reduce operation power and energy consumption (Zhao ¶ [0079] ).
Furthermore, the limitation of controlling a write voltage applied through the conductor layer to the memory cell is a recitation of a product-by-process claim. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 14, Lin et al. teach the memory device of claim 12. However, Lin et al. do not teach: the processing circuitry is configured to operate the memory cell with a memory window sufficient for 3-bit operation by controlling a write voltage applied through the conductor layer to the memory cell so a level of the write voltage is sufficient for 3-bit operation.
Wu, in the same field of invention, teaches a memory device wherein the processing circuitry is configured to operate the memory cell with a memory window (¶ [0029]: range of write voltage greater than the threshold voltage) sufficient for 3-bit operation (¶ [0099]) by controlling a write voltage (¶ [0025]) applied through the conductor layer to the memory cell so a level of the write voltage is sufficient for 3-bit operation (¶ [0099], [0029]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Lin et al. to configure the device to have a 3-bit operation. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the power efficiency and storage capacity of the device (Wu ¶ [0029] ).
Lin et al. in view of Wu further teaches the write voltage has to be greater than a threshold voltage (Wu ¶ [0022], [0024]-[0025]). However, Lin et al. in view of Wu do not teach
the memory window sufficient for 3-bit operation is greater than or equal to 6.5 V, and a magnitude of the level of the write voltage sufficient for 3-bit operation is greater than or equal to 12.0 V and less than or equal to 15.0 V.
Zhao, in the same field of invention, teaches memory window sufficient that is greater than or equal to 6.5 V (¶ [0079]: programming voltage Vp can have a magnitude from 3 V to 10 V), and a magnitude of the level of the write voltage is greater than or equal to 12.0 V and less than or equal to 15.0 V (¶ [0079]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the additional teachings of Zhao into the device of Lin et al. in view of Wu to set the memory window for the 3-bit operation to be greater than or equal to 6.5 V and to set the write voltage to greater than 12.0 V and less than or equal to 15.0 V. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of optimizing the thickness of the ferroelectric material that leads to a corresponding memory window and write voltage that is sufficient for 3-bit operation and still be able to optimally reduce operation power and energy consumption (Zhao ¶ [0079] ).
Furthermore, the limitation of controlling a write voltage applied through the conductor layer to the memory cell is a recitation of a product-by-process claim. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2022/0231049 A1) in view of Yoon ‘089 (US 2023/0120089 A1) and Han (US 2021/0175253 A1) as applied to claim 11 above, and further in view of Zhao (US 2024/0164107 A1).
Regarding claim 15, the memory device of claim 11, further comprising:
processing circuitry (Lin ¶ [0016]: functional circuits of device 10 control memory device 120 ) connected to a memory cell (¶ [0014]: memory device 120 is comprised of memory cells) including the plurality of ferroelectric layers (in view of Yoon ‘089, these cells having the plurality of ferroelectric layers), wherein
the processing circuitry is configured to control a memory operation (Lin ¶ [0016]: functional circuits control read / write operations) on the memory cell.
However, Lin et al. does not teach: applying a pulse voltage using the conductor layer to the memory cell and then applying a read voltage to the memory cell using the conductor layer, the pulse voltage is a program pulse voltage or an erase pulse voltage, a sign of the program pulse voltage is opposite a sign of the erase pulse voltage, and a magnitude of the read voltage is less than a magnitude of the program pulse voltage and a less than a magnitude of the erase pulse voltage.
Zhao, in the same field of invention, teaches applying a pulse voltage (¶ [0079]: Vp can be a voltage pulse with a duration of 10 ns to 100 μs) using the conductor layer to the memory cell (Lin in view of Yoon ‘089 and Zhao teaches applying the pulse voltage to the conductor layer) and then applying a read voltage (¶ [0095]) to the memory cell using the conductor layer (in view of Lin in view of Yoon ‘089 and Zhao teaches applying the read voltage to the conductor layer),
the pulse voltage is a program pulse voltage or an erase pulse voltage (¶ [0079] Vp is a programming voltage),
a sign (positive sign of program Vp; see Fig. 3 and ¶ [0091] ) of the program pulse voltage is opposite a sign (negative sign of erase Vp; ¶ [0092]) of the erase pulse voltage, and
a magnitude (¶ [0095] Vread) of the read voltage is less than a magnitude (¶ [0091]: Vp needs to be greater than coercive voltage Vc ) of the program pulse voltage and a less than a magnitude (¶ [0092]: -Vp needs to be greater than negative coercive voltage -Vc ) of the erase pulse voltage (see also ¶ [0079] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zhao into the device of Lin et al. to use the device by applying pulse voltages for programming and erasing operations and for applying read voltage lesser than the program/erase voltage for read operations. The ordinary artisan would understand that these are known device characteristics of ferroelectric memories due to the electric polarization features of the ferroelectric material (Zhao ¶ [0073]-[0079]).
Furthermore, the limitation of applying a pulse voltage for programming and/or erasing and applying a read voltage is a recitation of a product-by-process claim. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 17, Lin et al. teach the memory device of claim 11, wherein
the interface layer includes an oxide (Zhao ¶ [0087]: silicon oxide) of a material (Yoon ‘089 ¶ [0040]: CHL made of silicon) in channel, and
the plurality of ferroelectric layers are a different material (Yoon ‘089 ¶ [0038]: HZO, PSZ, STB, BFO, HSO) than a material (¶ [0039]: SiO2) of the tunnel dielectric layer,
opposite surfaces (right and left surfaces of interface layer 332; see Han Fig. 7) of the interface layer directly contact the channel (322) and the first ferroelectric layer (312), respectively (in view of Han, the interface layer is located in between kFL and CHL as shown in Yoon ‘089 Fig. 5F)
the plurality of ferroelectric layers each are thicker than the tunnel dielectric layer (Yoon ‘089 Figs. 4A-4E; ¶ [0051]), and
a distance (distance between channel 224A and conductor layer 220 is the thickness of the ferroelectric layer 223A; see Lin Fig. 29) between the channel and the conductor layer corresponds to a thickness of a stacked structure consisting of the plurality of ferroelectric layers, the tunnel dielectric layer, and the interface layer (Lin in view of Yoon ‘089 and Zhao teaches said distance to be the combined thicknesses of the plurality of ferroelectric layers, tunnel dielectric layer, and interface layer).
However, Lin et al. do not teach the distance between the channel and the conductor layer is 20 nm or less.
Zhao, in the same field of invention, teaches the semiconductor layer and the conductor layer are separated from each other by a distance of less than or equal to 20 nm (¶ [0086]: thickness of the ferroelectric film can be at least 5 nm; note: Yoon ‘089 in view of Zhao teaches the plurality of ferroelectric film to be in between the semiconductor layer and the conductor layer in claim 1 rejection above).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the additional teachings of Zhao into the device of Lin et al. to have the thickness of the layers in between the semiconductor layer and the conductor layer to be less than or equal to 20 nm. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using any deposition known in the art for depositing the plurality of ferroelectric layers and interface layer (Zhao ¶ [0086]-[0087] ), which results in an optimized thickness of the ferroelectric film and an improved device density and scalability (¶ [0005]). Furthermore, the written disclosure of the instant application has not shown any criticality of the thicknesses of these layers. See also MPEP § 2144.05.
Conclusion
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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