DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 17 and 19-20 are objected to because of the following informalities:
Claim 17 recites “a second direction” which should be replaced with “the second direction”, to avoid antecedent basis issue (because “a second direction” has been previously recited in claim 16).
Claim 19 recites “a second direction” (line 15) which should be replaced with “the second direction”, to avoid antecedent basis issue (because “a second direction” has been previously recited in line 5 of claim 19).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung et al. (hereinafter Sung) in view of Xie et al. (US 2023/0085628, hereinafter Xie).
With respect to claim 1, Sung discloses a semiconductor device, comprising:
a substrate (402/404) (Sung, Figs. 1-2, ¶0051-¶0052);
lower channel layers (412) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate (402/404) and extending in a first direction (e.g., X direction) parallel to the upper surface of the substrate;
upper channel layers (422) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) on the lower channel layers (412), and spaced apart from each other in the vertical direction;
a middle dielectric isolation structure (602) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0061) between an uppermost lower channel layer (412) among the lower channel layers and a lowermost upper channel layer (422) among the upper channel layers;
a lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050) on the lower channel layers (412);
an upper gate structure (HKMG2) (Sung, Figs. 1-2, ¶0046, ¶0050, ¶0080) on the upper channel layers (422) and that extends in a second direction (Y direction) perpendicular to the first direction (X direction);
a gate isolation insulating layer (spacer 902) (Sung, Figs. 1-2, ¶0046, ¶0064), in contact with a side surface of the middle dielectric isolation structure (602) on the lower gate structure, and on at least a portion of the lower gate structure (HKMG1);
a lower source/drain region (1010) (Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) on at least one side of the lower gate structure (HKMG1) and electrically connected to the lower channel layers 412);
an upper source/drain region (1012) Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) electrically connected to each of the upper channel layers (422) on at least one side of the upper gate structure (HKMG2) and spaced apart from the lower source/drain region (1010) in the vertical direction; and
a barrier structure (602A) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0065) between the lower source/drain region (1010) and the upper source/drain region (1012).
Further, Sung does not specifically disclose a gate isolation insulating layer between the lower gate structure and the upper gate structure.
However, Xie teaches forming stacked gate-all-around (GAA) nanosheets FETs (Xie, Figs. 19A-19C, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0043-¶0092, ¶0094-¶0105) comprising the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103) and the upper gate structure (144/149) each having a gate extension (147/149) including a base portion (151/155) and a side portion (153/157), such that a gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) is between the lower gate structure (144/147) and the upper gate structure (144/149), in contact with a side surface of the middle dielectric isolation structure (126) on the lower gate structure (144/147), and on at least a portion of the lower gate structure (144/147), wherein the matching orientation between the lower base portion (151) and the upper base portion (155) facilitate formation of the common gate contact (182) to establish connection between the gates of the lower stack (115) and the upper stack (113), to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming the lower gate structure and the upper gate structure each having a gate extension isolated with a gate isolation insulating layer as taught by Xie to have the semiconductor device, comprising: a gate isolation insulating layer between the lower gate structure and the upper gate structure, in order to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
Regarding claim 15, Sung in view of Xie discloses the semiconductor device of claim 1. Further, Sung discloses the semiconductor device, wherein the gate isolation insulating layer (e.g., spacer 902 has a liner shape) (Sung, Figs. 1-2, ¶0046, ¶0064) has a liner shape.
Claims 2-5, 7-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) as applied to claim 1, and further in view of Song et al. (US 2022/0254781, hereinafter Song).
Regarding claims 2 and 4, Sung in view of Xie discloses the semiconductor device of claim 1. Further, Sung discloses the semiconductor device, wherein the lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050) comprises: a lower gate electrode extending around the lower channel layers (412) and extending in the second direction (e.g., the Y direction), but does not specifically disclose a first lower gate electrode layer on a side surface and a lower surface of the lower gate electrode; and a second lower gate electrode layer on a side surface and a lower surface of the first lower gate electrode layer (as claimed in claim 2); wherein the lower gate electrode, the first lower gate electrode layer, and the second lower gate electrode layer include different materials (as claimed in claim 4).
However, Song teaches forming a semiconductor device (Song, Figs. 3A-3B, ¶0004-¶0005, ¶0024, ¶0083-¶0099) comprising a plurality of stacked channel layers (SP1-SP3), and a gate electrode including a first lower gate electrode layer (MP2) on a side surface and a lower surface of the lower gate electrode (IGE/MP1); and a second lower gate electrode layer (FMP) on a side surface and a lower surface of the first lower gate electrode layer (MP2), wherein the lower gate electrode (IGE/MP1), the first lower gate electrode layer (MP2), and the second lower gate electrode layer (FMP) include different materials, to adjust the threshold voltage of the transistor, and to provide a semiconductor device with improved electrical characteristics (Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie by forming the lower gate structure including a plurality of layers as taught by Song to have the semiconductor device, wherein a first lower gate electrode layer on a side surface and a lower surface of the lower gate electrode; and a second lower gate electrode layer on a side surface and a lower surface of the first lower gate electrode layer (as claimed in claim 2); wherein the lower gate electrode, the first lower gate electrode layer, and the second lower gate electrode layer include different materials (as claimed in claim 4), in order to adjust the threshold voltage of the transistor, and to provide a semiconductor device with improved electrical characteristics (Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
Regarding claim 3, Sung in view of Xie and Song discloses the semiconductor device of claim 2. Further, Sung discloses the semiconductor device, wherein the gate isolation insulating layer (902) extends along a side surface of the lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050), but does not specifically disclose that the gate isolation insulating layer extends on an upper surface of the lower gate structure, and is in contact with at least a portion of a lower surface of the second lower gate electrode layer.
However, Xie teaches that the gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) extends on an upper surface of the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103), and is in contact with at least a portion of a lower surface of the lower gate extension (147) including a base portion (151).
Further, Song teaches forming the lower gate electrode structure (Song, Figs. 3A-3B, ¶0083-¶0099) including the second lower gate electrode layer (FMP), to provide a semiconductor device with improved electrical characteristics (Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Song by forming the lower gate structure and the upper gate structure each having a gate extension isolated with a gate isolation insulating layer as taught by Xie, wherein the gate extension of the lower gate structure comprises a plurality of layers including the second lower gate electrode layer as taught by Song to have the semiconductor device, wherein the gate isolation insulating layer extends on an upper surface of the lower gate structure, and is in contact with at least a portion of a lower surface of the second lower gate electrode layer, in order to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures; and to adjust the threshold voltage of the transistor, and to provide a semiconductor device with improved electrical characteristics (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105; Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
Regarding claim 5, Sung in view of Xie discloses the semiconductor device of claim 1. Further, Sung discloses the semiconductor device, wherein the lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050) comprises: a lower gate electrode extending around the lower channel layers (412), and wherein the lower gate electrode is in contact with the gate isolation insulating layer (902), but does not specifically disclose a first lower gate electrode layer on a side surface and a lower surface of the lower gate electrode; and a second lower gate electrode layer on a side surface and a lower surface of the first lower gate electrode layer, and the first lower gate electrode layer is in contact with the gate isolation insulating layer.
However, Song teaches forming a semiconductor device (Song, Figs. 3A-3B, ¶0004-¶0005, ¶0024, ¶0083-¶0099) comprising a plurality of stacked channel layers (SP1-SP3), and a gate electrode including a first lower gate electrode layer (MP2) on a side surface and a lower surface of the lower gate electrode (IGE/MP1); and a second lower gate electrode layer (FMP) on a side surface and a lower surface of the first lower gate electrode layer (MP2), wherein the lower gate electrode (IGE/MP1), the first lower gate electrode layer (MP2), and the second lower gate electrode layer (FMP) include different materials, to adjust the threshold voltage of the transistor, and to provide a semiconductor device with improved electrical characteristics (Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
Further, Xie teaches that the gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) extends on an upper surface of the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103), and is in contact with at least a portion of a lower surface of the lower gate extension (147) including a base portion (151).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie by forming the lower gate structure comprises a plurality of layers including a first lower gate electrode layer and a second lower gate electrode layer as taught by Song, wherein the lower gate structure has a gate extension in contact with the gate isolation insulating layer as taught by Xie to have the semiconductor device, wherein a first lower gate electrode layer on a side surface and a lower surface of the lower gate electrode; and a second lower gate electrode layer on a side surface and a lower surface of the first lower gate electrode layer, and the first lower gate electrode layer is in contact with the gate isolation insulating layer, in order to adjust the threshold voltage of the transistor, and to provide a semiconductor device with improved electrical characteristics; and to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099; Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
Regarding claim 7, Sung in view of Xie and Song discloses the semiconductor device of claim 5. Further, Sung discloses the semiconductor device, wherein, in the cross-sectional view (Sung, Fig. 2) in the second direction (Y direction), the gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) is in contact with a side surface of the middle dielectric isolation structure (602) on an upper surface of the lower gate structure (HKMG1), wherein the gate isolation insulating layer (902) extends along a side surface of the lower gate structure (HKMG1), but does not specifically disclose that the gate isolation insulating layer extends along a side surface of the second lower gate electrode layer, and wherein, in a lower portion of the lower gate structure, the gate isolation insulating layer is on a side surface of the lower gate electrode and is on a side surface of the first lower gate electrode layer.
However, Xie teaches that the gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) extends on an upper surface of the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103), and a side surface of the lower gate extension (147) including a side portion (153).
Further, Song teaches forming the lower gate electrode structure (Song, Figs. 3A-3B, ¶0083-¶0099) including the second lower gate electrode layer (FMP) on a side of the first lower gate electrode layer (MP2), and on a side of the lower gate electrode (MP1), to provide a semiconductor device with improved electrical characteristics (Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Song by forming the lower gate structure and the upper gate structure each having a gate extension isolated with a gate isolation insulating layer as taught by Xie, wherein the gate extension of the lower gate structure comprises a plurality of layers including the second lower gate electrode layer on a side of the first lower gate electrode layer and on a side of the lower gate electrode as taught by Song to have the semiconductor device, wherein the gate isolation insulating layer extends along a side surface of the second lower gate electrode layer, and wherein, in a lower portion of the lower gate structure, the gate isolation insulating layer is on a side surface of the lower gate electrode and is on a side surface of the first lower gate electrode layer, in order to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures; and to adjust the threshold voltage of the transistor, and to provide a semiconductor device with improved electrical characteristics (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105; Song, ¶0004-¶0005, ¶0024, ¶0086, ¶0090, ¶0094, ¶0099).
Regarding claim 8, Sung in view of Xie and Song discloses the semiconductor device of claim 7. Further, Sung discloses the semiconductor device, wherein the gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) extends perpendicularly towards the upper surface of the substrate (402/404) along a side surface of the lower gate structure (HKMG1).
Regarding claim 10, Sung in view of Xie and Song discloses the semiconductor device of claim 7. Further, Sung discloses the semiconductor device, wherein a lower surface of the gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) and a lowermost end of the lower gate electrode (HKMG1) are substantially a same distance from the substrate (402/404).
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) and Song (US 2022/0254781) as applied to claim 5 (claim 7), and further in view of Reboh et al. (US 2015/0040240, hereinafter Reboh).
Regarding claim 6, Sung in view of Xie and Song discloses the semiconductor device of claim 5. Further, Sung does not specifically disclose the semiconductor device, wherein a lowermost end of the lower gate structure and a lowermost end of the upper gate structure are substantially on the same level.
However, Reboh teaches forming a semiconductor device (Reboh, Figs. 1-3, ¶0004-¶0005, ¶0024-¶0042) comprising stacked FET transistors including vertically stacked nanosheet channel regions, and middle dielectric isolation structures (e.g., mid dielectric layers 20) (Reboh, Figs. 1-3, ¶0024, ¶0028, ¶0031) extending in a first direction (X direction) between the lower structure (15) and the upper structure (10), and a first gate structure (45) surrounding the channel layers of the lower structure (15), and a second gate structure (45) surrounding the channel layers of the upper structure (10), and extending on a side of the first gate structure (45) surrounding the channel layers of the lower structure (15), such that a lowermost end of the lower gate structure and a lowermost end of the upper gate structure are substantially on the same level, to provide improved semiconductor device having critical dimensions and independent control to the channel layers of the stacked transistor devices (Reboh, ¶0001-¶0005, ¶0024, ¶0028, ¶0042).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Song by forming a gate structure surrounding channels of a plurality of stacked FET transistors as taught by Reboh to have the semiconductor device, wherein a lowermost end of the lower gate structure and a lowermost end of the upper gate structure are substantially on the same level, in order to provide improved semiconductor device having critical dimensions and independent control to the channel layers of the stacked transistor devices (Reboh, ¶0001-¶0005, ¶0024, ¶0028, ¶0042).
Regarding claim 9, Sung in view of Xie and Song discloses the semiconductor device of claim 7. Further, Sung does not specifically disclose the semiconductor device, wherein the gate isolation insulating layer extends diagonally along a side surface of the lower gate structure with respect to the upper surface of the substrate.
However, Reboh teaches forming a semiconductor device (Reboh, Figs. 1-3, ¶0004-¶0005, ¶0024-¶0042) comprising stacked FET transistors including vertically stacked nanosheet channel regions, and the gate isolation insulating layer (24/29/34/39) (Reboh, Figs. 1-3, ¶0032, ¶0039-¶0040) has a tapered shape and extends diagonally along a side surface of the lower gate structure (e.g., gate structure 45 surrounding the lower channel layers 15) with respect to the upper surface of the substrate (1) (Reboh, Figs. 1-3, ¶0081), to provide improved semiconductor device having critical dimensions and independent control to the channel layers of the stacked transistor devices (Reboh, ¶0001-¶0005, ¶0024, ¶0032, ¶0040, ¶0042).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Song by forming the gate isolation insulating layer as gate cut structures having a tapered shape as taught by Reboh to have the semiconductor device, wherein the gate isolation insulating layer extends diagonally along a side surface of the lower gate structure with respect to the upper surface of the substrate, in order to provide improved semiconductor device having critical dimensions and independent control to the channel layers of the stacked transistor devices (Reboh, ¶0001-¶0005, ¶0024, ¶0032, ¶0040, ¶0042).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) and Song (US 2022/0254781) as applied to claim 7, and further in view of Chung et al. (US 2024/0429299, hereinafter Chung).
Regarding claim 11, Sung in view of Xie and Song discloses the semiconductor device of claim 7. Further, Sung does not specifically disclose the semiconductor device, wherein an upper surface of the lower gate structure is between an upper surface of the middle dielectric isolation structure and a lower surface of the middle dielectric isolation structure.
However, Chung teaches forming stacked FET transistors (Chung, Figs. 44-46, ¶0001, ¶0011-¶0094) including a lower gate structure (5221) (Chung, Figs. 44-46, ¶0071, ¶0093) and the upper gate structure (5222), and a middle dielectric isolation structure (127) between the lower gate structure (5221) and the upper gate structure (5222), wherein an upper surface of the lower gate structure (5221) is between an upper surface of the middle dielectric isolation structure (127) and a lower surface of the middle dielectric isolation structure, to provide improved isolation structure for an integrated circuit having higher transistor density and integration (Chung, ¶0001, ¶0011, ¶0071, ¶0093).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Song by forming the lower gate structure and the upper gate structure isolated with a middle dielectric isolation structure as taught by Chung to have the semiconductor device, wherein an upper surface of the lower gate structure is between an upper surface of the middle dielectric isolation structure and a lower surface of the middle dielectric isolation structure, in order to provide improved isolation structure for an integrated circuit having higher transistor density and integration (Chung, ¶0001, ¶0011, ¶0071, ¶0093).
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) as applied to claim 1, and further in view of Chung (US 2024/0429299).
Regarding claim 12, Sung in view of Xie discloses the semiconductor device of claim 1. Further, Sung does not specifically disclose the semiconductor device, wherein an upper surface of the lower gate structure is between an upper surface of the middle dielectric isolation structure and a lower surface of the middle dielectric isolation structure.
However, Chung teaches forming stacked FET transistors (Chung, Figs. 44-46, ¶0001, ¶0011-¶0094) including a lower gate structure (5221) (Chung, Figs. 44-46, ¶0071, ¶0093) and the upper gate structure (5222), and a middle dielectric isolation structure (127) between the lower gate structure (5221) and the upper gate structure (5222), wherein an upper surface of the lower gate structure (5221) is between an upper surface of the middle dielectric isolation structure (127) and a lower surface of the middle dielectric isolation structure, to provide improved isolation structure for an integrated circuit having higher transistor density and integration (Chung, ¶0001, ¶0011, ¶0071, ¶0093).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie by forming the lower gate structure and the upper gate structure isolated with a middle dielectric isolation structure as taught by Chung to have the semiconductor device, wherein an upper surface of the lower gate structure is between an upper surface of the middle dielectric isolation structure and a lower surface of the middle dielectric isolation structure, in order to provide improved isolation structure for an integrated circuit having higher transistor density and integration (Chung, ¶0001, ¶0011, ¶0071, ¶0093).
Regarding claim 14, Sung in view of Xie discloses the semiconductor device of claim 1. Further, Sung does not specifically disclose the semiconductor device, wherein the gate isolation insulating layer has a thickness of 5 nm to 15 nm.
However, Chung teaches forming stacked FET transistors (Chung, Figs. 44-46, ¶0001, ¶0011-¶0094) including a lower gate structure (5221) (Chung, Figs. 44-46, ¶0071, ¶0093) and the upper gate structure (5222), and a middle dielectric isolation structure (127) between the lower gate structure (5221) and the upper gate structure (5222), and the gate isolation insulating layer (440) on both sides of the middle dielectric isolation structure (127), and a thickness of the gate isolation insulating layer is about a thickness of the channel layer (121/122) which between 3 and 8 nm (Chung, Figs. 44-46, ¶0020), to provide improved isolation structure for an integrated circuit having higher transistor density and integration (Chung, ¶0001, ¶0011, ¶0071, ¶0093). The claimed range overlaps the range of Chung.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie by forming the lower gate structure and the upper gate structure isolated with a middle dielectric isolation structure and the gate isolation insulating layer having a specific thickness as taught by Chung to have the semiconductor device, wherein the gate isolation insulating layer has a thickness of 5 nm to 15 nm, in order to provide improved isolation structure for an integrated circuit having higher transistor density and integration (Chung, ¶0001, ¶0011, ¶0020, ¶0071, ¶0093).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) as applied to claim 1, and further in view of Smith et al. (US 2019/0172828, hereinafter Smith).
Regarding claim 13, Sung in view of Xie discloses the semiconductor device of claim 1. Further, Sung does not specifically disclose the semiconductor device, wherein an upper surface of the lower gate structure has a curved portion, and wherein at least a portion of the gate isolation insulating layer extends into the curved portion.
However, Smith teaches forming stacked FET transistors (Smith, Fig. 4, ¶0004, ¶0024-¶0071) including a lower gate structure (32) (Smith, Fig. 4, ¶0054, ¶0068-¶0070), an upper gate structure (34), and a gate isolation insulating layer (1410) (Smith, Fig. 4, ¶0054, ¶0073) between the lower gate structure (32) and the upper gate structure (34), wherein an upper surface of the lower gate structure (32) has a curved portion, and wherein at least a portion of the gate isolation insulating layer (1410) extends into the curved portion, to enhance the method of forming the stacked gates and to provide improved semiconductor device with increased density of the semiconductor devices (Smith, ¶0003, ¶0004, ¶0054, ¶0068-¶0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie by forming the stacked gates of the stacked FET transistors as taught by Smith to have the semiconductor device, wherein an upper surface of the lower gate structure has a curved portion, and wherein at least a portion of the gate isolation insulating layer extends into the curved portion, in order to enhance the method of forming the stacked gates and to provide improved semiconductor device with increased density of the semiconductor devices (Smith, ¶0003, ¶0004, ¶0054, ¶0068-¶0070).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) and Ho et al. (US 2024/0290864, hereinafter Ho).
With respect to claim 16, Sung discloses a semiconductor device, comprising:
a substrate (402/404) (Sung, Figs. 1-2, ¶0051-¶0052);
first lower channel layers (412) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate (402/404) and extending in a first direction (e.g., X direction) parallel to the upper surface of the substrate;
first upper channel layers (422) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) on the first lower channel layers (412), and spaced apart from each other in the vertical direction;
a first middle dielectric isolation structure (602) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0061) between an uppermost lower channel layer (412) among the first lower channel layers and a lowermost upper channel layer (422) among the first upper channel layers;
a first lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050) including a lower gate electrode on the first lower channel layers (412);
a first upper gate structure (HKMG2) (Sung, Figs. 1-2, ¶0046, ¶0050, ¶0080) on the first upper channel layers (422) and that extends in a second direction (Y direction) perpendicular to the first direction (X direction);
a first lower gate isolation insulating layer (spacer 902) (Sung, Figs. 1-2, ¶0046, ¶0064);
a lower source/drain region (1010) (Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) on at least one side of the first lower gate structure (HKMG1) and electrically connected to the first lower channel layers 412), respectively;
an upper source/drain region (1012) Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) electrically connected to each of the first upper channel layers (422) on at least one side of the first upper gate structure (HKMG2) and spaced apart from the lower source/drain region (1010) in the vertical direction;
a barrier structure (602A) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0065) between the lower source/drain region (1010) and the upper source/drain region (1012).,
wherein the first lower gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064)is in contact with a side surface of the first middle dielectric isolation structure (602), and
wherein the first lower gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) extends along a side surface of the first lower gate structure (HKMG1).
Further, Sung does not specifically disclose (1) a first lower gate isolation insulating layer between the first lower gate structure and the first upper gate structure; (2) a lower gate contact structure below the first lower gate structure and electrically connected to the lower gate electrode of the first lower gate structure; and a lower interconnection below the lower gate contact structure and electrically connected to the lower gate contact structure.
Regarding (1), Xie teaches forming stacked gate-all-around (GAA) nanosheets FETs (Xie, Figs. 19A-19C, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0043-¶0092, ¶0094-¶0105) comprising the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103) and the upper gate structure (144/149) each having a gate extension (147/149) including a base portion (151/155) and a side portion (153/157), such that a gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) is between the lower gate structure (144/147) and the upper gate structure (144/149), in contact with a side surface of the middle dielectric isolation structure (126) on the lower gate structure (144/147), and on at least a portion of the lower gate structure (144/147), wherein the matching orientation between the lower base portion (151) and the upper base portion (155) facilitate formation of the common gate contact (182) to establish connection between the gates of the lower stack (115) and the upper stack (113), to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming the lower gate structure and the upper gate structure each having a gate extension isolated with a gate isolation insulating layer as taught by Xie to have the semiconductor device, comprising: a first lower gate isolation insulating layer between the first lower gate structure and the first upper gate structure, in order to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
Regarding (2), Ho teaches forming stacked gate-all-around (GAA) nanosheets FETs (Ho, Fig. 16A, ¶0010, ¶0013-¶0015, ¶0047-¶0059, ¶0065-¶0068) comprising a lower gate contact structure (108) below the first lower gate structure (80U) and electrically connected to the lower gate electrode of the first lower gate structure; and a lower interconnection (114) (Ho, Fig. 16A, ¶0056-¶0057) below the lower gate contact structure (108) and electrically connected to the lower gate contact structure (108), to provide staked transistors with improved routine flexibility, process integration, and device performance (Ho, ¶0011, ¶0013, ¶0015, ¶0056-¶0059).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming the lower gate contact structure connected to the lower interconnect as taught by Ho to have the semiconductor device, comprising: a lower gate contact structure below the first lower gate structure and electrically connected to the lower gate electrode of the first lower gate structure; and a lower interconnection below the lower gate contact structure and electrically connected to the lower gate contact structure, in order to provide staked transistors with improved routine flexibility, process integration, and device performance (Ho, ¶0011, ¶0013, ¶0015, ¶0056-¶0059).
Regarding claim 18, Sung in view of Xie and Ho discloses the semiconductor device of claim 16. Further, Sung does not specifically disclose that the first lower gate structure is configured to exchange input/output signals through the lower interconnection.
However, Ho teaches that the first lower gate structure (80U) (Ho, Fig. 16A, ¶0056-¶0057) is electrically connected to the lower interconnect (114) to provide input to the gate electrode (80).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Ho by forming the lower gate contact structure connected to the lower interconnect as taught by Ho to have the semiconductor device, wherein the first lower gate structure is configured to exchange input/output signals through the lower interconnection, in order to provide staked transistors with improved routine flexibility, process integration, and device performance (Ho, ¶0011, ¶0013, ¶0015, ¶0056-¶0059).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Xie (US 2023/0085628) and Chiu et al. (US 2025/0071964, hereinafter Chiu).
With respect to claim 16, Sung discloses a semiconductor device, comprising:
a substrate (402/404) (Sung, Figs. 1-2, ¶0051-¶0052);
first lower channel layers (412) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate (402/404) and extending in a first direction (e.g., X direction) parallel to the upper surface of the substrate;
first upper channel layers (422) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) on the first lower channel layers (412), and spaced apart from each other in the vertical direction;
a first middle dielectric isolation structure (602) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0061) between an uppermost lower channel layer (412) among the first lower channel layers and a lowermost upper channel layer (422) among the first upper channel layers;
a first lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050) including a lower gate electrode on the first lower channel layers (412);
a first upper gate structure (HKMG2) (Sung, Figs. 1-2, ¶0046, ¶0050, ¶0080) on the first upper channel layers (422) and that extends in a second direction (Y direction) perpendicular to the first direction (X direction);
a first lower gate isolation insulating layer (spacer 902) (Sung, Figs. 1-2, ¶0046, ¶0064);
a lower source/drain region (1010) (Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) on at least one side of the first lower gate structure (HKMG1) and electrically connected to the first lower channel layers 412), respectively;
an upper source/drain region (1012) Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) electrically connected to each of the first upper channel layers (422) on at least one side of the first upper gate structure (HKMG2) and spaced apart from the lower source/drain region (1010) in the vertical direction;
a barrier structure (602A) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0065) between the lower source/drain region (1010) and the upper source/drain region (1012).,
wherein the first lower gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064)is in contact with a side surface of the first middle dielectric isolation structure (602), and
wherein the first lower gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) extends along a side surface of the first lower gate structure (HKMG1).
Further, Sung does not specifically disclose (1) a first lower gate isolation insulating layer between the first lower gate structure and the first upper gate structure; (2) a lower gate contact structure below the first lower gate structure and electrically connected to the lower gate electrode of the first lower gate structure; and a lower interconnection below the lower gate contact structure and electrically connected to the lower gate contact structure.
Regarding (1), Xie teaches forming stacked gate-all-around (GAA) nanosheets FETs (Xie, Figs. 19A-19C, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0043-¶0092, ¶0094-¶0105) comprising the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103) and the upper gate structure (144/149) each having a gate extension (147/149) including a base portion (151/155) and a side portion (153/157), such that a gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) is between the lower gate structure (144/147) and the upper gate structure (144/149), in contact with a side surface of the middle dielectric isolation structure (126) on the lower gate structure (144/147), and on at least a portion of the lower gate structure (144/147), wherein the matching orientation between the lower base portion (151) and the upper base portion (155) facilitate formation of the common gate contact (182) to establish connection between the gates of the lower stack (115) and the upper stack (113), to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming the lower gate structure and the upper gate structure each having a gate extension isolated with a gate isolation insulating layer as taught by Xie to have the semiconductor device, comprising: a first lower gate isolation insulating layer between the first lower gate structure and the first upper gate structure, in order to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
Regarding (2), Chiu teaches forming stacked gate-all-around (GAA) nanostructure-FETs (Chiu, Fig. 12A, ¶0014-¶0102) comprising a lower gate contact structure (196) (Chiu, Fig. 12A, ¶0096) below the lower gate structure (134L) and electrically connected to the lower gate electrode of the lower gate structure; and a lower interconnection (200) (Chiu, Fig. 12A, ¶0099-¶0102) below the lower gate contact structure (196) and electrically connected to the lower gate contact structure (196), to efficiently provide power delivery to the staked transistors (Chiu, ¶0014, ¶0102).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming the lower gate contact structure connected to the lower gate electrode and the lower interconnect as taught by Chiu to have the semiconductor device, comprising: a lower gate contact structure below the first lower gate structure and electrically connected to the lower gate electrode of the first lower gate structure; and a lower interconnection below the lower gate contact structure and electrically connected to the lower gate contact structure, in order to efficiently provide power delivery to the staked transistors (Chiu, ¶0014, ¶0102).
Regarding claim 17, Sung in view of Xie and Chiu discloses the semiconductor device of claim 16. Further, Sung discloses the semiconductor device, further comprising: second lower channel layers (e.g., 412, under the second gate of Fig. 1) (Sung, Figs. 1-2, ¶0045, ¶0046) spaced apart from each other in the vertical direction, electrically connected to the lower source/drain region (1010), and adjacent to the first lower channel layers (e.g., 412, under the first gate of Fig. 1) in the first direction; second upper channel layers (e.g., 422, under the second gate of Fig. 1) on the second lower channel layers (e.g., 412, under the second gate of Fig. 1), spaced apart from each other in the vertical direction, electrically connected to the upper source/drain region (1012), and adjacent to the first upper channel layers (e.g., 422, under the first gate of Fig. 1) in the first direction; a second middle dielectric isolation structure (602) between an uppermost lower channel layer among the second lower channel layers and a lowermost upper channel layer among the second upper channel layers; a second lower gate structure (HKMG1, of the second gate of Fig. 1) extending around the second lower channel layers (e.g., 412, under the second gate of Fig. 1); a second upper gate structure (HKMG2, of the second gate of Fig. 1) including an upper gate electrode extending around the second upper channel layers (e.g., 422, under the second gate of Fig. 1) on the second lower gate structure and extending in a second direction perpendicular to the first direction; a second gate isolation insulating layer (902) between the second lower gate structure and the second upper gate structure, but does not specifically disclose an upper gate contact structure on the second upper gate structure and electrically connected to the upper gate electrode of the second upper gate structure; and an upper interconnection on the upper gate contact structure and electrically connected to the upper gate contact structure, wherein the upper interconnection is electrically connected to the lower interconnection.
However, Chiu teaches stacked FETs comprising an upper gate contact structure (156) (Chiu, Fig. 12A, ¶0080, ¶0082) on the second upper gate structure (134U) and electrically connected to the upper gate electrode of the second upper gate structure; and an upper interconnection (170) on the upper gate contact structure (156) and electrically connected to the upper gate contact structure.
Further, Chiu teaches forming cross-coupling contacts (Chiu, Fig. 14A, ¶0014, ¶0115-¶0117) to interconnect nanostructured-FETs, to decrease interconnect complexity, and increase the device scaling.
Specifically, Chiu teaches a cross-coupling contact (208A) (Chiu, Fig. 14A, ¶0114, ¶0115) connected to the common source/drain contact (184A) that is connected to the lower source/drain region (108L2) and the upper source/drain region (108U2) such that the lower interconnect (200) is connected to the upper interconnect (170) though the channel (66U) and the source/drain contact (158R) of the first upper FET, wherein the upper interconnection (170) is electrically connected to the lower interconnection (200).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Chiu by forming the upper gate contact structure connected to the upper interconnect, and cross-coupling contacts connected to the gate and the source/drain of adjacent transistors as taught by Chiu to have the semiconductor device, wherein an upper gate contact structure on the second upper gate structure and electrically connected to the upper gate electrode of the second upper gate structure; and an upper interconnection on the upper gate contact structure and electrically connected to the upper gate contact structure, wherein the upper interconnection is electrically connected to the lower interconnection, in order to efficiently provide power delivery to the staked transistors; to decrease interconnect complexity, and increase the device scaling (Chiu, ¶0014, ¶0102, ¶0115-¶0117).
Regarding claim 18, Sung in view of Xie and Chiu discloses the semiconductor device of claim 16. Further, Sung does not specifically disclose that the first lower gate structure is configured to exchange input/output signals through the lower interconnection.
However, Chiu teaches forming the lower gate contact structure (196) (Chiu, Fig. 12A, ¶0096) below the lower gate structure (134L) and electrically connected to the interconnection (200) (Chiu, Fig. 12A, ¶0099-¶0102), to efficiently provide power delivery to the staked transistors (Chiu, ¶0014, ¶0102).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung/Xie/Chiu by forming the lower gate contact structure connected to the lower gate electrode and the lower interconnect as taught by Chiu to have the semiconductor device, wherein the first lower gate structure is configured to exchange input/output signals through the lower interconnection, in order to efficiently provide power delivery to the staked transistors (Chiu, ¶0014, ¶0102).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0332082 to Sung in view of Reboh (US 2015/0040240) and Xie (US 2023/0085628).
With respect to claim 19, a semiconductor device, comprising:
a lower structure (e.g., 412, 1010, and HKMG1) (Sung, Figs. 1-2, ¶0046);
an upper structure (e.g., 422, 1012, 1302, and HKMG2) (Sung, Figs. 1-2, ¶0046);
middle dielectric isolation structures (602) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0061) extending in a first direction (e.g., X direction) between the lower structure and the upper structure; and
a gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064), and extending from a side surface of at least a portion of the middle dielectric isolation structures (602) toward a lower end of the lower structure,
wherein the lower structure includes:
a lower source/drain regions (1010) (Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) spaced apart from each other in the first direction (e.g., X-direction);
lower active layers (412) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) spaced apart from each other in a vertical direction, between lower source/drain regions (1010), and electrically connected to the lower source/drain regions; and
a lower gate structure (HKMG1) (Sung, Figs. 1-2, ¶0046, ¶0048, ¶0050) including a first lower gate structure having a first lower gate electrode that extends in a second direction (Y direction) perpendicular to the first direction (X direction), and a second lower gate structure (e.g., a portion of the HKMG1 on the left side of the spacer 902) including a second lower gate electrode electrically insulated from the first lower gate electrode by the gate isolation insulating layer (902),
wherein the upper structure includes:
upper source/drain regions (1012) Sung, Figs. 1-2, ¶0046, ¶0065-¶0068, ¶0070) spaced apart from each other in the first direction and overlapping the lower source/drain regions (1010) in the vertical direction;
upper active layers (422) (Sung, Figs. 1-2, ¶0046, ¶0053-¶0056, ¶0062) spaced apart from each other in the vertical direction, between the upper source/drain regions (1012), connected to the upper source/drain regions, and overlapping the lower active layers (412) in the vertical direction; and
an upper gate structure (HKMG2) (Sung, Figs. 1-2, ¶0046, ¶0050, ¶0080) extending in the second direction (the Y direction) and overlapping the lower gate structure (HKMG1) in the vertical direction,
wherein the gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) is in contact with a side surface of the middle dielectric isolation structure (602) on the second lower gate structure (e.g., on a side of the HKMG1 on the left side of the spacer 902),
wherein the gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) extends along a side surface of the second lower gate structure (e.g., the HKMG1 on the left side of the spacer 902), and
wherein a lower end of the gate isolation insulating layer (902) (Sung, Figs. 1-2, ¶0046, ¶0064) is substantially a same distance from a substrate (402) as a lower end of the second lower gate structure (e.g., the HKMG1 on the left side of the spacer 902) and a lower end of the upper structure (e.g., vertical isolation region 1302).
Further, Sung does not specifically disclose (1) middle dielectric isolation structures spaced apart from each other in a second direction perpendicular to the first direction; (2) a gate isolation insulating layer between at least a portion of the lower gate structure and at least a portion of the upper gate structure.
Regarding (1), Reboh teaches forming a semiconductor device (Reboh, Figs. 1-3, ¶0004-¶0005, ¶0024-¶0042) comprising stacked FET transistors including vertically stacked nanosheet channel regions, and middle dielectric isolation structures (e.g., mid dielectric layers 20) (Reboh, Figs. 1-3, ¶0024, ¶0028, ¶0031) extending in a first direction (X direction) between the lower structure (15) and the upper structure (10) and spaced apart from each other in a second direction (Y direction) perpendicular to the first direction, to provide improved semiconductor device having critical dimensions and independent control to the channel layers of the stacked transistor devices (Reboh, ¶0001-¶0005, ¶0024, ¶0028, ¶0042).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming mid dielectric layers between a plurality of stacked FET transistors as taught by Reboh to have the semiconductor device, comprising: middle dielectric isolation structures spaced apart from each other in a second direction perpendicular to the first direction, in order to provide improved semiconductor device having critical dimensions and independent control to the channel layers of the stacked transistor devices (Reboh, ¶0001-¶0005, ¶0024, ¶0028, ¶0042).
Regarding (2), Xie teaches forming stacked gate-all-around (GAA) nanosheets FETs (Xie, Figs. 19A-19C, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0043-¶0092, ¶0094-¶0105) comprising the lower gate structure (144/147) (Xie, Fig. 19, ¶0102-¶0103) and the upper gate structure (144/149) each having a gate extension (147/149) including a base portion (151/155) and a side portion (153/157), such that a gata isolation layer (e.g., a portion of the ILD insulation layer 122) (Xie, Fig. 19, ¶0059, ¶0100) is between the lower gate structure (144/147) and the upper gate structure (144/149), in contact with a side surface of the middle dielectric isolation structure (126) on the lower gate structure (144/147), and on at least a portion of the lower gate structure (144/147), wherein the matching orientation between the lower base portion (151) and the upper base portion (155) facilitate formation of the common gate contact (182) to establish connection between the gates of the lower stack (115) and the upper stack (113), to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Sung by forming the lower gate structure and the upper gate structure each having a gate extension isolated with a gate isolation insulating layer as taught by Xie to have the semiconductor device, comprising: a gate isolation insulating layer between at least a portion of the lower gate structure and at least a portion of the upper gate structure, in order to provide improved stacked GAA nanosheet FETs with improved electrical isolation, increased device density, and improved contacts for independently controlled or shared gate structures (Xie, ¶0004-¶0006, ¶0031, ¶0036, ¶0039, ¶0103, ¶0105).
Regarding claim 20, Sung in view of Reboh and Xie discloses the semiconductor device of claim 19. Further, Sung discloses the semiconductor device, wherein the upper source/drain regions (e.g., p-type doped S/D regions 1012) (Sung, Figs. 1-2, ¶0046) and the lower source/drain regions (e.g., n-type doped S/D regions 1010) have different conductivity types.
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
