Prosecution Insights
Last updated: October 24, 2026
Application No. 18/816,109

DISPLAY APPARATUS AND TEST CIRCUIT BOARD

Non-Final OA §103
Filed
Aug 27, 2024
Priority
Dec 15, 2023 — RE 10-2023-0182947
Examiner
YECHURI, SITARAMARAO S
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
775 granted / 907 resolved
+17.4% vs TC avg
Minimal -8% lift
Without
With
+-8.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
33 currently pending
Career history
953
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
61.7%
+21.7% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 907 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claims 3-5, 7, 9, 10, 13-15, 17, 19, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 2, 6, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20180076234 A1) hereafter referred to as Kim in view of Chen (CN 101865937 B) In regard to claim 1 Kim teaches [see Fig. 20-22, Fig. 1, Fig. 2, “FIG. 2 is a schematic, partial side view of the display device of FIG. 1 showing the overlap and connection of a substrate pad and PCB pad” “FIG. 20 is a schematic top plan view of a printed circuit board coupled to the display device of FIG. 1” “FIG. 21 is an enlarged, plan view of a third terminal region of FIG. 20” “FIG. 22 is a cross-sectional view taken along line XXII-XXIII′ of FIG. 21” “FIG. 1 is a schematic, exploded perspective view of a display device”] a display apparatus comprising: a substrate [see Fig. 2, “display area DA and a pad area PNL_PAD represent an area positioned on the substrate SUB” ] including a display area where a plurality of display [“display area DA is an area displaying an image, and a display panel 100 (see FIG. 3) emitting light may be positioned in the display area DA” “display unit 140 includes the plurality of pixels 150 positioned in crossing regions of the first gate lines GW1, the second gate lines GW2, and the data lines DW. Here, each pixel 150 includes an organic light emitting diode”] elements is disposed; and a display circuit board [see Fig. 1, “printed circuit board 300 may be coupled with the first pad unit PAD_1 of the pad area PNL_PAD of the substrate SUB to transmit a signal required for driving the display panel 100 to the display panel 100”] disposed outside the display area, the display circuit board comprising: a first pad [see Fig. 22 “second contact pad terminal ROW_PAD_F”] and a second pad [“first contact pad terminal ROW_PAD_E”], which are disposed on the display circuit board [“Referring to FIG. 20, the printed circuit board 300 may include the base film 310, the second pad unit PAD_2, and the driving chip 350”] and connected to [see Fig. 2 “printed circuit board 300 may be coupled with the first pad unit PAD_1 of the pad area PNL_PAD of the substrate SUB to transmit a signal required for driving the display panel 100 to the display panel 100”] the substrate; and an film layer [“flexible base film 310”] disposed between the first pad and the second pad, PNG media_image1.png 215 723 media_image1.png Greyscale and a thickness [see under broadest reasonable interpretation, thickness of ROW_PAD_E_1 includes height of CT_1 see “the first contact hole CT_1 may be filled with the same metal as that of the first terminal line P_L_A_1, or may be filled with the metal of the first one of the first contact pad terminals ROW_PAD_E_1”, thus if it is the same metal, then ROW_PAD_E_1 extends into “the first contact hole CT_1” under broadest reasonable interpretation] of at least a portion of the second pad is different from a thickness of the first pad, but does not actually state that the film layer is an insulating layer and wherein the first pad overlaps the second pad, See that ROW_PAD_F_1 overlaps P_L_A_1 thus it is just naming convention whether P_L_A_1 is part of the pad ROW_PAD_E_1 or not. However insulation is obvious, see “A first terminal line P_L_A_1 and a second terminal line P_L_B_1 may be positioned at both sides, that is, an upper side and a lower side, based on the base film 310 on the printed circuit board SUB”, thus if the base film was not an insulator, then P_L_A_1 and P_L_B_1 would be shorted electrically i.e. the structure would be useless. PNG media_image2.png 289 802 media_image2.png Greyscale See that this is standard manufacturing, see for example Chen Figs. 1-12 see “two cantilever probes 25, 26 is made of a conductive material, the cantilever probes 25, 26 and conductive elements 23, 24 is made from the same material can also be made of different materials, and connected as a whole” “insulating strengthening layer 22, is made of insulating material” “conductive third conductive member 134 and a first beam member 133” are isolated by “second insulating strengthening layer 15” “As shown in FIG. 12, removing all of the sacrificial layer, the product of this invention is of the multi-layer probe group 20”, see that the built-up structure is easy design and allows making conductive structures to be of as thick and wide dimensions as desired. Thus if teaching of Chen is applied to Kim, then (P_L_A_1 and CT_1 metal and ROW_PAD_E_1) would be made of the same metal as one unit i.e. pad and as it can be seen in Chen Fig. 12, this would also have the thickness difference and as in Kim Fig. 22 the pad on the left is L shaped and goes beneath the pad on the right. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include that the film layer is an insulating layer and wherein the first pad overlaps the second pad. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is insulation so that the separate pads do not become electrically shorted and thus useless and that teaching of Chen gives simpler design and good electrical conduction using L shapes of same metal as thick and wide dimensions as desired. In regard to claim 2 Kim and Chen as combined teaches wherein the second pad comprises a first portion [see combination, see Kim Fig. 22 the pad on the left is L shaped and goes beneath the pad on the right, thus on the right side there is pad overlap on the left side there is no overlap and instead the thickness of the pad is large] overlapping the first pad and a second portion non-overlapping the first pad, wherein a thickness of the first portion is less than a thickness of the second portion. In regard to claim 6 Kim and Chen as combined teaches wherein the insulating layer contacts at least one of the first pad and the second pad on two surfaces [see combination, see Kim Fig. 22 the pad on the left is L shaped and goes beneath the pad on the right, thus at the corner of the L shape the insulation touches both the vertical side and the horizontal base of the L shaped pad] of the at least one of the first pad and the second pad, and the two surfaces extend along different directions from each other. In regard to claim 8 Kim and Chen as combined teaches wherein the two surfaces extending in the different directions [see claim 6 this edge is the corner of the L shaped pad] from each other share a same edge. Claim(s) 11, 12, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20180076234 A1) hereafter referred to as Kim in view of Chen (CN 101865937 B) In regard to claim 11 Kim teaches [see Fig. 20-22, Fig. 1, Fig. 2, “FIG. 2 is a schematic, partial side view of the display device of FIG. 1 showing the overlap and connection of a substrate pad and PCB pad” “FIG. 20 is a schematic top plan view of a printed circuit board coupled to the display device of FIG. 1” “FIG. 21 is an enlarged, plan view of a third terminal region of FIG. 20” “FIG. 22 is a cross-sectional view taken along line XXII-XXIII′ of FIG. 21” “FIG. 1 is a schematic, exploded perspective view of a display device”] a test circuit board for testing a display circuit board disposed outside a display apparatus [see Fig. 2, “display area DA and a pad area PNL_PAD represent an area positioned on the substrate SUB” “display area DA is an area displaying an image, and a display panel 100 (see FIG. 3) emitting light may be positioned in the display area DA” “display unit 140 includes the plurality of pixels 150 positioned in crossing regions of the first gate lines GW1, the second gate lines GW2, and the data lines DW. Here, each pixel 150 includes an organic light emitting diode”], the test circuit board [see Fig. 1, “printed circuit board 300 may be coupled with the first pad unit PAD_1 of the pad area PNL_PAD of the substrate SUB to transmit a signal required for driving the display panel 100 to the display panel 100”] comprising: a first test pad [see Fig. 22 “second contact pad terminal ROW_PAD_F”]; a second test pad [“first contact pad terminal ROW_PAD_E”] spaced apart from the first test pad; and an film layer [“flexible base film 310”] disposed between the first test pad and the second test pad, PNG media_image1.png 215 723 media_image1.png Greyscale and a thickness [see under broadest reasonable interpretation, thickness of ROW_PAD_E_1 includes height of CT_1 see “the first contact hole CT_1 may be filled with the same metal as that of the first terminal line P_L_A_1, or may be filled with the metal of the first one of the first contact pad terminals ROW_PAD_E_1”, thus if it is the same metal, then ROW_PAD_E_1 extends into “the first contact hole CT_1” under broadest reasonable interpretation] of at least a portion of the second test pad is different from a thickness of the first test pad, but does not actually state that the film layer is an insulating layer and wherein the first test pad overlaps the second test pad. See that ROW_PAD_F_1 overlaps P_L_A_1 thus it is just naming convention whether P_L_A_1 is part of the pad ROW_PAD_E_1 or not. However insulation is obvious, see “A first terminal line P_L_A_1 and a second terminal line P_L_B_1 may be positioned at both sides, that is, an upper side and a lower side, based on the base film 310 on the printed circuit board SUB”, thus if the base film was not an insulator, then P_L_A_1 and P_L_B_1 would be shorted electrically i.e. the structure would be useless. PNG media_image2.png 289 802 media_image2.png Greyscale See that this is standard manufacturing, see for example Chen Figs. 1-12 see “two cantilever probes 25, 26 is made of a conductive material, the cantilever probes 25, 26 and conductive elements 23, 24 is made from the same material can also be made of different materials, and connected as a whole” “insulating strengthening layer 22, is made of insulating material” “conductive third conductive member 134 and a first beam member 133” are isolated by “second insulating strengthening layer 15” “As shown in FIG. 12, removing all of the sacrificial layer, the product of this invention is of the multi-layer probe group 20”, see that the built-up structure is easy design and allows making conductive structures to be of as thick and wide dimensions as desired. Thus if teaching of Chen is applied to Kim, then (P_L_A_1 and CT_1 metal and ROW_PAD_E_1) would be made of the same metal as one unit i.e. pad and as it can be seen in Chen Fig. 12, this would also have the thickness difference and as in Kim Fig. 22 the pad on the left is L shaped and goes beneath the pad on the right. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include that the film layer is an insulating layer and wherein the first test pad overlaps the second test pad. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is insulation so that the separate pads do not become electrically shorted and thus useless and that teaching of Chen gives simpler design and good electrical conduction using L shapes of same metal as thick and wide dimensions as desired. In regard to claim 12 Kim and Chen as combined teaches wherein the second test pad comprises a first portion [see combination, see Kim Fig. 22 the pad on the left is L shaped and goes beneath the pad on the right, thus on the right side there is pad overlap on the left side there is no overlap and instead the thickness of the pad is large] overlapping the first test pad and a second portion non-overlapping the first test pad, wherein a thickness of the first portion is less than a thickness of the second portion. In regard to claim 16 Kim and Chen as combined teaches wherein the insulating layer contacts at least one of the first test pad and the second test pad on two surfaces [see combination, see Kim Fig. 22 the pad on the left is L shaped and goes beneath the pad on the right, thus at the corner of the L shape the insulation touches both the vertical side and the horizontal base of the L shaped pad] of the at least one of the first test pad and the second test pad, and the two surfaces extend along different directions from each other. In regard to claim 18 Kim and Chen as combined teaches wherein the two surfaces extending in the different directions [see claim 16 this edge is the corner of the L shaped pad] from each other share a same edge. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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Prosecution Timeline

Aug 27, 2024
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
77%
With Interview (-8.1%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 907 resolved cases by this examiner. Grant probability derived from career allowance rate.

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