Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 9th, 2026, has been received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20230345786 A1), and further in view of Iwamoto et al. (US 20070210414 A1).
Regarding independent claim 1, Yang (US 20230345786 A1) teaches a semiconductor device, comprising:
a doped structure (Fig. 15; conductive pad layer 280. See [0034] for improved thermal stability, which the examiner understands to be relevant for fuse structures);
a first dielectric layer (Fig. 15; dielectric capping layer 570), extending along a first direction (Fig. 15), and disposed on a top surface of the doped structure (Fig. 15; top surface that connects to conductive contact 550) along a second direction vertical to the first direction (Fig. 15); … and
an first insulating structure (Fig. 15; passivation layer 240) extending along the second direction (Fig. 15; thickness of passivation layer 240; wherein the thickness is taught to extend along the walls of a via opening) and disposed adjacent to a lateral surface of the doped structure (Fig. 15), wherein an first end of the first insulating structure is at the same escalation level with the bottom surface of the doped structure (Fig. 15; bottom end), and length of the first insulating structure is smaller than length of the doped structure (Fig. 15).
However, Yang remains silent regarding:
… a second dielectric layer, provided below a bottom surface of the doped structure along the second direction; …
The disclosure of Yang is a generalized structure for interconnecting semiconductor layers, e.g., connecting upper device layers to back-end-of-line (BEOL) layers. Further, Yang’s Figs. 1A-1C show circuitry that may be included over or in the substrate 110 ([0027]). Wherein examiner asserts that substrate 110 is a type of wiring layer, at least in view of Fig. 1A - 1C, [0018], and [0027].
However, in the same field of endeavor, Iwamoto (US 20070210414 A1) teaches a fuse structure (Fig. 13; [0033]). Further, Iwamoto teaches that this fuse structure may be located between any of layers M1 – M5; and, even further, Iwamoto teaches that the fuse structure also may be located in any of the semiglobal layer 200 and the global layer 300 too (Fig. 2 and [0083] – [0084]). Examiner asserts that one of ordinary skill in the art would recognize Yang’s substrate 110 may be considered as a wiring layer, or at least including wiring layers (see [0027] of Yang), e.g., BEOL layers; wherein Yang’s connective/interconnect structure (Fig. 15) may be implemented to connect device/wiring layers in a semiconductor device (such as Iwamoto’s). Thus, it would be obvious that when Yang’s substrate 110 is modified to include a BEOL structure, as disclosed by Iwamoto (Fig. 2); e.g., the portion of Yang’s conductive pad 280 that forms the via may be equivalent to the via connecting metal wiring layer M5 to metal wiring layer M3 in Iwamoto’s disclosure; wherein Yang’s interconnect element 220 may be considered the same as one of Iwamoto’s wiring layers, e.g., metal wiring layers M1 – M5. Therefore, Yang’s connective/interconnect structure may be connected to the BEOL of a device which may include a fuse, such as Iwamoto’s fuse (Fig. 13). The combination of Yang, further in view of Iwamoto, yields the semiconductor structure wherein:
… a second dielectric layer (Fig. 2; wherein an insulator layer 4b (unlabeled; see Fig. 13)), provided below a bottom surface of the doped structure along the second direction (yielded through the combination of Yang and Iwamoto); …
Examiner asserts that Yang’s connective structure would easily be implemented to Iwamoto’s Fig. 2; wherein an insulator layer 4b (Unlabeled. See Fig. 13) is in direct contact over the various metal wiring layers M1 – M5. Iwamoto’s Fig. 2 also shows a via V3 – V4 connecting metal wiring layer M5 to metal wiring layer M3, which is an obvious way to connect Yang’s structure to Iwamoto’s fuse.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Yang’s substrate to include to include semiconductor circuitry/devices, e.g., fuses and associated circuitry, as disclosed by Yang and Iwamoto, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Iwamoto’s wiring layers and circuitry are comparable to the wiring and circuitry discussed by Yang because they disclose similar semiconductor devices and connections thereto. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Yang’s substrate to include semiconductor circuitry/devices, e.g., fuses and associated circuitry, as disclosed by Yang and Iwamoto, with the predictable result of connecting semiconductor device to the appropriate circuitry of therein.
Regarding dependent claim 2, Yang, further in view of Iwamoto, teach the semiconductor device of claim 1, wherein
the first insulating structure is spaced apart from the second dielectric layer (Yielded through the combination of Yang, further in view of Iwamoto, at least by Yang’s etch stop layer 230. See Fig. 15).
Regarding dependent claim 3, Yang, further in view of Iwamoto, teach the semiconductor device of claim 1, wherein
each of the first dielectric layer (Yang: Fig. 15; recess of dielectric capping layer 570) and the second dielectric layer comprises a recess structure (Iwamoto: Fig. 13; recess of insulator layer 4b).
Regarding dependent claim 4, Yang, further in view of Iwamoto, teach the semiconductor device of claim 3, wherein
the doped structure is formed between the recess structures of the first dielectric layer and the second dielectric layer (Yielded through the combination of Yang, further in view of Iwamoto).
Regarding dependent claim 5, Yang, further in view of Iwamoto, teach the semiconductor device of claim 4, further comprising:
a fuse metal (Iwamoto: Fig. 13; metal cap film 9), formed on the recess structure of the second dielectric layer (Iwamoto: Fig. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, further in view of Iwamoto, to include a fuse structure, as disclosed by Iwamoto, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, the substrate of Yang, further in view of Iwamoto, as modified by Iwamoto’s fuse can yield a predictable result of overcurrent protection for the semiconductor device since that is the known function of a fuse. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding dependent claim 6, Yang, further in view of Iwamoto, teach the semiconductor device of claim 3, wherein
a width of the recess structure of the second dielectric layer is smaller than that of the recess structure of the first dielectric layer.
Examiner asserts that the widths of the recess structure (as disclosed by Iwamoto) in the first dielectric layer and the second dielectric layer are based off the widths of the conductive structures accommodated therein. Further, a width of the recess structure of the second dielectric layer is smaller than that of the recess structure of the first dielectric layer would be obvious from at least [0080] and Table 1 of Iwamoto, which teaches wiring widths.
Therefore, the claimed width of the recess structure of the second dielectric layer is smaller than that of the recess structure of the first dielectric layer would have been obvious, from at least [0080] and Table 1 of Iwamoto, to one of ordinary skill in the art before the effective filing date of the invention because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
Claims 7 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20230345786 A1), and further in view of Iwamoto et al. (US 20070210414 A1) and Kawabata et al. (US 7176080 B2).
Regarding dependent claim 7, Yang, further in view of Iwamoto, teach the semiconductor device of claim 1; however, Yang remains silent regarding the semiconductor device further comprising:
a doped portion, formed adjacent to a second end of the first insulating structure and the lateral surface of the doped structure.
However, in the same field of endeavor, Kawabata (US 7176080 B2) teaches a semiconductor structure known to be used in the same portion of a semiconductor device as disclosed by Yang, and Iwamoto, e.g., BEOL layer. Kawabata discloses a conductive structure that is a doped structure (col. 3; lines 33 – 35); wherein a doped portion (Fig. 12; strap 35. See col. 3; lines 52 – 55), formed adjacent to a second end of the first insulating structure (Kawabata teaches a similar structure, insulating film 30, as the first insulating layer) and the lateral surface of the doped structure (Fig. 12). Kawabata teaches in col. 3; lines 54 – 59 that the function of the strap 38 is such that “electrical resistance can be reduced in a junction region between the third conductive layer 33 and the cell transistor 23 or between a diffusion region 38 of the cell transistor 23 and the capacitor C”. Examiner asserts that it would be obvious to one of ordinary skill in the art that a structure such as Kawabata’s doped portion would function to lower the resistance along an analogous electrical path, e.g., a path to a fuse, such that it would be obvious to combine Kawabata’s doped portion to the device of Yang, further in view of Iwamoto to provide a path with low resistance to structure such as a fuse.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, further in view of Iwamoto, to include Kawabata’s doped portion, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Kawabata’s doped portion, formed adjacent to a second end of the first insulating structure and the lateral surface of the doped structure resides within a BEOL area of the device which is comparable to Iwamoto’s disclosure of a BEOL layer for a semiconductor device because both they are similar BEOL structures for similar device. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Yang, further in view of Iwamoto, to include Kawabata’s doped portion, formed adjacent to a second end of the first insulating structure and the lateral surface of the doped structure with the predictable result of electrically connecting transistors of the device to other semiconductor device formed within.
Regarding dependent claim 8, Yang, further in view of Iwamoto and Kawabata, teach the semiconductor device of claim 7; however, Yang remains silent on the semiconductor device further comprising:
a well region, extending along the first direction, wherein the doped portion is formed within the well region, and the first insulating structure is formed between the doped structure and the well region.
However, Kawabata teaches a well region (Kawabata teaches active areas of the substrate 22, e.g., active areas AAa and AAb, which the examiner understands to be a well region. For example, see col. 5; 62 – 67), extending along the first direction (Fig. 1; active area AAb), wherein the doped portion is formed within the well region (Fig. 2B is a cross-sectional view along line 2B). One of ordinary skill in the art would recognize that forming impurity regions (for device circuitry) in semiconductor wells is a standard practice within the field of endeavor, as disclosed by Kawabata.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, further in view of Iwamoto and Kawabata, to include Kawabata’s teaching of a well region, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Kawabata’s teaching of a well region is comparable to the well discussed in Yang ([0018]) because both acknowledge the use of well structures to form appropriately doped source/drain layers/structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Yang, further in view of Iwamoto and Kawabata, to include Kawabata’s teaching of a well region with the predictable result of forming source/drain layers/structures within the semiconductor device.
Further, examiner asserts that the combination of Yang and Iwamoto, further in view of Kawabata would yield the semiconductor structure wherein the first insulating structure is formed between the doped structure and the well region (yielded through the combination of Yang and Iwamoto, further in view of Kawabata).
Claims 9 – 11 and 13 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20230345786 A1), and further in view of Iwamoto et al. (US 20070210414 A1), Kawabata et al. (US 7176080 B2), and Huang (US 20240206156 A1).
Regarding dependent claim 9, Yang, further in view of Iwamoto and Kawabata, teach the semiconductor device of claim 8; however, Yang remains further comprising:
a doped layer, extending along the first direction and formed above the well region, wherein the doped structure is surrounded by the doped layer, and the doped portion is in direct contact with the well region and the doped layer.
However, in the same field of endeavor, Kawabata teaches a doped layer (Figs. 2A – 2B; impurity region 60), extending along the first direction (Figs. 2A – 2B) and … wherein the doped structure is surrounded by the doped layer (Figs. 2A – 2B), and the doped portion is in direct contact with the well region (Figs. 2A – 2B) and the doped layer (Figs. 2A – 2B). Such connectivity is known in the field of endeavor, and may be used as way to connect regions over a substrate in a semiconductor device, such as the device of Yang, Iwamoto, and Kawabata, with the expectation of success for forming a functional semiconductor device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, Iwamoto, and Kawabata, to include Kawabata’s doped layer, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Kawabata’s doped layer is comparable to the source/drain regions disclosed by Yang [0018], because Yang states that Various doped regions, such as source/drain regions, may be formed in or on the substrate 110. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Yang, Iwamoto, and Kawabata, to include Kawabata’s doped layer with the predictable result of forming device circuitry.
Additionally, it is the examiner’s opinion that Kawabata’s impurity region 60 ,i.e., doped layer, within the device disclosed also includes the feature wherein a doped layer is … formed above the well region (Figs. 2A – 2B). However, for the sake of compact prosecution, examiner points to Huang (US 20240206156 A1), in the same field of endeavor, who discloses a gate structure (Figs. 1B – 2) wherein source/drain region 114, i.e., a doped layer, is strictly above/abutting an uppermost boundary of the substrate 102 (i.e., a well region). Examiner asserts that in view of Kawabata’s impurity region 60 (i.e., doped layer) feature, a modification wherein a doped layer is strictly above/abutting an uppermost boundary of the well region would be an obvious structure choice, particularly when Kawabata’s gate structure is inverted about a virtual line that resides along a boundary of Kawabata’s substrate 22 and interlayer dielectric film 42. This forms an “inverted gate structure” (relative to what is shown by example of Kawabata); wherein this is “inverted gate structure” is a common gate structure design within the art (Huang: Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, Iwamoto, and Kawabata, to include Huang’s doped layer … formed above the well region, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Huang’s doped layer is comparable to Kawabata’s doped layer because they function as source/drain regions/layers/structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Yang, Iwamoto, and Kawabata, to include Huang’s doped layer … formed above the well region with the predictable result of providing appropriate electrical insulation for the source/drain structure and ease of manufacturing.
Regarding dependent claim 10, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 9, wherein
the doped layer is spaced apart from the first insulating structure (Yielded through the combination of Yang and Iwamoto, further in view of Kawabata).
Regarding dependent claim 11, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 9, wherein
a size of the doped portion is substantially equal to or less than 20% of a thickness of the doped layer (Kawabata shows this relative relationship in Fig. 2B. See excerpt below).
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Kawabata shows in Fig. 2B that the strap 35 and the impurity region 60 have a relative relationship of 0.09 : 0.47 (≈ 19%) for their widths.
Therefore, the claimed size of the doped portion is substantially equal to or less than 20% of a thickness of the doped layer would have been obvious, from at least Fig. 2B of Kawabata, to one of ordinary skill in the art before the effective filing date of the invention because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
Regarding dependent claim 13, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 9; however, Yang remains silent on the semiconductor device further comprising:
a gate structure, spaced apart from the doped structure and surrounded by the doped layer and the well region.
However, in the same field of endeavor, Kawabata teaches a gate structure (Fig. 2A; gate electrode 36), spaced apart from the doped structure (Figs. 2A – 2B) and surrounded by the doped layer (Figs. 2A – 2B) and the well region (Figs. 2A – 2B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, further in view of Iwamoto, Kawabata, and Huang, to include Kawabata’s gate structure, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Kawabata’s gate structure is comparable to the gate structures disclosed amongst Yang, Iwamoto, and Huang because their gate structures are in similar layers of a semiconductor device and include the same function of controlling/gatekeeping the current flow direction throughout the semiconductor device. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Yang, further in view of Iwamoto, Kawabata, and Huang, to include Kawabata’s gate structure with the predictable result of allowing current to flow to different portions of the semiconductor device.
Regarding dependent claim 14, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 13, further comprising:
a second insulating structure (Kawabata: Fig. 2A; gate insulating film 37), …
However, Kawabata remains silent wherein a second insulating structure is formed above the gate structure, wherein a top surface of the second insulating structure is at the same escalation level with that of the doped layer.
However, in the same field of endeavor, Huang teaches electrically insulating structure 128 (Fig. 1B), i.e., a second insulating structure, that is formed above the gate structure (Fig. 1B; gate electrode 122), wherein a top surface of the second insulating structure is at the same escalation level with that of the doped layer (Fig. 1B; top surface of doped layer 114 and top surface of electrically insulating structure 128).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, further in view of Iwamoto, Kawabata, and Huang, to include Haung’s second insulating structure formed above the gate structure, wherein a top surface of the second insulating structure is at the same escalation level with that of the doped layer, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Haung’s second insulating structure formed above the gate structure, wherein a top surface of the second insulating structure is at the same escalation level with that of the doped layer is comparable to Kawabata’s second insulating structure because they both function as gate insulating layers. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Yang, further in view of Iwamoto, Kawabata, and Huang, to include Haung’s second insulating structure formed above the gate structure, wherein a top surface of the second insulating structure is at the same escalation level with that of the doped layer, with the predictable result of providing insulating for the gate structure and even the doped layer.
Regarding dependent claim 15, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 14, further comprising:
a first oxidation layer (Yang: Fig. 15; dielectric layer 380), extending along the first direction (Yang: Fig. 15) and disposed between the doped layer and the first dielectric layer (Yielded through the combination of at least Yang and Kawabata), wherein the first oxidation layer is in direct contact with the doped structure (Yang: Fig. 15).
Regarding dependent claim 16, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 14; however, Yang remains silent on the semiconductor device further comprising:
a second oxidation layer, extending along the first direction and disposed between the well region and the second dielectric layer.
However, in the same field of endeavor, Iwamoto teaches insulator layer 4a (examiner interpreting as a second oxidation layer) in Fig. 13; wherein a second oxidation layer (Fig. 13; insulator layer 4a), extending along the first direction (Fig. 13) and disposed between the well region and the second dielectric layer (Yielded through the combination of Yang, further in view of Iwamoto, Kawabata, and Huang)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Yang, further in view of Iwamoto, Kawabata, and Huang, to include Iwamoto’s second oxidation layer, extending along the first direction and disposed between the well region and the second dielectric layer, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, the semiconductor device of Yang, further in view of Iwamoto, Kawabata, and Huang, as modified by Iwamoto’s second oxidation layer, extending along the first direction and disposed between the well region and the second dielectric layer can yield a predictable result of providing isolation and insulation for the fuse structure of their device since that is the function of Iwamoto’s insulator layer 4a. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20230345786 A1), and further in view of Iwamoto et al. (US 20070210414 A1), Kawabata et al. (US 7176080 B2), Huang (US 20240206156 A1), and Kimoto (US 20150357491 A1).
Regarding dependent claim 12, Yang, further in view of Iwamoto, Kawabata, and Huang, teach the semiconductor device of claim 9; however, Yang remains silent wherein
dopant concentration of the doped structure is greater than that of the doped layer, and dopant concentration of the doped portion is greater than that of the doped layer.
However, in the same field of endeavor, Huang teaches a doped portion (Fig. 2; heavily-doped region 238); wherein the examiner is considering the heavily-doped region 238 to be the doped portion because the heavily-doped region 238 is relatively smaller than the remaining doped region 236 of the source/drain region 114. Further, Huang teaches (at least [0083]) the same function for their heavily-doped region 238 as the instant application teaches their doped portion and as Kawabata’s teaches their doped portion, i.e., strap 35. Also, Huang teaches in [0083] that the doped region 236 has a doping concentration less than that of the heavily-doped region 238. Examiner asserts that due to the relative size of the structure and the need for the structure to attune a current direction towards upper/lower layers, it would be obvious that the doped portion is formed such that a dopant concentration of the doped portion is greater than that of the doped layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the doped portions of Yang, Iwamoto, Kawabata, and Huang, to include Huang’s teaching of dopant concentrations, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Huang’s doped portions are comparable to Kawabata’s doped portions because they have the same function of creating low resistance electrical pathways to nearby semiconductor structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the doped portions of Yang, Iwamoto, Kawabata, and Huang, to include Huang’s teaching of dopant concentrations with the predictable result of creating low resistance pathways to nearby semiconductors structures.
Further, in the same field of endeavor, Kimoto (US 20150357491 A1) teaches an interconnect structure (Fig. 1; lower electrode 91 + n-type layer 6) similar to that shown in Yang’s Fig. 15. Kimoto teaches a doping concentration of n-type layer 6 of about (5 x 1020 atoms·cm-3); wherein Huang taches in [0067] that the doping concentration of doped region 236 may be about (1 x 1013 atoms·cm-3). Thus, following Kimoto’s instruction for doping of interconnect layers, it would be obvious to form the device wherein dopant concentration of the doped structure is greater than that of the doped layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the doped structures of Yang, Iwamoto, Kawabata, and Huang, to include Kimoto’s teaching of dopant concentrations, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yang’s doped structure is comparable to Kimoto’s doped structure because they have the same function of creating low resistance electrical pathways to nearby semiconductor structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the doped structures of Yang, Iwamoto, Kawabata, and Huang, to include Kimoto’s teaching of dopant concentrations with the predictable result of creating low resistance pathways to nearby semiconductors structures.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20160359110 A1 – considered for Fig. 5.
US 20030186507 A1 – considered for Fig. 1H.
US 20060050559 A1 – considered for Fig. 3B.
US 20100230780 A1 – considered for Figs. 7 – 13.
US 20120032261 A1 – considered for Fig. 3A.
US 20140015030 A1 – considered for the HVG structure in Fig. 2.
US 20160329282 A1 – considered for Figs. 2A – 2C.
US 20220246625 A1 – considered for Fig. 2G.
US 8603918 B2 – considered for Figs. 15 – 16.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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