DETAILED ACTION
This office action is in response to the application filed on 8/27/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/27/2024, 10/30/2025 and 8/14/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 2020/0111742)
With respect to Claim 17, Han shows (Fig. 13) all aspects of the current invention including a semiconductor package, comprising:
a first semiconductor chip (120);
an encapsulant (131) covering at least a portion of the first semiconductor chip;
insulating layers (132,190) provided on the encapsulant (par 66);
wiring layers (152) provided on the encapsulant, the wiring layers being partially covered by the insulating layers
wherein an outermost insulating layer of the insulating layers comprises a first region (opening portion comprising M) and a second region (region of 190 surrounding M),
wherein the second region surrounds the first region
wherein at least one marking pattern (M) comprising at least one step portion is provided in the first region of the insulating layer (see enlarged portion in Fig 13)
wherein the first region comprises an insulating material without carbon black (resin; par 66,83)
With respect to Claim 18, Han shows (Fig. 13) wherein the insulating layers comprise a thermosetting material layer (par 66)
With respect to Claim 19, Han shows (Fig. 13) wherein insulating layers comprise a photoimageable dielectric material layer (par 66,83)
With respect to Claim 20, Han shows (Fig. 13) all aspects of the current invention including a semiconductor package, comprising:
a first semiconductor chip (120);
an encapsulant (131) covering at least a portion of the first semiconductor chip;
insulating layers (132,190) provided on the encapsulant (par 66);
wiring layers (152) provided on the encapsulant, the wiring layers being partially covered by the insulating layers
wherein an outermost insulating layer of the insulating layers comprises a first region (opening portion comprising M) and a second region (region of 190 surrounding M),
wherein the second region surrounds the first region
wherein at least one marking pattern (M) comprising at least one step portion is provided in the first region of the insulating layer (see enlarged portion in Fig 13)
wherein an insulating material layer in the first region is in a further hardened state than an insulating material layer in the second region (resin; par 66,83)
Claims 17,20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae (US 2020/0105679).
With respect to Claim 17, Bae shows (Fig. 16) all aspects of the current invention including a semiconductor package, comprising:
a first semiconductor chip (120);
an encapsulant (131) covering at least a portion of the first semiconductor chip;
insulating layers (132,151,190) provided on the encapsulant (par 66);
wiring layers (152,152L) provided on the encapsulant, the wiring layers being partially covered by the insulating layers
wherein an outermost insulating layer of the insulating layers comprises a first region (insulation portion comprising MP) and a second region (region of 190 surrounding MP),
wherein the second region surrounds the first region
wherein at least one marking pattern (MP) comprising at least one step portion is provided in the first region of the insulating layer
wherein the first region comprises an insulating material without carbon black (PID resin; par 70,102)
With respect to Claim 20, Bae shows (Fig. 16) all aspects of the current invention including a semiconductor package, comprising:
a first semiconductor chip (120);
an encapsulant (131) covering at least a portion of the first semiconductor chip;
insulating layers (132,151,190) provided on the encapsulant (par 66);
wiring layers (152,152L) provided on the encapsulant, the wiring layers being partially covered by the insulating layers
wherein an outermost insulating layer of the insulating layers comprises a first region (insulation portion comprising MP) and a second region (region of 190 surrounding MP),
wherein the second region surrounds the first region
wherein at least one marking pattern (MP) comprising at least one step portion is provided in the first region of the insulating layer
wherein an insulating material layer in the first region is in a further hardened state than an insulating material layer in the second region (PID resin; par 70,102)
Allowable Subject Matter
Claims 1-16 contain allowable subject matter. With respect to claim 1, the prior art of record fails to disclose or suggest a semiconductor package, comprising wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, wherein the second region surrounds the first region, wherein at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer and wherein a polycrystalline ratio of an insulating material layer in the first region is higher than a polycrystalline ratio of an insulating material layer in the second region.
Examiner’s comments: the closest prior art references include (Han US 2020/0111742; Bae US 2020/0105679; Chiang US 2020/0273806; Lim US 2015/0380359) all directed in part to a semiconductor package, comprising mark patterns similar to the instant invention. However, the following references do neither anticipates nor renders obvious the following features of wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, wherein the second region surrounds the first region, wherein at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer and wherein a polycrystalline ratio of an insulating material layer in the first region is higher than a polycrystalline ratio of an insulating material layer in the second region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached on M-F 9AM-4PM.
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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