DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8, and 10-20 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by RYU et al. (US 20220223732 A1, hereinafter Ryu)
With regards to claim 1, Ryu discloses a semiconductor device (FIGS. 1-2) comprising:
a bit line; (conductive bit line 120)
an active pattern (channel 130) on the bit line, and including a lower active portion (oxide semiconductor layer 132) electrically connected to the bit line,
a first vertical active portion (left portion of oxide semiconductor layer 134) extending from the lower active portion, and
a second vertical active portion (right portion of oxide semiconductor layer 134) extending from the lower active portion,
wherein the first vertical active portion and the second vertical active portion are spaced apart from one another; (see FIG. 2)
a word line (gate electrodes 150) between a lower region of the first vertical active portion and a lower region of the second vertical active portion; and
a conductive pad pattern (at least landing pads 160) electrically connected to an upper region of the first vertical active portion and an upper region of the second vertical active portion. (see FIG. 2, showing the connection)
With regards to claim 2, Ryu discloses the semiconductor device of claim 1, wherein the active pattern includes an oxide semiconductor. (oxide semiconductor 134)
With regards to claim 3, Ryu discloses the semiconductor device of claim 1, wherein the bit line extends in a first horizontal direction, (X direction, see FIGS. 1-2)
wherein the word line extends in a second horizontal direction (Y direction) perpendicular to the first horizontal direction, (See FIG. 1-2) wherein the first vertical active portion and the second vertical active portion are spaced apart in the first horizontal direction, (See FIG. 2) and
wherein the conductive pad pattern comprises:
an upper pad portion; (upper portions of pads 160)
a first lower pad portion (lower portion of pad 160A) extending from the upper pad portion and electrically connected to the upper region of the first vertical active portion; and
a second lower pad portion (lower portion of pad 160B) extending from the upper pad portion and electrically connected to the upper region of the second vertical active portion. (See FIGS. 1-2)
With regards to claim 4, Ryu discloses the semiconductor device of claim 3, wherein the first vertical active portion has a first side surface facing the second vertical active portion and a second side surface opposing the first side surface, (see FIG. 2)
wherein the second vertical active portion has a third side surface facing the first vertical active portion and a fourth side surface opposing the third side surface, (see FIG. 2)
wherein the first lower pad portion contacts the second side surface of the first vertical active portion, and
wherein the second lower pad portion contacts the fourth side surface of the second vertical active portion. (See FIG. 2, showing the contacting of the pads 160A/B onto the sides of layers 134)
With regards to claim 5, Ryu discloses the semiconductor device of claim 4, wherein at least a portion of an upper surface of the first vertical active portion is in contact with the first lower pad portion.
With regards to claim 7, Ryu discloses the semiconductor device of claim 1, further comprising an insulating capping pattern between an upper surface of the word line and the conductive pad pattern, wherein the insulating capping pattern comprises:
an upper capping portion (insulating layer 116) that is a greater first distance from the bit line than a second distance of the active pattern from the bit line; and
a lower capping portion (insulating layer 114) extending from a central area of the upper capping portion and contacting the upper surface of the word line, and
wherein the upper capping portion includes a portion vertically overlapping at least one of the first and second vertical active portions. (See FIG. 2)
With regards to claim 8, Ryu discloses the semiconductor device of claim 1, wherein the active pattern further comprises: a first extended active portion (left upper extending portion of channel 132) extending from an upper region of the first vertical active portion in a direction away from the second vertical active portion; and
a second extended active portion (right upper extending portion of channel 132) extending from an upper region of the second vertical active portion in a direction away from the first vertical active portion.
With regards to claim 10, Ryu discloses the semiconductor device of claim 8, wherein the first vertical active portion has a first side surface facing the second vertical active portion and a second side surface opposing the first side surface, (See FIG. 2)
wherein the second vertical active portion has a third side surface facing the first vertical active portion and a fourth side surface opposing the third side surface, and
wherein the conductive pad pattern comprises:
an upper pad portion; (upper portion of pads 160A/160B) and
a lower pad portion (lower portion of pads 160A/160B) extending from a central area of the upper pad portion and contacting the first side surface of the first vertical active portion and the third side surface of the second vertical active portion. (See Fig. 2)
With regards to claim 11, Ryu discloses the semiconductor device of claim 10, wherein at least a portion of an upper surface of the active pattern is in contact with the conductive pad pattern. (see FIG. 2, showing the electrical contact)
With regards to claim 12, Ryu discloses a semiconductor device comprising:
a conductive line (conductive line 120) extending in a first horizontal direction;
a first active pattern and a second active pattern (channels 132 and 134) on the conductive line;
a first gate electrode and a second gate electrode (150A and 150B) on the conductive line; and
a first conductive pad pattern and a second conductive pad pattern (at least pads 160A and 160B) on the first and second gate electrodes, respectively, wherein each of the first and second active patterns comprises:
a lower active portion (horizontal portion of channel 132/134) electrically connected to an upper surface of the conductive line;
a first vertical active portion (left horizontal portion of oxide semiconductor layer 132/134) extending from the lower active portion; and
a second vertical active portion (right horizontal portion of oxide semiconductor layer 132/134) extending from the lower active portion,
wherein the first gate electrode is between the first vertical active portion of the first active pattern and the second vertical active portion of the first active pattern, and is on the lower active portion of the first active pattern, (See FIG. 2)
wherein the second gate electrode is between the first vertical active portion of the second active pattern and the second vertical active portion of the second active pattern, and is on the lower active portion of the second active pattern, (See FIG. 2)
wherein the first conductive pad pattern is electrically connected to the first vertical active portion of the first active pattern and the second vertical active portion of the first active pattern, (See FIG. 2) and
wherein the second conductive pad pattern is electrically connected to the first vertical active portion of the second active pattern and the second vertical active portion of the second active pattern. (See FIG. 2)
With regards to claim 13, Ryu discloses the semiconductor device of claim 12, wherein respective widths of the first and second conductive pad patterns in the first horizontal direction are greater than respective widths of the first and second active patterns in the first horizontal direction. (See FIG. 2, showing the relative widths)
With regards to claim 14, Ryu discloses the semiconductor device of claim 12, wherein the first conductive pad pattern comprises:
an upper pad portion (upper portion of pads 160) on the first active pattern;
a first lower pad portion (lower portion of pad 160A) extending from the upper pad portion and contacting a side surface of the first vertical active portion of the first active pattern; and
a second lower pad portion (lower portion of pad 160B) extending from the upper pad portion and contacting a side surface of the second vertical active portion of the first active pattern. (See FIG. 2)
With regards to claim 15, Ryu discloses the e semiconductor device of claim 14, wherein the first lower pad portion is in contact with at least a portion of an upper surface of the first vertical active portion. (See FIG. 2)
With regards to claim 16, Ryu discloses the semiconductor device of claim 12, wherein the first conductive pad pattern comprises:
an upper pad portion (upper portion of pads 160) on the first active pattern; and
a lower pad portion (lower portions of pads 160A/160B) extending from a central portion of the upper pad portion and contacting a side surface of the first vertical active portion of the first active pattern and a side surface of the second vertical active portion of the first active pattern. (See FIG. 2)
With regards to claim 17, Ryu discloses the semiconductor device of claim 16, wherein the lower pad portion is in contact with at least a portion of an upper surface of the first vertical active portion. (See FIG. 2)
With regards to claim 18, Ryu discloses a semiconductor device comprising:
a conductive line (conductive line 120) extending in a first horizontal direction;
a cell transistor (transistor 130-150) on the conductive line; and
a conductive pad pattern (at least pads 160) on the cell transistor, wherein the cell transistor comprises:
an active pattern (at least channel 132/134) including a first vertical channel portion (left vertical portion of 134) and a second vertical channel portion (right vertical portion of 134) spaced apart from each other in the first horizontal direction;
a single gate electrode (electrode 150A) between the first and second vertical channel portions; and
a gate dielectric layer (dielectric 140A) between the single gate electrode and the active pattern, and
wherein the conductive pad pattern contacts upper regions of the first and second vertical channel portions. (See FIG. 2)
With regards to claim 19, Ryu discloses the semiconductor device of claim 18, wherein the first vertical channel portion has a first side surface facing the second vertical channel portion and a second side surface (side surfaces of left channel 132) opposing the first side surface, wherein the second vertical channel portion has a third side surface facing the first vertical channel portion and a fourth side surface (side surface of right channel 132) opposing the third side surface, (see FIG. 2) and wherein the conductive pad pattern comprises:
an upper pad portion; (upper portions of pads 160)
a first lower pad portion (lower portion of pad 160A) extending from the upper pad portion and contacting the second side surface of the first vertical channel portion; and
a second lower pad portion (lower portion of pad 160B) extending from the upper pad portion and contacting the fourth side surface of the second vertical channel portion. (See FIG. 2)
With regards to claim 20, Ryu discloses the semiconductor device of claim 18, wherein the first vertical channel portion has a first side surface facing the second vertical channel portion and a second side surface (side surfaces of left channel 132) opposing the first side surface, wherein the second vertical channel portion has a third side surface facing the first vertical channel portion and a fourth side surface (side surfaces of rightchannel 132) opposing the third side surface, and wherein the conductive pad pattern comprises:
an upper pad portion; (upper portions of pads 160A/160B) and
a lower pad portion (lower portions of pads 160A and 160B) extending from a central area of the upper pad portion and contacting the first side surface of the first vertical channel portion and the third side surface of the second vertical channel portion. (See FIG. 2)
Allowable Subject Matter
Claims 6 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 20230292490 A1) – cell transistor structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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