DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected for indefiniteness.
Regarding claim 19, the claim recites, "the base layer comprises Yuma." However, the specification is silent to a definition of "Yuma." A broad search related to semiconductors did not yield a material called "Yuma." Examiner is unclear as to the composition of Yuma and therefore claim 19 will not be examined. Proper correction is required.
Allowable Subject Matter
Claims 4-6 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 4 and 9, no prior art found in the search teaches or suggests a method wherein after the first hard mask is removed an organic planarization layer is deposited then removing at least a portion of the additional hard mask after depositing the organic planarization layer; and removing the organic planarization layer after removing the at least a portion of the additional hard mask. Emphasis on the underlined portion.
While Nagabhirava (US 20230343593 A1) teaches an organic planarization layer as the top portion of the base layer 201, Nagabhirava does not disclose forming 201 after removing a hard mask. No other prior art found in the search teaches or suggests these method limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagabhirava (US 20230343593 A1).
Regarding claim 15, Nagabhirava teaches a semiconductor structure (200, Fig 2) comprising:
a base layer (201B: 201 is comprised of two subparts; 201A is the top portion of 201 that comprises an organic planarization layer and the organic planarization layer is completely etched through, [0051]; 201B is the lower portion comprised of another structure, [0051]) of dielectric material (low-k dielectric, [0035]);
a body layer (201A) of a low-k dielectric material (low-k dielectric, [0035]) over (over, [0051]) the base layer (201B);
a hard mask (202b) over (shown over) the body layer (201A); and
a plurality of trenches (204) etched through (shown etched through) the hard mask (202b) and the body layer (201A; the organic planarization layer is completely etched through, [0051]) and only partially etched (shown only partially etched) into the base layer (201B).
Regarding claim 16, Nagabhirava teaches the structure of claim 15 and goes on to teach wherein the hard mask (202B, Fig 2) comprises silicon oxynitride (SiON, [0006]).
Regarding claim 17, Nagabhirava teaches the structure of claim 15 and goes on to teach further comprising a second hard mask (202a, Fig 2) over (shown over) the hard mask (202b), wherein
the plurality of trenches (204) is etched through (shown etched through) the second hard mask (202a).
Regarding claim 18, Nagabhirava teaches the structure of claim 17 and goes on to teach wherein the second hard mask (202a, Fig 2) comprises titanium nitride (TiN, [0006]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nagabhirava (US 20230343593 A1), and further in view of Hsue (US 6696222 B2).
Regarding claim 1, Nagabhirava teaches a method (method, Fig 1) for forming … structures (425, Fig 4; underlying structures, [0062]),
the method comprising:
etching trenches (204, Fig 2) into a semiconductor structure (200) such that the trenches (204) extend completely through (shown extended completely through) a hard mask (202a) and a body layer (201A: 201 is comprised of two subparts; 201A is the top portion of 201 that comprises an organic planarization layer and the organic planarization layer is completely etched through, [0051]; 201B is the lower portion comprised of another structure, [0051]) of low-k dielectric material (low-k dielectric, [0035]), and only partially into (shown only partially into) a base layer (201B) of dielectric material (low-k dielectric, [0035]);
removing (shown removed, Fig 2) the hard mask (202a) while the base layer (201B) of dielectric material is only partially etched (shown partially etched); and
etching fully through (shown fully etched through, Fig 4) the base layer (201B) of dielectric material to complete the trenches (204) after (shown after) the hard mask removal (shown removed) of the hard mask (202a).
Nagabhirava fails to explicitly teach a method for forming interconnects over tungsten structures.
However, Hsue teaches a method for forming interconnects (50', Fig 2) over (shown over) tungsten (32; metal wire structures, [Col 3, Ln 21]; it is well known in the art to use tungsten for wires) structures.
Nagabhirava and Hsue are considered analogous to the claimed invention because both are from the same field of endeavor of methods of forming interconnects for semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Nagabhirava with the features of Hsue to create a method for forming interconnects over tungsten structures in order to reduce the parasitic capacitance for increasing the speed of conduction between the metal interconnections (Hsue, [Col 1, Ln 18-21]) to increase the gap-filling capacity of the subsequently deposited conductive layer in the dual damascene opening (Hsue, [Col 2, Ln 43-45]) and to reduce RC delay and cross talk, therefore allowing chip size to be scaled down to the next generation (Hsue, [Col 2, Ln 49-51]).
Regarding claim 2, the combination of Nagabhirava and Hsue discloses the method of claim 1. Nagabhirava goes on to teach wherein removing the hard mask (202a, Fig 2) comprises performing an etch (etch; selective etch to material of upper layer, [0042]) selective to titanium nitride (TiN, [0006]).
Regarding claim 3, the combination of Nagabhirava and Hsue discloses the method of claim 1. Hsue teaches tungsten (32; metal wire structures, [Col 3, Ln 21]; it is well known in the art to use tungsten for wires) structures.
Nagabhirava goes on to teach wherein the base layer (201B, Fig 2) protects (shown protecting) underlying tungsten structures (425, Fig 4) during the etch (etch) selective to titanium nitride (TiN).
Regarding claim 7, the combination of Nagabhirava and Hsue discloses the method of claim 1. Nagabhirava teaches the trenches (204, Fig 2).
Hsue goes on to teach further comprising:
filling (shown filling, Fig 2) the trenches (204, Fig 2) with copper (50); and
removing excess (shown removing excess) copper (50) using chemical mechanical planarization (CMP, [Col 4, Ln 4]).
Regarding claim 8, Nagabhirava teaches a method (method, Fig 1) for fully removing (shown fully removed, Fig 2) hard masks (202) …, the method comprising:
partially etching (shown partially etched) a base layer (201) of dielectric material (low-k dielectric, [0035]);
performing hard mask removal (etch; selective etch to material of upper layer, [0042]) of a titanium nitride (TiN, [0006]) hard mask (202a) over (shown over) the base layer (201) while the base layer (201) of dielectric material is partially etched (shown partially etched); and
opening (shown open, Fig 4) the dielectric material of the base layer (201) with a reactive ion etch (etch) after the hard mask (202a) removal (shown removed) of the titanium nitride hard mask (202a).
Nagabhirava fails to explicitly teach a method for fully removing hard masks for forming interconnects.
However, Hsue teaches a method for fully removing hard masks for forming interconnects (50', Fig 2).
Nagabhirava and Hsue are considered analogous to the claimed invention because both are from the same field of endeavor of methods of forming interconnects for semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Nagabhirava with the features of Hsue to create a method for fully removing hard masks for forming interconnects in order to reduce the parasitic capacitance for increasing the speed of conduction between the metal interconnections (Hsue, [Col 1, Ln 18-21]) to increase the gap-filling capacity of the subsequently deposited conductive layer in the dual damascene opening (Hsue, [Col 2, Ln 43-45]) and to reduce RC delay and cross talk, therefore allowing chip size to be scaled down to the next generation (Hsue, [Col 2, Ln 49-51]).
Regarding claim 20, Nagabhirava teaches the structure of claim 15 and goes on to teach wherein the base layer (201, Fig 2) of dielectric material is positioned above (shown above) a … structure (425, Fig 4; underlying structures, [0062]).
Nagabhirava fails to explicitly teach a tungsten structure.
However, Hsue teaches a tungsten (32; metal wire structures, [Col 3, Ln 21]; it is well known in the art to use tungsten for wires) structure.
Nagabhirava and Hsue are considered analogous to the claimed invention because both are from the same field of endeavor of methods of forming interconnects for semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of Nagabhirava with the features of Hsue to create a structure wherein the base layer of dielectric material is positioned above a tungsten structure in order to reduce the parasitic capacitance for increasing the speed of conduction between the metal interconnections (Hsue, [Col 1, Ln 18-21]) to increase the gap-filling capacity of the subsequently deposited conductive layer in the dual damascene opening (Hsue, [Col 2, Ln 43-45]) and to reduce RC delay and cross talk, therefore allowing chip size to be scaled down to the next generation (Hsue, [Col 2, Ln 49-51]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Indrakanti (US 9105700 B2) - a1, self-aligned vias
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
