DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2023-0141407, filed on 10/20/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF WHICH INCLUDES ATTACHING AN INSULATING LAYER AND A SEED LAYER ON AN ACTIVE SURFACE OF A SEMICONDUCTOR CHIP USING A CARRIER LAYER AND FORMING CONDUCTIVE VIAS”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chia (US 2009/0090541 A1) in view of Hsu-510 (US 2022/0225510 A1).
Regarding claim 1, Chia teaches a method of manufacturing a semiconductor package (stacked semiconductor device, Figs. 2A-D followed by Figs. 3A-C, and then Figs. 2H-K, as the second embodiment, [0046]) that comprises a semiconductor chip (semiconductor chip 23, Fig. 2K, [0029]) comprising an active surface (active surface 23a, Fig. 2K (refer to Fig. 2A for the label), [0029]) and an inactive surface (inactive surface 23b, Fig. 2K (refer to Fig. 2A for the label), [0029]) opposite to the active surface (active surface 23a, Fig. 2K), the method comprising:
attaching (Figs. 2A-B, [0030]), to the active surface (active surface 23a, Figs. 2A-B) of the semiconductor chip (semiconductor chip 23, Figs. 2A-B), a film structure (comprising second flexible layer 22 and metal layer 221, Figs. 2A-B, [0030]) comprising an insulating layer (second flexible layer 22, Figs. 2A-B; while Chia does not explicitly disclose that the second flexible layer is an insulating layer, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the second flexible layer is an insulating layer as it contains connection vias (via 220, Figs. 2C and 2K, [0032]) and connection layers (conductive layer 222, Figs. 2C and 2K, [0032]) in the final device (Fig. 2K)) and a first seed layer (metal layer 221, Figs. 2A-B) contacting the insulating layer (second flexible layer 22, Figs. 2A-B);
forming a via hole (via 220, Fig. 2C, [0031]) penetrating the insulating layer (second flexible layer 22, Figs. 2C) and the first seed layer (metal layer 221, Figs. 2C);
forming a second seed layer (conductive layer 222, Fig. 2D, [0032]) on the insulating layer (second flexible layer 22, Figs. 2D) and the first seed layer (metal layer 221, Figs. 2D);
forming a photoresist pattern (resist layer 24, Fig. 3A, [0049]) on the second seed layer (conductive layer 222, Fig. 3A); and
forming a conductive via (conductive vias 252, Figs. 3C) by filling (Fig. 3B: partially filling) a space defined by the via hole (via 220, Fig. 3B) with a conductive material (metal layer 223, Fig. 3B, [0048)) and forming a conductive pattern (comprising metal layer 221, conductive layer 222, and conductive pad 253 in the via 220; Fig. 3C, [0049]) by filling a space (the regions between the resist layer 24, Fig. 2B) defined by the photoresist pattern (resist layer 24, Fig. 3B) with the conductive material (metal layer 223, Figs. 3B-C).
Chia, however, is silent about a descum process, and therefore does not teach
performing a descum process on the insulating layer and the first seed layer in which the via hole is formed; and
forming a second seed layer on the insulating layer and the first seed layer on which the descum process was performed.
Hsu-510, on the other hand, teaches a method for manufacturing a circuit board (circuit board 1, Figs. 1-9, [0017]), wherein a via hole (second opening 106, Figs. 2 and 5, [0022]) exposing a contact pad (connection pad 105, Fig. 2, [0018]) is formed through insulating layers (adhesive layer 103 and cover layer 104 Figs. 2 and 5, [0019]). Hsu-510 further teaches, after forming the via hole,
performing a descum process ([0032]: “The residue 24 in the second opening 106 is removed by plasma … to fully expose a surface of the connection pad 105.” [0032]);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that residues might also be present after forming the via holes in the method of Chia which might degrade the quality of the layers formed in the following steps of the method. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to perform a descum process, before forming the second seed layer, on the surface of the semiconductor package (including the insulating layer and the first seed layer in which the via hole is formed) to remove the residues formed on the surface after forming the via hole. Thus, the combination of Chia and Hsu-510 meets the limitations including
performing a descum process on the insulating layer and the first seed layer in which the via hole is formed; and
forming a second seed layer on the insulating layer and the first seed layer on which the descum process was performed.
Regarding claim 2, Chia in view of Hsu-510 teaches the method of claim 1, wherein,
the combination of Chia and Hsu-510 (descum process of Hsu-510 incorporated into the method of Chia, see claim 1 rejection above)
in performing the descum process (see claim 1 rejection above), a surface (top surface in direct contact with the metal layer 221, Fig. 2C) of the insulating layer (second flexible layer 22, Fig. 2C (showing the structure at the processing step when the descum process is applied according to Chia in view of Hsu-510)), which is parallel to the active surface (active surface 23a, Fig. 2C (refer to Fig. 2A for the label)) of the semiconductor chip (semiconductor chip 23, Fig. 2C), contacts the first seed layer (metal layer 221, Fig. 2C), and a surface (vertical sidewalls in the via 220, Fig. 2C) of the insulating layer (second flexible layer 22, Fig. 2C), which is not parallel to the active surface (active surface 23a, Fig. 2C) of the semiconductor chip (semiconductor chip 23, Fig. 2C), is exposed to a plasma (see claim 1 rejection above).
Regarding claim 3, Chia in view of Hsu-510 teaches the method of claim 1, wherein,
Chia further teaches that in forming the conductive via (via 220, Fig. 3C) and forming the conductive pattern (comprising metal layer 221, conductive layer 222, and conductive pad 253 in the via 220; Fig. 3C), a surface (horizontal portion of the top surface in Fig. 3C) of the insulating layer (second flexible layer 22, Fig. 3C), which is parallel to the active surface (active surface 23a, Fig. 3C (refer to Fig. 2A for the label)), contacts the first seed layer (metal layer 221, Fig. 3C), and a surface (corresponding to the sidewalls of the via 220, Fig. 3C) of the insulating layer (second flexible layer 22, Fig. 3C), which is not parallel to the active surface (active surface 23a, Fig. 3C) of the semiconductor chip (semiconductor chip 23, Fig. 3C), contacts the second seed layer (conductive layer 222, Fig. 3C).
Regarding claim 4, Chia in view of Hsu-510 teaches the method of claim 1, wherein,
Chia further teaches that in forming the second seed layer (conductive layer 222, Fig. 3C), a surface (corresponding to the sidewalls of the via 220, Fig. 3C) of the insulating layer (second flexible layer 22, Fig. 3C), which is not parallel to the active surface (active surface 23a, Fig. 3C (refer to Fig. 2A for the label)), contacts the second seed layer (conductive layer 222, Fig. 3C).
Regarding claim 5, Chia in view of Hsu-510 teaches the method of claim 1, wherein, in forming the second seed layer (conductive layer 222, Fig. 3C), the first seed layer (metal layer 221, Fig. 3C) and the second seed layer (conductive layer 222, Fig. 3C) form an interface (Fig. 3C: first seed layer and second seed layer are in direct contact and therefore form an interface).
Regarding claim 7, Chia in view of Hsu-510 teaches the method of claim 1, wherein
Chia further teaches that in forming the conductive via (via 220, Fig. 3C) and forming the conductive pattern (comprising metal layer 221, conductive layer 222, and conductive pad 253 in the via 220; Fig. 3C), a side surface of the first seed layer (side surface of metal layer 221, Fig. 3C), a side surface of the second seed layer (side surface of conductive layer 222, Fig. 3C), and a side surface of the conductive pattern (comprising metal layer 221, conductive layer 222, and conductive pad 253 in the via 220; Fig. 3C) are located on a same plane (vertical plane formed by the sidewalls of metal layer 221, conductive layer 222, and conductive pad 253, Fig. 3C).
Regarding claim 8, Chia in view of Hsu-510 teaches the method of claim 1, wherein
the combination of Chia and Hsu-510 further teaches that
performing the descum process (Hsu-510, [0032]: “The residue 24 in the second opening 106 is removed by plasma … to fully expose a surface of the connection pad 105.” [0032]) comprises applying a plasma treatment ([0032]: plasma).
Claims 6, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chia (US 2009/0090541 A1) in view of Hsu-510 (US 2022/0225510 A1) as applied to claims 1-5 and 7-8 above, and further in view of Matsuura (US 2018/0376602 A1).
Regarding claim 6, while Chia in view of Hsu-510 teaches the method of claim 1,
Chia and Hsu-510 do not teach that in forming the conductive via and forming the conductive pattern, a width of the conductive via decreases towards the active surface of the semiconductor chip.
Matsuura, on the other hand, teaches a method for manufacturing a printed wiring board (printed wiring board, Figs. 4-5, [0026]-[0027]), which is analogous to the method of Chia in view of Hsu-510 in that the method includes forming a via hole (via hole 128, Fig. 4b, [0002]) through a first seed layer (thin copper layer 118, Fig. 4b, [0002]) and an underlying insulating layer (comprising resin layer 122 ([0031]) and primer layer 119 ([0040]), Fig. 4b) to expose a connection pad (inner conductor 126, Fig. 4b, [0031]), and forming a second seed layer (copper plating layer 130, Fig. 4c, [0002]) and a conductive structure (comprising thin copper layer 118, copper plating layer 130, and lead 134; Fig. 5g, [0002]). Matsuura further teaches that in forming the conductive via (via hole 128 filled with thin copper layer 118, copper plating layer 130, and lead 134, Fig. 5g) and forming the conductive pattern (comprising thin copper layer 118, copper plating layer 130, and lead 134, Fig. 5g), a width of the conductive via (via hole 128 filled with thin copper layer 118, copper plating layer 130, and lead 134, Fig. 5g) decreases towards the active surface (top surface of the inner conductor 126, Fig. 5c).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that forming the sidewalls of the via hole in the method of Chia in view of Hsu-510, as taught by Matsuura, such that the width of the conductive via decreases towards the active surface, provides the benefit that the second seed layer can be prevented from being broken in the via hole, thereby improving effect and reliability of the connection, as evidenced by Ma (US 20210341808 A1, Fig. 5, [0063]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Chia in view of Hsu-510 to form the conductive via as taught by Matsuura, such that the width of the conductive via decreases towards the active surface of the semiconductor chip, to obtain the benefit of covering the sidewalls of the via without interruptions of the second seed layer.
Regarding claim 9, while Chia in view of Hsu-510 teaches the method of claim 1,
Chia and Hsu-510 are silent about material compositions of the first seed layer and second seed layer, and therefore do not teach that the first seed layer includes a same material as the second seed layer.
Matsuura, on the other hand, teaches a method for manufacturing a printed wiring board (printed wiring board, Figs. 4-5, [0026]-[0027]), which is analogous to the method of Chia in view of Hsu-510 in that the method includes forming a via hole (via hole 128, Fig. 4b, [0002]) through a first seed layer (thin copper layer 118, Fig. 4b, [0002]) and an underlying insulating layer (comprising resin layer 122 ([0031]) and primer layer 119 ([0040]), Fig. 4b) to expose a connection pad (inner conductor 126, Fig. 4b, [0031]), and forming a second seed layer (copper plating layer 130, Fig. 4c, [0002]) and a conductive structure (comprising thin copper layer 118, copper plating layer 130, and lead 134; Fig. 5g, [0002]). Accordingly, Matsuura teaches that the first seed layer (thin copper layer 118, 5g) includes a same material (copper) as the second seed layer (copper plating layer 130, Fig. 5g).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the method of Chia in view of Hsu-510 and the method of Matsuura are analogous, and both methods are geared towards forming a connection structure on a contact pad with analogous first seed and second seed layers. Selecting a known material based on its suitability for its intended use (for serving as first and second seed layers in the case of current applications) supports a prima facie obviousness (see MPEP 2144.06). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the same material (copper) for the first seed layer and the second seed layer in the method of Chia in view of Hsu-510, as Matsuura demonstrated that such a material composition is proper for forming the connection structure aimed by the method of Chia in view of Hsu-510.
Regarding claim 11, while Chia in view of Hsu-510 teaches the method of claim 1,
Chia and Hsu-510 are silent about the thickness of the first seed layer and therefore do not teach that a thickness of the first seed layer is in a range from about 0.02 micrometers to about 0.1 micrometers.
Matsuura, on the other hand, teaches a method for manufacturing a printed wiring board (printed wiring board, Figs. 4-5, [0026]-[0027]), which is analogous to the method of Chia in view of Hsu-510 in that the method includes forming a via hole (via hole 128, Fig. 4b, [0002]) through a first seed layer (thin copper layer 118, Fig. 4b, [0002]) and an underlying insulating layer (comprising resin layer 122 ([0031]) and primer layer 119 ([0040]), Fig. 4b) to expose a connection pad (inner conductor 126, Fig. 4b, [0031]), and forming a second seed layer (copper plating layer 130, Fig. 4c, [0002]) and a conductive structure (comprising thin copper layer 118, copper plating layer 130, and lead 134; Fig. 5g, [0002]). Matsuura further teaches that a thickness of the first seed layer (thin copper layer 118, Fig. 5g) is in a range from about 0.02 micrometers to about 0.1 micrometers (claim 6: “thickness of 50 to 2500 nm”, corresponding to 0.05 micrometers to 2.5 micrometers).
Therefore, the range of thickness provided by the prior art overlaps with the range of thickness provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of thickness of the first seed layer can be optimized by routine experimentation for meeting the fine pitch requirements and achieving desired uniformity of in-plane thickness of layer (Matsuura, [0038]). Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, the thickness of the first seed layer to meet the fine pitch requirements and achieve layer uniformity. Consequently, a person of ordinary skill in the art before the effective filing date of the claimed invention would have had a reasonable expectation of success to arrive at a thickness of the second seed layer between about 0.02 micrometers to about 0.1 micrometers in the method of Chia in view of Hsu-510.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chia (US 2009/0090541 A1) in view of Hsu-510 (US 2022/0225510 A1) as applied to claims 1-5 and 7-8 above, and further in view of Kim (US 2012/0161323 A1).
Regarding claim 10, Chia in view of Hsu-510 teaches the method of claim 1,
Chia and Hsu-510 are silent about material compositions of the first seed layer and second seed layer and therefore do not teach that the first seed layer includes tungsten (W), and the second seed layer includes titanium (Ti) or copper (Cu).
Kim, on the other, hand teaches a method for manufacturing a package substrate (substrate 100, Figs. 2-8, [0043]) which includes forming a conductive pattern (circuit pattern layer 400, Fig. 8, [0030]) with a first layer (first seed layer 160, Fig. 8, [0038]) and a second seed layer (first seed layer 160, Fig. 8, [0038]) over connection pads (connection pads 115, Fig. 8, [0031]). Kim further teaches that the first seed layer includes tungsten (W) ([0038]: “The first seed layer 160 may be … a titanium-tungsten (TiW) layer”), and the second seed layer includes titanium (Ti) or copper (Cu) ([0038]: “The second seed layer 170 may be a copper (Cu) layer”).
Kim further disclosed that the first seed layer works as a layer to improve the adhesion between the insulating layer (insulating layer 150, Fig. 8, [0038]) and second seed layer ([0038]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the improved adhesion would particularly benefit the mechanical strength and durability of the metal traces that are not connected to a via hole (see label 252 in Fig. 2G of Chia) in the semiconductor package manufactured by the method of Chia in view of Hsu-510. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the first seed layer from tungsten (W) and the second seed layer from copper (Cu) as taught by Kim to have a semiconductor package with improved adhesion of metal traces.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu-666 (US 2008/0067666 A1) in views of Schrittwieser (US 2011/0203107 A1), Meyer-Berg (US 2011/0193217 A1), and Hsu-510 (US 2022/0225510 A1).
Regarding claim 12, Hsu-666 teaches a method of manufacturing a semiconductor package (circuit board, Figs. 2A-2G, [0021]) that comprises a semiconductor chip (semiconductor chip 22, Fig. 2A, [0028]) comprising an active surface (active surface 22a, Fig. 2A, [0028]) and an inactive surface (inactive surface 22b, Fig. 2A, [0028]) opposite to the active surface (active surface 22a, Fig. 2A), the method comprising:
attaching (Figs. 2A-B, [0028]-[0029]), to the active surface (active surface 22a, Fig. 2A), a film structure (resin coated element 23, Figs. 2A-B) comprising an insulating layer (dielectric layer 231, Figs. 2A-B, [0028]), a first seed layer (metal layer 232, Figs. 2A-B, [0028]), which are sequentially stacked;
forming a via hole (opening 230, Fig. 2D, [0034]) by removing a portion of the insulating layer (dielectric layer 231, Fig. 2D) that does not overlap the first seed layer (thinned metal layer 232' (metal layer 232 is thinned (Figs. 2B-C) and became thinned metal layer 232’), Fig. 2D, [0029]);
forming a second seed layer (conductive layer 24, Fig. 2D, [0034]) on the first seed layer (thinned metal layer 232', Fig. 2D) and the insulating layer (dielectric layer 231, Fig. 2D);
forming a second photoresist pattern (resist 25, Fig. 2E, [0035]) on the second seed layer (conductive layer 24, Fig. 2E); and
forming a conductive via (openings 230 filled with conductive structures 261, Figs. 2F-G, [0036]-[0037]) by filling a space defined by the via hole (opening 230, Figs. 2F-G) with a conductive material (electroplated metal layer 26, Figs. 2F-G, [0036]) and forming a conductive pattern (conductive structures 261, Fig. 2G) by filling a space defined by the second photoresist pattern (pattern of resist 25, Fig. 2F) with the conductive material (electroplated metal layer 26, Fig. 2F).
Hsu-666, however, does not teach
a film structure also comprising a release layer, and a carrier film which are sequentially stacked;
forming a first photoresist pattern on the first seed layer after the release layer and the carrier film are removed;
removing the first photoresist pattern after etching a portion of the first seed layer that does not overlap the first photoresist pattern;
performing a descum process on the first seed layer and the insulating layer in which the via hole is formed.
Schrittwieser, on the other hand, teaches a method (embodiment shown in Figs. 1a-j, but with a film structure (laminate 10) including a carrier layer 26 as shown in Fig. 3, [0034] and [0093]) for integrating an electronic component into a printed circuit board (Figs. 1a-j, [0034]), wherein the method comprises attaching a film structure (laminate 10 with carrier 26, Fig. 1b, [0044]) to the active surface (surface with contacts 6, Fig. 1b, [0044]) of a semiconductor chip (electronic component 4, Fig. 1b, [0044]), a film structure comprising an insulating layer (insulating layer 1, Fig. 1b, [0044]), a first seed layer (conductive layer 2, Fig. 1b, [0041]), a release layer (carrier/protection layer 3, Fig. 1b, [0041]), and a carrier film (carrier 26, Fig. 3, [0093]) which are sequentially stacked.
Schrittwieser further discloses that the release layer (carrier/protection layer) enables protection of the first seed layer (conducting layer) from damage during attachment process ([0029]), and the carrier film (carrier 26) provides mechanical strength to the film structure during attachment process ([0093]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to also include a release layer and a carrier film, as taught by Schrittwieser, in the film structure in the method of Hsu-666, which would protect the first seed layer and give mechanical strength to the whole film structure during attachment process, which would consequently improve the reliability of the method.
Thus, the combination of Hsu-666 and Schrittwieser teaches
a film structure also comprising a release layer, and a carrier film which are sequentially stacked,
and therefore, forming the first photoresist pattern on the first seed layer after the release layer and the carrier film are removed.
The combination of Hsu-666 and Schrittwieser, however, does not teach
forming a first photoresist pattern on the first seed layer after the release layer and the carrier film are removed;
removing the first photoresist pattern after etching a portion of the first seed layer that does not overlap the first photoresist pattern;
performing a descum process on the first seed layer and the insulating layer in which the via hole is formed.
Meyer-Berg, on the other hand, teaches a method (Figs. 3A-M) for manufacturing a fan-out type package (device 300, Fig. 3M, [0050]), wherein forming via holes (Figs. 3H-I, [0044]-[0046]) on to the active surface (surface with the contact elements 13, Fig. 3H, [0023]) of a semiconductor chip (semiconductor chip 12, Fig. 3H, [0023]) comprises
forming a first photoresist pattern (etching mask 40, Fig. 3H, [0044]: “The etching mask 40 may consist of photoresist”) on the first seed layer (metal foil 10, Fig. 3H, [0044]) after the release layer (adhesive tape 21, Fig. 3G, [0043]) and the carrier film (carrier 20, Fig. 3G, [0043]) are removed;
removing the first photoresist pattern (etching mask 40, Fig. 3I-J, [0046]: “stripped away”) after etching a portion of the first seed layer (metal foil 10, Figs. 3I-J) that does not overlap the first photoresist pattern (etching mask 40, Fig. 3I).
The photolithography-based patterning method disclosed by Meyer-Berg is a commonly used technique in semiconductor manufacturing to form vias. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the photolithography-based patterning method, as taught by Meyer-Berg, would be also suitable to form the via hole in the method of Hsu-666 and Schrittwieser. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to incorporate the photolithography-based method of Meyer-Berg into the method of Hsu-666 and Schrittwieser to obtain the predictable result of successfully forming the via hole (see MPEP 2143(I)(D)).
The combination of Hsu-666, Schrittwieser, and Meyer-Berg, however, do not teach
performing a descum process on the first seed layer and the insulating layer in which the via hole is formed.
Hsu-510, on the other hand, teaches a method for manufacturing a circuit board (circuit board 1, Figs. 1-9, [0017]), wherein a via hole (second opening 106, Figs. 2 and 5, [0022]) exposing a contact pad (connection pad 105, Fig. 2, [0018]) is formed through insulating layers (adhesive layer 103 and cover layer 104 Figs. 2 and 5, [0019]). Hsu-510 further teaches, after forming the via hole,
performing a descum process ([0032]: “The residue 24 in the second opening 106 is removed by plasma … to fully expose a surface of the connection pad 105.” [0032]);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that residues might also be present after forming the via holes in the method of Hsu-666 in views Schrittwieser and Meyer-Berg, which might degrade the quality of the layers formed in the following steps of the method. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to perform a descum process, before forming the second seed layer, on the surface of the semiconductor package (including the insulating layer and the first seed layer in which the via hole is formed) to remove the residues formed on the surface after forming the via hole. Thus, the combination of Hsu-666, Schrittwieser, Meyer-Berg and Hsu-510 meets the limitations including
performing a descum process on the first seed layer and the insulating layer in which the via hole is formed.
Regarding claim 13, Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 teaches the method of claim 12, wherein
Hsu-666 further teaches in attaching the film structure (Fig. 2B) to the active surface (active surface 22a, Fig. 2B) of the semiconductor chip (semiconductor chip 22, Fig. 2B), the insulating layer (dielectric layer 231, Figs. 2B) is in a semi-cured state that is a B stage ([0028]: “the dielectric layer 231 is a prepreg”, which is a stage B material).
Regarding claim 14, Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 teaches the method of claim 12, wherein,
Hsu-666 further teaches that in forming the conductive via (openings 230 filled with conductive structures 261, Figs. 2G) and forming the conductive pattern (conductive structures 261, Fig. 2G), a surface (top surface of dielectric layer 231, Fig. 2G) of the insulating layer (dielectric layer 231, Fig. 2G), which is parallel to the active surface (active surface 22a, Fig. 2G), contacts the first seed layer (thinned metal layer 232’, Fig. 2G), and a surface of the insulating layer (surface of the dielectric layer 231 in the opening 230, Fig. 2G), which is not parallel to the active surface (active surface 22a, Fig. 2G), contacts the second seed layer (conductive layer 24, Fig. 2G).
Regarding claim 15, Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 teaches the method of claim 12, wherein,
Hsu-666 further teaches that in forming the conductive via (openings 230 filled with conductive structures 261, Figs. 2G) and forming the conductive pattern (conductive structures 261, Fig. 2G), a side surface of the first seed layer (side surface of thinned metal layer 232’ outside the opening 230, Fig. 2G), a side surface of the second seed layer (side surface of conductive layer 24 outside the opening 230, Fig. 2G), and a side surface of the conductive pattern (side surface of conductive structures 261 outside the opening 230, Fig. 2G) are located on a same plane (a vertical plane in Fig. 2G).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu-666 (US 2008/0067666 A1) in views of Schrittwieser (US 2011/0203107 A1), Meyer-Berg (US 2011/0193217 A1), and Hsu-510 (US 2022/0225510 A1) as applied to claims 12-15 above, and further in view of Oda (US 2011/0143501 A1).
Regarding claim 16, while Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 teaches the method of claim 12,
Hsu-666, Schrittwieser, Meyer-Berg and Hsu-510 are silent about the thickness of the carrier film, and therefore do not teach that a thickness of the carrier film is in a range from about 10 micrometers to about 50 micrometers.
Oda, on the other hand, teaches a method of producing a semiconductor device (Figs. 1a-f, [0017]) wherein a thickness of the carrier film (metal support layer 1, Fig. 1, [0035]) is in a range from about 10 micrometers to about 50 micrometers ([0079]: “about 20 µm to 80 µm”).
Therefore, the range of thickness provided by the prior art overlaps with the range of thickness provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of thickness of carrier film can be optimized by routine experimentation to achieve desired mechanical strength and handling ability given the rigidity of the material (Oda, [0079]-[0080]) (see MPEP 2144.05(II)). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention aiming to use the method of Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 would have had a reasonable expectation to arrive at a thickness of the carrier film in a range from about 10 micrometers to about 50 micrometers, in order to achieve desired mechanical characteristics of the carrier film.
Regarding claim 17, while Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 teaches the method of claim 12,
Hsu-666, Schrittwieser, Meyer-Berg and Hsu-510 do not teach that a thickness of the release layer is in a range from about 0.2 micrometers to about 1 micrometer.
Oda, on the other hand, teaches a method of producing a semiconductor device (Figs. 1a-f, [0017]) wherein a thickness of the release layer (release layer 5, Fig. 1a, [0084]) is in a range from about 0.2 micrometers to about 1 micrometer ([0084]: ”0.1 to 5 µm”).
Therefore, the range of thickness provided by the prior art overlaps with the range of thickness provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of thickness of release film can be optimized by routine experimentation to achieve desired mechanical characteristics (Oda, [0084]: the thickness is selected to prevent the entire wiring substrate from bowing) (see MPEP 2144.05(II)). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention aiming to use the method of Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 would have had a reasonable expectation to arrive at a thickness of the release film in a range from about 0.1 micrometers to about 1 micrometers, in order to achieve desired mechanical characteristics of the release film.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu-666 (US 2008/0067666 A1) in views of Schrittwieser (US 2011/0203107 A1), Meyer-Berg (US 2011/0193217 A1), Hsu-510 (US 2022/0225510 A1), and Kwon (US 2021/0183785 A1).
Regarding claim 18, Hsu-666 (US 2008/0067666 A1) teaches a method of manufacturing a semiconductor package (circuit board, Figs. 2A-2G, [0021]) that comprises a semiconductor chip (semiconductor chip 22, Fig. 2A, [0028]) comprising an active surface (active surface 22a, Fig. 2A, [0028]) and an inactive surface (inactive surface 22b, Fig. 2A, [0028]) opposite to the active surface (active surface 22a, Fig. 2A), the method comprising:
attaching (Figs. 2A-B, [0028]-[0029]), to the active surface (active surface 22a, Fig. 2A), a film structure (resin coated element 23, Figs. 2A-B) comprising a photosensitive insulating layer (dielectric layer 231, Figs. 2A-B, [0028]: “the dielectric layer 231 is a prepreg”, which is a UV sensitive material), a first seed layer (metal layer 232, Figs. 2A-B, [0028]), which are sequentially stacked;
forming a via hole (opening 230, Fig. 2D, [0034]) by removing a portion of the photosensitive insulating layer (dielectric layer 231, Fig. 2D) that does not overlap the first seed layer (thinned metal layer 232' (metal layer 232 is thinned (Figs. 2B-C) and became thinned metal layer 232’), Fig. 2D, [0029]);
forming a second seed layer (conductive layer 24, Fig. 2D, [0034]) on the first seed layer (thinned metal layer 232', Fig. 2D) and the photosensitive insulating layer (dielectric layer 231, Fig. 2D);
forming a second photoresist pattern (resist 25, Fig. 2E, [0035]) on the second seed layer (conductive layer 24, Fig. 2E); and
forming a conductive via (openings 230 filled with conductive structures 261, Figs. 2F-G, [0036]-[0037]) by filling a space defined by the via hole (opening 230, Figs. 2F-G) with a conductive material (electroplated metal layer 26, Figs. 2F-G, [0036]) and forming a conductive pattern (conductive structures 261, Fig. 2G) by filling a space defined by the second photoresist pattern (pattern of resist 25, Fig. 2F) with the conductive material (electroplated metal layer 26, Fig. 2F).
Hsu-666, however, does not teach
an intermediate connection structure having a multilayered structure and surrounding the semiconductor chip;
a release layer, and a carrier film, sequentially stacked;
forming a first photoresist pattern on the first seed layer after the release layer and the carrier film are removed;
removing the first photoresist pattern after etching a portion of the first seed layer that does not overlap the first photoresist pattern;
performing a descum process on the first seed layer and the photosensitive insulating layer in which the via hole is formed.
Schrittwieser, on the other hand, teaches a method (embodiment shown in Figs. 1a-j, but with a film structure (laminate 10) including a carrier layer 26 as shown in Fig. 3, [0034] and [0093]) for integrating an electronic component into a printed circuit board (Figs. 1a-j, [0034]), wherein the method comprises attaching a film structure (laminate 10 with carrier 26, Fig. 1b, [0044]) to the active surface (surface with contacts 6, Fig. 1b, [0044]) of a semiconductor chip (electronic component 4, Fig. 1b, [0044]), a film structure comprising an insulating layer (insulating layer 1, Fig. 1b, [0044]), a first seed layer (conductive layer 2, Fig. 1b, [0041]), a release layer (carrier/protection layer 3, Fig. 1b, [0041]), and a carrier film (carrier 26, Fig. 3, [0093]) which are sequentially stacked.
Schrittwieser further discloses that the release layer (carrier/protection layer) enables protection of the first seed layer (conducting layer) from damage during attachment process ([0029]), and the carrier film (carrier 26) provides mechanical strength to the film structure during attachment process ([0093]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to also include a release layer and a carrier film, as taught by Schrittwieser, in the film structure in the method of Hsu-666, which would protect the first seed layer and give mechanical strength to the whole film structure during attachment process, which would consequently improve the reliability of the method.
Thus, the combination of Hsu-666 and Schrittwieser teaches
a film structure also comprising a release layer, and a carrier film which are sequentially stacked.
The combination of Hsu-666 and Schrittwieser, however, does not teach
an intermediate connection structure having a multilayered structure and surrounding the semiconductor chip;
forming a first photoresist pattern on the first seed layer after the release layer and the carrier film are removed;
removing the first photoresist pattern after etching a portion of the first seed layer that does not overlap the first photoresist pattern;
performing a descum process on the first seed layer and the photosensitive insulating layer in which the via hole is formed.
Meyer-Berg, on the other hand, teaches a method (Figs. 3A-M) for manufacturing a fan-out type package (device 300, Fig. 3M, [0050]), wherein forming via holes (Figs. 3H-I, [0044]-[0046]) on to the active surface (surface with the contact elements 13, Fig. 3H, [0023]) of a semiconductor chip (semiconductor chip 12, Fig. 3H, [0023]) comprises
forming a first photoresist pattern (etching mask 40, Fig. 3H, [0044]: “The etching mask 40 may consist of photoresist”) on the first seed layer (metal foil 10, Fig. 3H, [0044]) after the release layer (adhesive tape 21, Fig. 3G, [0043]) and the carrier film (carrier 20, Fig. 3G, [0043]) are removed;
removing the first photoresist pattern (etching mask 40, Fig. 3I-J, [0046]: “stripped away”) after etching a portion of the first seed layer (metal foil 10, Figs. 3I-J) that does not overlap the first photoresist pattern (etching mask 40, Fig. 3I).
The photolithography-based patterning method disclosed by Meyer-Berg is a commonly used technique in semiconductor manufacturing to form vias. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the photolithography-based patterning method, as taught by Meyer-Berg, would be also suitable to form the via hole in the method of Hsu-666 and Schrittwieser. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to incorporate the photolithography-based method of Meyer-Berg into the method of Hsu-666 and Schrittwieser to obtain the predictable result of successfully forming the via hole (see MPEP 2143(I)(D)).
The combination of Hsu-666, Schrittwieser, and Meyer-Berg, however, do not teach
an intermediate connection structure having a multilayered structure and surrounding the semiconductor chip;
performing a descum process on the first seed layer and the photosensitive insulating layer in which the via hole is formed.
Hsu-510, on the other hand, teaches a method for manufacturing a circuit board (circuit board 1, Figs. 1-9, [0017]), wherein a via hole (second opening 106, Figs. 2 and 5, [0022]) exposing a contact pad (connection pad 105, Fig. 2, [0018]) is formed through insulating layers (adhesive layer 103 and cover layer 104 Figs. 2 and 5, [0019]). Hsu-510 further teaches, after forming the via hole,
performing a descum process ([0032]: “The residue 24 in the second opening 106 is removed by plasma … to fully expose a surface of the connection pad 105.” [0032]);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that residues might also be present after forming the via holes in the method of Hsu-666 in views Schrittwieser and Meyer-Berg, which might degrade the quality of the layers formed in the following steps of the method. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to perform a descum process, before forming the second seed layer, on the surface of the semiconductor package (including the insulating layer and the first seed layer in which the via hole is formed) to remove the residues formed on the surface after forming the via hole. Thus, the combination of Hsu-666, Schrittwieser, Meyer-Berg and Hsu-510 meets the limitations including
performing a descum process on the first seed layer and the photosensitive insulating layer in which the via hole is formed.
The combination of Hsu-666, Schrittwieser, Meyer-Berg and Hsu-510, however, do not teach
an intermediate connection structure having a multilayered structure and surrounding the semiconductor chip.
Kwon, on the other hand, teaches a semiconductor package (semiconductor package 100F, Fig. 13, [0078]) with connection structures (see connection structures in Illustrative Fig. 1, which is an annotated version of Kwon’s Fig. 13) on the active surface (active surface, Illustrative Fig. 1: active surface is the surface with connection electrodes 120P ([0028]) of a semiconductor chip (semiconductor chip 120, Illustrative Fig. 1, [0028]), wherein the semiconductor package (semiconductor package 100F, Illustrative Fig. 1) comprises
an intermediate connection structure (vertical connection structure 110, Illustrative Fig. 1, [0079]) having a multilayered structure (comprising first insulating layer 111a and second insulating layer 111b, Illustrative Fig. 1, [0078]) and surrounding the semiconductor chip (semiconductor chip 120, Illustrative Fig. 1: at left and right sides).
Kwon further discloses that including the connection structures on the front and back surfaces of a semiconductor chip with surrounding intermediate connection structure improves integration density and reliability of the semiconductor package ([0004]), and form reduced area package-on-package structures ([0003], see Fig. 16 as an example). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to manufacture a high-density package -on-package structure would be motivated to apply the method of Hsu-666 in views of Schrittwieser, Meyer-Berg and Hsu-510 to a semiconductor chip integrated with a surrounding intermediate connection structure to form the connection structures on the intermediate connection structure and active side of the semiconductor chip. Thus, the combination of Hsu-666, Schrittwieser, Meyer-Berg, Hsu-510, and Kwon further meets the limitation that the method comprises a semiconductor chip with an intermediate connection structure having a multilayered structure and surrounding the semiconductor chip.
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Regarding claim 19, while Hsu-666 in views of Schrittwieser, Meyer-Berg, Hsu-510, and Kwon teaches the method of claim 18,
Hsu-666, Schrittwieser, Meyer-Berg, and Hsu-510 are silent about an intermediate connection structure and therefore do not teach that the conductive via and the conductive pattern are electrically connected to the intermediate connection structure.
Kwon, on the other hand, teaches that the conductive via and the conductive pattern (conductive structures on the connection electrodes 120P, Illustrative Fig. 1) are electrically connected to the intermediate connection structure (vertical connection structure 110, Illustrative Fig. 1, [00810]: “The wiring layers 112a, 112b, and 112c may provide upper/lower electrical connection paths of the package together with wiring vias 113a and 113b, and may serve to redistribute a connection electrodes 120P.”).
Kwon further discloses that including the connection structures including the intermediate connection structure improves integration density and reliability of the semiconductor package ([0004]), and form reduced area package-on-package structures ([0003], see Fig. 16 as an example). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to manufacture a high-density package-on-package structure would be motivated to apply the method of Hsu-666 in views of Schrittwieser, Meyer-Berg, Hsu-510, Kwon to a semiconductor chip integrated with a surrounding intermediate connection structure, which is electrically connected to the conductive via and the conductive pattern, to provide the benefit of distributing the connections of the semiconductor chip at various locations and thereby increasing the integration density. Thus, the combination of Hsu-666, Schrittwieser, Meyer-Berg, Hsu-510, and Kwon meets all the limitations of claim 19.
Regarding claim 20, while Hsu-666 in views of Schrittwieser, Meyer-Berg, Hsu-510, and Kwon teaches the method of claim 18,
Hsu-666, Schrittwieser, Meyer-Berg, and Hsu-510 are silent about an intermediate connection structure, and therefore do not teach that
the intermediate connection structure comprises:
a plurality of intermediate conductive pattern layers with different vertical levels; and
a plurality of intermediate vias respectively arranged between the plurality of intermediate conductive pattern layers.
Kwon, on the other hand, teaches that
the intermediate connection structure (vertical connection structure 110, Illustrative Fig. 1) comprises:
a plurality of intermediate conductive pattern layers (first insulating layer 111a including the first wiring layer 112a and first wiring vias 113a, and second insulating layer 111b with second wiring layer 112b and second wiring vias 113b, Illustrative Fig. 1, [0078]) with different vertical levels (Illustrative Fig. 1: layers are vertically distributed); and
a plurality of intermediate vias (first wiring via 113as and second wiring vias 113b) respectively arranged between the plurality of intermediate conductive pattern layers (first insulating layer 111a including the first wiring layer 112a and first wiring vias 113a, and second insulating layer 111b with second wiring layer 112b and second wiring vias 113b, Illustrative Fig. 1).
Kwon further discloses that including the connection structures including the intermediate connection structure improves integration density and reliability of the semiconductor package ([0004]), and form reduced area package-on-package structures ([0003], see Fig. 16 as an example). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to manufacture a high-density package-on-package structure would be motivated to apply the method of Hsu-666 in views of Schrittwieser, Meyer-Berg, Hsu-510, Kwon to a semiconductor chip integrated with a surrounding intermediate connection structure comprising a plurality of intermediate conductive pattern layers with different vertical levels, and a plurality of intermediate vias respectively arranged between the plurality of intermediate conductive pattern layers, which would provide the benefit of increasing integration density. Thus, the combination of Hsu-666, Schrittwieser, Meyer-Berg, Hsu-510, and Kwon meets all the limitations of claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin (US 2018/0240683 A1) teaches a wafer level chip packaging method, which is relevant to all claims.
Li (US 2017/0170031 A1) teaches a wafer level chip packaging method, which is relevant to all claims.
Qiu (US 2019/0035642 A1) teaches a chip packaging method, which is relevant to all claims.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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